ATE403905T1 - Speicherbarrieren-stammfunktionen in einer asymmetrischen heterogenen multiprozessorumgebung - Google Patents

Speicherbarrieren-stammfunktionen in einer asymmetrischen heterogenen multiprozessorumgebung

Info

Publication number
ATE403905T1
ATE403905T1 AT05823124T AT05823124T ATE403905T1 AT E403905 T1 ATE403905 T1 AT E403905T1 AT 05823124 T AT05823124 T AT 05823124T AT 05823124 T AT05823124 T AT 05823124T AT E403905 T1 ATE403905 T1 AT E403905T1
Authority
AT
Austria
Prior art keywords
memory
memory barrier
command
bus operation
multiprocessor environment
Prior art date
Application number
AT05823124T
Other languages
English (en)
Inventor
Michael Day
Charles Johns
Peichun Liu
Thuong Truong
Takeshi Yamazaki
Original Assignee
Sony Computer Entertainment Inc
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Computer Entertainment Inc, Ibm filed Critical Sony Computer Entertainment Inc
Application granted granted Critical
Publication of ATE403905T1 publication Critical patent/ATE403905T1/de

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/20Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46Multiprogramming arrangements
AT05823124T 2004-07-29 2005-07-18 Speicherbarrieren-stammfunktionen in einer asymmetrischen heterogenen multiprozessorumgebung ATE403905T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/902,474 US7725618B2 (en) 2004-07-29 2004-07-29 Memory barriers primitives in an asymmetric heterogeneous multiprocessor environment

Publications (1)

Publication Number Publication Date
ATE403905T1 true ATE403905T1 (de) 2008-08-15

Family

ID=35733704

Family Applications (1)

Application Number Title Priority Date Filing Date
AT05823124T ATE403905T1 (de) 2004-07-29 2005-07-18 Speicherbarrieren-stammfunktionen in einer asymmetrischen heterogenen multiprozessorumgebung

Country Status (9)

Country Link
US (1) US7725618B2 (de)
EP (1) EP1782220B1 (de)
JP (1) JP4678623B2 (de)
KR (1) KR100866714B1 (de)
CN (1) CN101052954B (de)
AT (1) ATE403905T1 (de)
DE (1) DE602005008747D1 (de)
TW (1) TWI391826B (de)
WO (1) WO2006040692A1 (de)

Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7200688B2 (en) 2003-05-29 2007-04-03 International Business Machines Corporation System and method asynchronous DMA command completion notification by accessing register via attached processing unit to determine progress of DMA command
US7243200B2 (en) 2004-07-15 2007-07-10 International Business Machines Corporation Establishing command order in an out of order DMA command queue
US7725618B2 (en) 2004-07-29 2010-05-25 International Business Machines Corporation Memory barriers primitives in an asymmetric heterogeneous multiprocessor environment
DE102004046438B4 (de) * 2004-09-24 2006-07-06 Infineon Technologies Ag Vorrichtung zum Steuern des Zugriffs von Verarbeitungseinrichtungen auf Speicher in einem eingebetteten System
US9026744B2 (en) * 2005-03-23 2015-05-05 Qualcomm Incorporated Enforcing strongly-ordered requests in a weakly-ordered processing
US7716387B2 (en) * 2005-07-14 2010-05-11 Canon Kabushiki Kaisha Memory control apparatus and method
GB2433333B (en) 2005-12-13 2011-07-13 Advanced Risc Mach Ltd Distributed direct memory access provision within a data processing system
JP4446968B2 (ja) * 2006-02-22 2010-04-07 シャープ株式会社 データ処理装置
US7917676B2 (en) * 2006-03-10 2011-03-29 Qualcomm, Incorporated Efficient execution of memory barrier bus commands with order constrained memory accesses
US7610458B2 (en) * 2006-04-25 2009-10-27 International Business Machines Corporation Data processing system, processor and method of data processing that support memory access according to diverse memory models
US7454580B2 (en) * 2006-04-25 2008-11-18 International Business Machines Corporation Data processing system, processor and method of data processing that reduce store queue entry utilization for synchronizing operations
US7783817B2 (en) * 2006-08-31 2010-08-24 Qualcomm Incorporated Method and apparatus for conditional broadcast of barrier operations
US8275963B2 (en) * 2008-02-01 2012-09-25 International Business Machines Corporation Asynchronous memory move across physical nodes with dual-sided communication
US8095758B2 (en) * 2008-02-01 2012-01-10 International Business Machines Corporation Fully asynchronous memory mover
US7991981B2 (en) * 2008-02-01 2011-08-02 International Business Machines Corporation Completion of asynchronous memory move in the presence of a barrier operation
US8356151B2 (en) * 2008-02-01 2013-01-15 International Business Machines Corporation Reporting of partially performed memory move
US7941627B2 (en) * 2008-02-01 2011-05-10 International Business Machines Corporation Specialized memory move barrier operations
US8245004B2 (en) * 2008-02-01 2012-08-14 International Business Machines Corporation Mechanisms for communicating with an asynchronous memory mover to perform AMM operations
US8015380B2 (en) * 2008-02-01 2011-09-06 International Business Machines Corporation Launching multiple concurrent memory moves via a fully asynchronoous memory mover
US8327101B2 (en) * 2008-02-01 2012-12-04 International Business Machines Corporation Cache management during asynchronous memory move operations
JP5187038B2 (ja) * 2008-07-15 2013-04-24 セイコーエプソン株式会社 マルチプロセッサシステム及びそれを搭載した流体吐出装置
GB2469299B (en) * 2009-04-07 2011-02-16 Imagination Tech Ltd Ensuring consistency between a data cache and a main memory
US8352682B2 (en) 2009-05-26 2013-01-08 Qualcomm Incorporated Methods and apparatus for issuing memory barrier commands in a weakly ordered storage system
US8997103B2 (en) * 2009-09-25 2015-03-31 Nvidia Corporation N-way memory barrier operation coalescing
US20110119469A1 (en) * 2009-11-13 2011-05-19 International Business Machines Corporation Balancing workload in a multiprocessor system responsive to programmable adjustments in a syncronization instruction
WO2012036954A2 (en) * 2010-09-15 2012-03-22 Rambus Inc. Scheduling amongst multiple processors
US20150033234A1 (en) * 2013-07-23 2015-01-29 Qualcomm Incorporated Providing queue barriers when unsupported by an i/o protocol or target device
CN110795150A (zh) * 2015-07-21 2020-02-14 安培计算有限责任公司 依dmb操作用加载/存储操作实施加载撷取/存储释放指令
KR101892357B1 (ko) * 2016-10-11 2018-08-27 한국과학기술원 실리콘 반도체를 기반으로 하는 광 빔 포밍 네트워크 칩
KR102262209B1 (ko) * 2018-02-09 2021-06-09 한양대학교 산학협력단 더미 입출력 요청을 이용한 배리어 명령 전달 방법 및 그 장치
DE102020127704A1 (de) 2019-10-29 2021-04-29 Nvidia Corporation Techniken zum effizienten transferieren von daten an einem prozessor
US11080051B2 (en) * 2019-10-29 2021-08-03 Nvidia Corporation Techniques for efficiently transferring data to a processor

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5911051A (en) * 1996-03-29 1999-06-08 Intel Corporation High-throughput interconnect allowing bus transactions based on partial access requests
TW320701B (de) * 1996-05-16 1997-11-21 Resilience Corp
US5887134A (en) * 1997-06-30 1999-03-23 Sun Microsystems System and method for preserving message order while employing both programmed I/O and DMA operations
US6209073B1 (en) 1998-04-27 2001-03-27 International Business Machines Corp. System and method for interlocking barrier operations in load and store queues
US6205494B1 (en) 1998-12-18 2001-03-20 Western Digital Corporation Controller with automatic generation of linked list of data transfer descriptors for sequential commands, with linked list being used for execution of sequential data transfers
US6347349B1 (en) * 1998-12-28 2002-02-12 International Business Machines Corp. System for determining whether a subsequent transaction may be allowed or must be allowed or must not be allowed to bypass a preceding transaction
US6647468B1 (en) * 1999-02-26 2003-11-11 Hewlett-Packard Development Company, L.P. Method and system for optimizing translation buffer recovery after a miss operation within a multi-processor environment
US6609192B1 (en) 2000-06-06 2003-08-19 International Business Machines Corporation System and method for asynchronously overlapping storage barrier operations with old and new storage operations
US6738836B1 (en) * 2000-08-31 2004-05-18 Hewlett-Packard Development Company, L.P. Scalable efficient I/O port protocol
US6658520B1 (en) * 2000-09-26 2003-12-02 Intel Corporation Method and system for keeping two independent busses coherent following a direct memory access
US6947049B2 (en) * 2001-06-01 2005-09-20 Nvidia Corporation Method and system for synchronizing updates of vertex data with a graphics processor that is fetching vertex data
US7673304B2 (en) * 2003-02-18 2010-03-02 Microsoft Corporation Multithreaded kernel for graphics processing unit
US8301844B2 (en) * 2004-01-13 2012-10-30 Hewlett-Packard Development Company, L.P. Consistency evaluation of program execution across at least one memory barrier
US7725618B2 (en) 2004-07-29 2010-05-25 International Business Machines Corporation Memory barriers primitives in an asymmetric heterogeneous multiprocessor environment

Also Published As

Publication number Publication date
CN101052954B (zh) 2011-10-19
EP1782220B1 (de) 2008-08-06
JP2008508586A (ja) 2008-03-21
EP1782220A1 (de) 2007-05-09
US7725618B2 (en) 2010-05-25
KR100866714B1 (ko) 2008-11-03
TW200617685A (en) 2006-06-01
JP4678623B2 (ja) 2011-04-27
DE602005008747D1 (de) 2008-09-18
TWI391826B (zh) 2013-04-01
CN101052954A (zh) 2007-10-10
WO2006040692A1 (en) 2006-04-20
KR20070038518A (ko) 2007-04-10
US20060026309A1 (en) 2006-02-02

Similar Documents

Publication Publication Date Title
ATE403905T1 (de) Speicherbarrieren-stammfunktionen in einer asymmetrischen heterogenen multiprozessorumgebung
WO2007078913A3 (en) Cross-architecture execution optimization
ATE407403T1 (de) Bildung einer befehlsreihenfolge in einer nicht sequentiell dma-befehlswarteschlange
DE602006017467D1 (de) Lernsteuerungsvorrichtung, Lernsteuerungsverfahren und Computerprogramm
DE602004029632D1 (de) Kollisionsdetektionsvorrichtung, Kollisionsdetektionsverfahren und Computerprogramm
FI20020847A0 (fi) Menetelmä ja laite valikkotoimintojen käyttämiseksi
DE60336247D1 (de) Bilddatenverarbeitungsverfahren, bilddatenverarbeitungseinrichtung und computerprogramm
ATE433584T1 (de) Verfahren, system und programm zur handhabung von eingabe-/ausgabebefehlen
DE602006001812D1 (de) Speichersteuervorrichtung, Datenverwaltungssystem und Datenverwaltungsverfahren
DE602006008397D1 (de) Speichersteuervorrichtung, Datenverwaltungssystem und Datenverwaltungsverfahren
BRPI0511223A (pt) método para acessar um sistema hospedeiro, sistema hospedeiro e dispositivo de entrada
NO20055468D0 (no) Datakommunikasjonssystem, kommunikasjonsanordning og tilhorende kommunikasjonsprogram
TW200511033A (en) Implementing a second computer system as an interface for a first computer system
ATE516551T1 (de) Vereinigter dma
DE602004025616D1 (de) Einrichtungssteuereinrichtung, -verfahren und -programm
DE60330400D1 (de) Sprachsynthesesystem, Sprachsyntheseverfahren und Rechnerprogramm
TW200602867A (en) Incremental merge methods and memory systems using the same
DE60335192D1 (de) Gui-anwendungs entwicklungs unterstützungseinrichtung, und -verfahren und computerprogramm
BRPI0418204A (pt) dispositivo eletrÈnico equipado com interface de voz, método para executar as configurações do idioma de interface do usuário no dispositivo eletrÈnico, e, programa de computador
EP2053520A4 (de) Informationsverarbeitungsvorrichtung, informationsverarbeitungsverfahren, computerprogramm und halbleiterbauelement
DE602005021098D1 (de) Busverbindungseinrichtung
DE50211638D1 (de) Verfahren, computerprogramm, sowie steuer- und/oder regelgerät zum betreiben einer brennkraftmaschine
DE602005017070D1 (de) Vergleichsverfahren, -system, -computer und -programm
DE602004013472D1 (de) Datenverarbeitungsgerät, - verfahren und -programm
DE602004031566D1 (de) Informationskommunikationssystem, Übertragungsvorrichtung, Übertragungsverfahren und Computerprogramm

Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties