TW200616141A - Strained silicon-on-insulator by anodization of a buried p+ silicon germanium layer - Google Patents

Strained silicon-on-insulator by anodization of a buried p+ silicon germanium layer

Info

Publication number
TW200616141A
TW200616141A TW094122166A TW94122166A TW200616141A TW 200616141 A TW200616141 A TW 200616141A TW 094122166 A TW094122166 A TW 094122166A TW 94122166 A TW94122166 A TW 94122166A TW 200616141 A TW200616141 A TW 200616141A
Authority
TW
Taiwan
Prior art keywords
semiconductor layer
strained
relaxed
layer
insulator
Prior art date
Application number
TW094122166A
Other languages
English (en)
Other versions
TWI359477B (en
Inventor
Thomas N Adam
Stephen W Bedell
Souza Joel P De
Keith E Fogel
Alexander Reznicek
Devendra K Sadana
Ghavam G Shahidi
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of TW200616141A publication Critical patent/TW200616141A/zh
Application granted granted Critical
Publication of TWI359477B publication Critical patent/TWI359477B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76259—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along a porous layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/967—Semiconductor on specified insulator

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Recrystallisation Techniques (AREA)
  • Thin Film Transistor (AREA)
  • Element Separation (AREA)
TW094122166A 2004-07-02 2005-06-30 Strained silicon-on-insulator by anodization of a TWI359477B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/883,887 US7172930B2 (en) 2004-07-02 2004-07-02 Strained silicon-on-insulator by anodization of a buried p+ silicon germanium layer

Publications (2)

Publication Number Publication Date
TW200616141A true TW200616141A (en) 2006-05-16
TWI359477B TWI359477B (en) 2012-03-01

Family

ID=34969794

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094122166A TWI359477B (en) 2004-07-02 2005-06-30 Strained silicon-on-insulator by anodization of a

Country Status (7)

Country Link
US (3) US7172930B2 (zh)
EP (1) EP1779423A1 (zh)
JP (1) JP5089383B2 (zh)
KR (1) KR100961815B1 (zh)
CN (1) CN101120442A (zh)
TW (1) TWI359477B (zh)
WO (1) WO2006003061A1 (zh)

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US8975125B2 (en) * 2013-03-14 2015-03-10 International Business Machines Corporation Formation of bulk SiGe fin with dielectric isolation by anodization
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Also Published As

Publication number Publication date
KR100961815B1 (ko) 2010-06-08
US20060003555A1 (en) 2006-01-05
EP1779423A1 (en) 2007-05-02
US20070111463A1 (en) 2007-05-17
JP5089383B2 (ja) 2012-12-05
WO2006003061A1 (en) 2006-01-12
US7172930B2 (en) 2007-02-06
US20080277690A1 (en) 2008-11-13
KR20070037483A (ko) 2007-04-04
CN101120442A (zh) 2008-02-06
TWI359477B (en) 2012-03-01
JP2008504704A (ja) 2008-02-14
US7592671B2 (en) 2009-09-22

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