TW200616108A - Semiconductor device having flip chip package - Google Patents
Semiconductor device having flip chip packageInfo
- Publication number
- TW200616108A TW200616108A TW093133969A TW93133969A TW200616108A TW 200616108 A TW200616108 A TW 200616108A TW 093133969 A TW093133969 A TW 093133969A TW 93133969 A TW93133969 A TW 93133969A TW 200616108 A TW200616108 A TW 200616108A
- Authority
- TW
- Taiwan
- Prior art keywords
- flip chip
- chip package
- carrier
- semiconductor device
- tested
- Prior art date
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3135—Double encapsulation or coating and encapsulation
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H01L2224/732—Location after the connecting process
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
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- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Wire Bonding (AREA)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW093133969A TWI249796B (en) | 2004-11-08 | 2004-11-08 | Semiconductor device having flip chip package |
US11/267,707 US20060097402A1 (en) | 2004-11-08 | 2005-11-03 | Semiconductor device having flip-chip package and method for fabricating the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW093133969A TWI249796B (en) | 2004-11-08 | 2004-11-08 | Semiconductor device having flip chip package |
Publications (2)
Publication Number | Publication Date |
---|---|
TWI249796B TWI249796B (en) | 2006-02-21 |
TW200616108A true TW200616108A (en) | 2006-05-16 |
Family
ID=36315506
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW093133969A TWI249796B (en) | 2004-11-08 | 2004-11-08 | Semiconductor device having flip chip package |
Country Status (2)
Country | Link |
---|---|
US (1) | US20060097402A1 (zh) |
TW (1) | TWI249796B (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103367272A (zh) * | 2012-03-30 | 2013-10-23 | 株式会社吉帝伟士 | 半导体模块 |
Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4185499B2 (ja) * | 2005-02-18 | 2008-11-26 | 富士通マイクロエレクトロニクス株式会社 | 半導体装置 |
US7364945B2 (en) | 2005-03-31 | 2008-04-29 | Stats Chippac Ltd. | Method of mounting an integrated circuit package in an encapsulant cavity |
SG135066A1 (en) * | 2006-02-20 | 2007-09-28 | Micron Technology Inc | Semiconductor device assemblies including face-to-face semiconductor dice, systems including such assemblies, and methods for fabricating such assemblies |
US7732907B2 (en) * | 2006-05-30 | 2010-06-08 | Stats Chippac Ltd. | Integrated circuit package system with edge connection system |
US8198735B2 (en) | 2006-12-31 | 2012-06-12 | Stats Chippac Ltd. | Integrated circuit package with molded cavity |
US8134227B2 (en) * | 2007-03-30 | 2012-03-13 | Stats Chippac Ltd. | Stacked integrated circuit package system with conductive spacer |
US9330945B2 (en) * | 2007-09-18 | 2016-05-03 | Stats Chippac Ltd. | Integrated circuit package system with multi-chip module |
US7948095B2 (en) * | 2008-02-12 | 2011-05-24 | United Test And Assembly Center Ltd. | Semiconductor package and method of making the same |
US8258015B2 (en) * | 2008-02-22 | 2012-09-04 | Stats Chippac Ltd. | Integrated circuit package system with penetrable film adhesive |
SG177945A1 (en) * | 2008-07-18 | 2012-02-28 | United Test & Assembly Ct Lt | Packaging structural member |
US8304869B2 (en) * | 2008-08-01 | 2012-11-06 | Stats Chippac Ltd. | Fan-in interposer on lead frame for an integrated circuit package on package system |
US8129824B1 (en) * | 2008-12-03 | 2012-03-06 | Amkor Technology, Inc. | Shielding for a semiconductor package |
US8344491B2 (en) * | 2008-12-31 | 2013-01-01 | Micron Technology, Inc. | Multi-die building block for stacked-die package |
US8058715B1 (en) * | 2009-01-09 | 2011-11-15 | Amkor Technology, Inc. | Package in package device for RF transceiver module |
US8143098B2 (en) * | 2009-03-25 | 2012-03-27 | Stats Chippac Ltd. | Integrated circuit packaging system with interposer and method of manufacture thereof |
KR101401708B1 (ko) * | 2012-11-15 | 2014-05-30 | 앰코 테크놀로지 코리아 주식회사 | 반도체 디바이스 및 그 제조 방법 |
US9484281B2 (en) | 2014-08-14 | 2016-11-01 | Qualcomm Incorporated | Systems and methods for thermal dissipation |
JP2020043258A (ja) * | 2018-09-12 | 2020-03-19 | キオクシア株式会社 | 半導体メモリおよびその製造方法 |
TWI832571B (zh) * | 2022-11-21 | 2024-02-11 | 矽品精密工業股份有限公司 | 電子封裝件及其製法 |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5450290A (en) * | 1993-02-01 | 1995-09-12 | International Business Machines Corporation | Printed circuit board with aligned connections and method of making same |
US5655703A (en) * | 1995-05-25 | 1997-08-12 | International Business Machines Corporation | Solder hierarchy for chip attachment to substrates |
US5815372A (en) * | 1997-03-25 | 1998-09-29 | Intel Corporation | Packaging multiple dies on a ball grid array substrate |
US6472471B2 (en) * | 1997-12-16 | 2002-10-29 | Cabot Corporation | Polymeric products containing modified carbon products and methods of making and using the same |
JP3565319B2 (ja) * | 1999-04-14 | 2004-09-15 | シャープ株式会社 | 半導体装置及びその製造方法 |
US6452278B1 (en) * | 2000-06-30 | 2002-09-17 | Amkor Technology, Inc. | Low profile package for plural semiconductor dies |
US6607937B1 (en) * | 2000-08-23 | 2003-08-19 | Micron Technology, Inc. | Stacked microelectronic dies and methods for stacking microelectronic dies |
US6472741B1 (en) * | 2001-07-14 | 2002-10-29 | Siliconware Precision Industries Co., Ltd. | Thermally-enhanced stacked-die ball grid array semiconductor package and method of fabricating the same |
JP4790157B2 (ja) * | 2001-06-07 | 2011-10-12 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US6838761B2 (en) * | 2002-09-17 | 2005-01-04 | Chippac, Inc. | Semiconductor multi-package module having wire bond interconnect between stacked packages and having electrical shield |
US7049691B2 (en) * | 2002-10-08 | 2006-05-23 | Chippac, Inc. | Semiconductor multi-package module having inverted second package and including additional die or stacked package on second package |
JP2004281919A (ja) * | 2003-03-18 | 2004-10-07 | Seiko Epson Corp | 半導体装置、電子デバイス、電子機器、半導体装置の製造方法および電子デバイスの製造方法 |
TWI234250B (en) * | 2004-02-24 | 2005-06-11 | Stack Devices Corp | Semiconductor packaging element capable of avoiding electromagnetic interference and its manufacturing method |
JP2006049569A (ja) * | 2004-08-04 | 2006-02-16 | Sharp Corp | スタック型半導体装置パッケージおよびその製造方法 |
-
2004
- 2004-11-08 TW TW093133969A patent/TWI249796B/zh not_active IP Right Cessation
-
2005
- 2005-11-03 US US11/267,707 patent/US20060097402A1/en not_active Abandoned
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103367272A (zh) * | 2012-03-30 | 2013-10-23 | 株式会社吉帝伟士 | 半导体模块 |
Also Published As
Publication number | Publication date |
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TWI249796B (en) | 2006-02-21 |
US20060097402A1 (en) | 2006-05-11 |
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