TW200540955A - Integrated circuit die and substrate coupling - Google Patents
Integrated circuit die and substrate coupling Download PDFInfo
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- TW200540955A TW200540955A TW094107723A TW94107723A TW200540955A TW 200540955 A TW200540955 A TW 200540955A TW 094107723 A TW094107723 A TW 094107723A TW 94107723 A TW94107723 A TW 94107723A TW 200540955 A TW200540955 A TW 200540955A
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- substrate
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- integrated circuit
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- 239000000758 substrate Substances 0.000 title claims abstract description 43
- 230000008878 coupling Effects 0.000 title claims abstract description 6
- 238000010168 coupling process Methods 0.000 title claims abstract description 6
- 238000005859 coupling reaction Methods 0.000 title claims abstract description 6
- 239000000463 material Substances 0.000 claims abstract description 63
- 238000000034 method Methods 0.000 claims description 14
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 238000001020 plasma etching Methods 0.000 claims description 2
- 238000003825 pressing Methods 0.000 claims 1
- 239000002390 adhesive tape Substances 0.000 description 3
- 239000012530 fluid Substances 0.000 description 3
- 239000010410 layer Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 239000000654 additive Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000011324 bead Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 231100001261 hazardous Toxicity 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 238000010248 power generation Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000004576 sand Substances 0.000 description 1
- 230000001568 sexual effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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- H—ELECTRICITY
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/27—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/1147—Manufacturing methods using a lift-off mask
- H01L2224/1148—Permanent masks, i.e. masks left in the finished device, e.g. passivation layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/27001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
- H01L2224/27003—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for holding or transferring the layer preform
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/271—Manufacture and pre-treatment of the layer connector preform
- H01L2224/2711—Shaping
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
- H01L2224/2743—Manufacturing methods by blanket deposition of the material of the layer connector in solid form
- H01L2224/27436—Lamination of a preform, e.g. foil, sheet or layer
- H01L2224/27438—Lamination of a preform, e.g. foil, sheet or layer the preform being at least partly pre-patterned
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/731—Location prior to the connecting process
- H01L2224/73101—Location prior to the connecting process on the same surface
- H01L2224/73103—Bump and layer connectors
- H01L2224/73104—Bump and layer connectors the bump connector being embedded into the layer connector
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- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
- H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
- H01L2224/83856—Pre-cured adhesive, i.e. B-stage adhesive
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01019—Potassium [K]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Wire Bonding (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Description
200540955 (1) 九、發明說明 【發明所屬之技術領域】 本發明係有關積體電路晶粒與基底耦合。 【先前技術】 積體電路(1C )晶粒會包含與半導體基底整合之電性 元件。IC晶粒也會包含可使電性元件相互電性耦接,以及 Φ 使電性元件電性耦接至外部連接物之導電路徑。晶粒會包 含多層的導電路徑,而每層會藉由層間介電質(inter_ layer dielectric,簡稱ILD ),而與相鄰層分離。ILD會 包含介電常數(k )極低的材料,以使導電路徑之間的電 谷親合與串擾最小。 低k的ILD材料時常會出現熱膨脹係數(a coefficient of thermal expansion,簡稱 CTE)明顯地與其 耦接的其他元件(如會耦接至1C晶粒之IC晶粒的其他元 馨件及1 C基底的元件)不同。此外,低k的IL D材料時常 很易碎。在1C晶粒及/或IC封裝的製造期間,這二種特 性會使低k的ILD材料產生裂痕。 【發明內容】與【實施方式】 1係根據某些實施例之膠帶(tape ) 1的透視圖。膠帶 1包含塡料部分10及塡料部分2〇。塡料部分1〇及2〇會 包含不會流動的塡料。不會流動的塡料可包含低黏性,可 熱聚合的液態樹脂系統,其會包含或不包含流體添加物。 -4 _ 200540955 (2) 非耗盡的例子包含充滿一^氧化砂重達5 0 %的填料’以及 Cookson電子半導體產品的STAYCHIPtm DP-0115。塡料 部分1 〇及2 0可處於非固化、部分固化、及/或完全固化 的狀態中。 塡料部分10會界定開口 15。開口 15會配置成可使電 性互連通過塡料部分10。電性互連會依序使1 c晶粒耦接 至1C基底。此種配置可使ILD機械故障降低,及/或產生 p 高的製造產量。 1C晶粒會置於開口 1 5的一側,並且會耦接至1C晶粒 的1C基底會置於開口 1 5的反側。參考圖1,1C晶粒會置 於部分10「之上」,而1C基底會置於部分1〇「之下」。 根據某些實施例之上述的例子之一例係敘述如下。 塡料部分20會界定開口 25,其功用與塡料部分1〇的 開口 1 5類似。因此,開口 25會使電性互連通過塡料部分 2〇,以使1C晶粒耦接至ic基底。ic晶粒及/或ic基底會 Φ 與經由開口 1 5而通過的電性互連所耦接之1C晶粒及/或
Ic基底相同。底下所述且顯示於圖4及1〇中的實施例包 曰置於專用IC晶粒與〗c基底的專用部分之間的塡料部分 10。 塡料部分1 0係經由耦合3 0而耦接至塡料部分2〇。耦 口 30會包含提供部分1〇與部分2〇有效分離之實際連接 或/、曰包Q材料的貫體區域。根據某些實施例,置於部 h 10與部分2〇之間的材料係與構成部分1〇與部分2〇的 材料不同。 200540955 (3) 在某些實施例中’膠帶1包括額外的塡料部分,其係 耦接至塡料部分i 0及/或塡料部分20。例如,一部分的塡 料會以使部分20親接至部分10的方式,而耦接至部分2〇 的末端2 7。因此,膠帶1會包含一串連接部分的塡料,其 可塗佈捲狀物,或其他適合的塗佈系統。 圖2係繪不根據某些實施例之IC晶粒4 0。IC晶粒4 〇 包含整合的電性元件,並且可使用任何適當的基底材料及 φ 製造技術而製造出來。1C晶粒40會提供一種或多種功能 。在某些實施例中,1C晶粒40包含具有矽基底的微處理 器晶片。 IC晶粒4 0的側面包含電性接點4 4。IC晶粒4 0會包 含覆晶配置,其中,電性元件係整合於1C晶粒40的基底 與電性接點4 4之間的位置中。在某些實施例中,基底係 位於電性元件與電性接點44之間。 電性接點44會包含製造於1C晶粒40上之銅或基於 • 導線的接點。電性接點44會包含控制崩潰晶片接合( Controlled Collapse Chip Connect,簡稱 C4)焊料凸塊。 就此點而言,導電接點44可位於1C晶粒4〇的第一側42 之下而凹進去、與1C晶粒4〇的第一側42齊平、或在IC 晶粒40的第一側42之上而延伸。電性接點44會電性耦 接至電性元件,其會整合至1C晶粒4〇。 圖3係根據某些實施例之1C基底50的側面之圖形。 基底5 G會包含任何陶瓷、有機、及/或其他適合的材料。 基底50可用來傳送1C晶粒40與外部電性組件之間的電 -6 - 200540955 (4) 源及/或I / 〇訊號。基底5 0也可用來將訊號直接傳送到 據某些實施例之1C晶粒40,以及接收來自根據某些實 例之1C晶粒40之訊號。 基底5 0的第一側5 2包含電性接點5 4。電性接點 會包含C4焊料凸塊或電鍍的銅接點。電性接點54可位 基底的第一側52之下而凹進去、與基底的第一側52齊 、或在基底的第一側5 2之上而延伸。雖然圖2及3的 施例係顯不如分別實質上具有正方形或圓形的橫截面之 性接點44及5 4,但是在其他的實施例中,電性接點44 54中的一個或多個會具有不同及/或變化的形狀之橫截 〇 圖4係根據某些實施例的系統6〇之截掉的側面圖 系統60包含塡料部分10、1C晶粒40及1C基底50。系 60還包含電性互連70,其會通過部分1〇的開口 15,並 其會耦接電性接點4 4及電性接點5 4。塡料部分1 0可將 φ 性互連7 0封入內部,因此可保護電性互連7 〇免於暴露 危害的環境。此外,在1C晶粒40附著於基底50的期 ,當加熱系統60時,1C晶粒40的CTE會與基底50 CTE不同,以使1C晶粒40上,產生過度的壓力。塡料 可藉由吸收某些壓力及/或使壓力分散而遠離1C晶粒 來應付此不匹配。 圖5係根據某些實施例之製程8 〇的圖形。製程8 0 藉由一個或多個製造裝置來進行,並且所有或一部分的 程80可以手動的方式來進行。在製造系統60之前,製 根 施 54 於 平 實 電 及 面 〇 統 且 電 在 間 的 10 40 可 製 程 200540955 (5) 80可隨時進行。 最初,在8 2,不會流動的塡料會塗佈在載體上。不會 流動的塡料會根據任何目前,或之後已知的系統(包含線 性泵浦及旋轉式正排量泵浦)來塗佈。塗佈過之不會流動 的塡料可爲根據各種實施例之非固化、部分固化或完全固 化。部分或完全固化可以疊層、板及/或膠帶的形式來塗 佈。 p 圖6係根據某些實施例之具有塡料部分i 〇的載體90 之側面圖。載體9 0會包含不會流動的塡料會塗佈於其上 之任何表面。在某些實施例中,塡料部分1 〇會塗佈爲氣 泡(bead ),或使用合適工具,而使其變平爲圖6中所顯 示的輪廓。在82之前,塡料部分10及/或載體90可使用 化學及/或基於電漿的技術而預先洗淨。 在8 4,會將塡料壓在樣板上,而在塡料中,產生開口 。圖7係靠近塡料〗〇的樣板丨〇 〇之截掉的側面圖,以產 # 生根據某些實施例之開口。樣板1 〇 〇包含凸出物1 1 0,以 產生開口及嘴120,而在84的期間,產生塡料1〇的範圍 。根據84的某些實施例,載體90會朝著樣板1〇〇移動, 及/或樣板100會朝著載體90移動。 凸出物1 1 0會爲中空,以聚集在84期間,「移出」 的部分塡料1 〇。在84之前,塡料1 〇會部分固化,而能完 全將材料自開口會產生於其中之區域移除。根據某些實施 例’塡料1 0會剛好在84之前加熱,而產生希望程度的固 化。 200540955 (6) 圖8係在84之後,塡料部分10與載體90之截掉的 側面圖。圖8係顯示藉由樣板1 00所產生的開口 1 5。在 84之後,開口 1 5可使用如電漿蝕刻的蝕刻技術而精製出 來。 在86,此部分的塡料會附著於1C基底。在86之前, 1C基底會預先洗淨。根據某些實施例,此部分的塡料會疊 層到1C基底。在86之後,此部分的塡料及1C基底會再 φ 次地洗淨。 圖9係根據某些實施例,在8 6之後之塡料部分1 〇與 1C基底50之截掉的側面圖。圖9係顯示電性互連70,其 會在86之前或之後,形成於基底50上。電性互連70會 通過開口 15之各自的一個,並且用來使1C基底50耦接 到1C晶粒。 在製程80之後,1C晶粒會附著於圖9的系統。根據 某些實施例,1C晶粒係使用拾取和放置機器的放置頭,而 φ 放置於其上。在放置1C晶粒之前,此種機器可使IC晶粒 的電性接點與電性互連7 0中的各自一個對準。圖4係繪 示所導致的系統之一例。 然後,此種系統會進行加熱,以形成IC晶粒與I c基 底之間的整體電性互連,及/或塡料1 0的完全固化部分。 在固化之後,部分塡料1 〇會形成惰性保護聚合物。塡料 部分1 0也會包含流體添加物,以還原1C晶粒與電性互連 70的電性接點之金屬表面。在某些實施例中,在加熱之前 ,流體也可以或選擇地放置於金屬表面上。 -9 - 200540955 (7) 圖1 〇係根據某些實施例的系統2 0 0之側面圖。系統 200會包含桌上型計算平台的組件。系統2〇〇包含如上述 的系統60、記憶體220及主機板23 0。系統200中的系統 60會包含處理器。 系統60的1C基底50會包含多層的導電跡線(trace )’其係藉由數層的介電材料而分離,並且藉由形成於介 電材料內的貫孔(via )而電性耦接。此種跡線及貫孔可 φ 使穿透孔接腳21 0電性耦接至電性接點5 4。因此,接腳 2 1 0可傳送訊號,如1C晶粒40與外部裝置之間的電源及 I/O訊號。接腳210可直接安裝於主機板23 0上,或裝入 插槽(未顯示),其會依序直接安裝於主機板23 0。主機 板23 0會包含記憶體匯流排(未顯示),其會電性耦接至 接腳210及記憶體220。因此,主機板23 0會使記憶體 220電性耦接至1C晶粒40。記億體220可包含用於儲存 資料之任何類型的記憶體,如單一資料率隨機存取記憶體 φ 、雙倍資料率隨機存取記憶體、或可程式唯讀記憶體。 在此所述的許多實施例僅作爲說明之用。在此所述的 各種特性不需全部一起使用,並且那些特性中的任一個或 多個可倂入單一實施例中。某些實施例會包含在此所述之 任何目前或之後已知的形式之元件。因此’熟習此項技術 者將會從此說明中瞭解另外的實施例可以各種修改及變化 來實施。 【圖式簡單說明】 -10- 200540955 (8) 圖1係根據某些實施例之二部分的塡料之透視圖; 圖2係根據某些實施例之1C晶粒的底視圖; 圖3係根據某些實施例之1C基底的上視圖; 圖4係根據某些實施例的系統之截掉的側面圖; 圖5係根據某些實施例之製程的圖形; 圖6係根據某些實施例之一部分的塡料與載體之側面 圖; 圖7係根據某些實施例之一部分的塡料、載體、以及 樣板之側面圖; 圖8係根據某些實施例之一部分的塡料與載體之截掉 的側面圖; 圖9係根據某些實施例之一部分的塡料與IC基底之 截掉的側面圖;以及 圖1 〇係根據某些實施例之系統的圖形。 【主要元件符號說明】 1 膠帶 10 塡料部分 15 開口 20 塡料部分 25 開口 27 末端 30 1C晶粒 40 1C晶粒 -11 - 200540955
(9) 42 第一側 44 電性接點 50 1C基底 52 第一側 54 電性接點 60 系統 70 電性互連 80 製程 90 載體 100 樣板 110 凸出物 120 嘴 200 系統 2 10 穿透孔接腳 220 記憶體 230 主機板
Claims (1)
- 200540955 (1) 十、申請專利範圍 1 · 一種晶粒賴合裝置,包括: 預先形成的塡料的第一部分,其界定開口,該等開口 係用以使電性互連通過,以使積體電路晶粒耦合至一基底 的一部份。 2·如申請專利範圍第1項之裝置,更包括: 預先形成的塡料的第二部分,耦合至該塡料的第一部 # 份’該第二部分的塡料係界定第二開口,該等第二開口使 第二電性互連通過,以使第二積體電路晶粒耦合至基底的 第二部分。 3 .如申請專利範圍第2項之裝置,更包括一預先形 成薄片的塡料,包含該第一部分及該第二部分。 4 ·如申請專利範圍第2項之裝置,更包括一預先形 成膠帶的塡料,包含該第一部分及該第二部分。 5 ·如申請專利範圍第1項之裝置,更包括: φ 該部分基底。 6 ·如申請專利範圍第5項之裝置,更包括: 該積體電路晶粒。 1'如申請專利範圍第1項之裝置,更包括: 該積體電路晶粒。 8.如申請專利範圍第1項之裝置,該塡料包括: 未流動的塡料。 9· 一種晶粒耦合方法,包括: ^造用以界定開1U之一預先形成的部分塡料,該等開 -13· 200540955 (2) 口係使電性互連通過,以使積體電路晶粒耦合至部分基底 〇 10. 如申請專利範圍第9項之方法,其中製造該部分 包括: 將該塡料壓在開口的樣板上,以產生該等開口。 11. 如申請專利範圍第1 0項之方法,其中製造該部 分更包括: 將該等開口進行電漿蝕刻,進一步產生該等開口。 1 2 ·如申請專利範圍第9項之方法,更包括: 將該塡料附著於該基底。 1 3 ·如申請專利範圍第1 2項之方法,更包括: 使用通過該等開口之電性互連,以將該基底耦合至該 積體電路晶粒。 1 4 · 一種電子系統,包括: 微處理器,包括: 積體電路晶粒; 基底;以及 預先形成的部分塡料,預先形成以界定開口,該等開 □用以使電性互連通過,以使該積體電路晶粒耦合至該基 底;以及 雙倍資料率記憶體,耦合至該微處理器。 1 5 ·如申請專利範圔第1 4項之系統,該塡料包括: 未流動的塡料。 16.如申請專利範園第1 4項之系統, -14- 200540955 (3) 該積體電路晶粒包括第一複數個電接點; 該基底包括第二複數個電接點;以及 該等電接點使該第一複數個電接點耦合至該第二複數 個電接點。-15-
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US6924171B2 (en) * | 2001-02-13 | 2005-08-02 | International Business Machines Corporation | Bilayer wafer-level underfill |
US20020162679A1 (en) * | 2001-05-04 | 2002-11-07 | Nael Hannan | Package level pre-applied underfills for thermo-mechanical reliability enhancements of electronic assemblies |
US7047633B2 (en) * | 2003-05-23 | 2006-05-23 | National Starch And Chemical Investment Holding, Corporation | Method of using pre-applied underfill encapsulant |
US20050082650A1 (en) * | 2003-10-21 | 2005-04-21 | Kooi Chee C. | Integrated circuit packaging system |
-
2004
- 2004-03-23 US US10/807,022 patent/US20050212105A1/en not_active Abandoned
-
2005
- 2005-03-14 TW TW094107723A patent/TWI294638B/zh not_active IP Right Cessation
- 2005-03-14 WO PCT/US2005/008604 patent/WO2005101479A1/en active Application Filing
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8981548B2 (en) | 2007-05-25 | 2015-03-17 | Stats Chippac Ltd. | Integrated circuit package system with relief |
Also Published As
Publication number | Publication date |
---|---|
WO2005101479A1 (en) | 2005-10-27 |
US20050212105A1 (en) | 2005-09-29 |
TWI294638B (en) | 2008-03-11 |
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