TW200535071A - Ready-for-dispatch packaging for semiconductor wafers, and method for the ready-for-dispatch packaging of semiconductor wafers - Google Patents

Ready-for-dispatch packaging for semiconductor wafers, and method for the ready-for-dispatch packaging of semiconductor wafers Download PDF

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Publication number
TW200535071A
TW200535071A TW094112501A TW94112501A TW200535071A TW 200535071 A TW200535071 A TW 200535071A TW 094112501 A TW094112501 A TW 094112501A TW 94112501 A TW94112501 A TW 94112501A TW 200535071 A TW200535071 A TW 200535071A
Authority
TW
Taiwan
Prior art keywords
container
sheath
packaging
containers
semiconductor wafers
Prior art date
Application number
TW094112501A
Other languages
Chinese (zh)
Other versions
TWI284624B (en
Inventor
Helmut Schwenk
Friedrich-Georg Hohl
Nathalie Lecompte
Oliver Ruscitti
Original Assignee
Siltronic Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE200410019664 external-priority patent/DE102004019664B4/en
Application filed by Siltronic Ag filed Critical Siltronic Ag
Publication of TW200535071A publication Critical patent/TW200535071A/en
Application granted granted Critical
Publication of TWI284624B publication Critical patent/TWI284624B/en

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/673Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere using specially adapted carriers or holders; Fixing the workpieces on such carriers or holders
    • H01L21/6735Closed carriers
    • H01L21/67366Closed carriers characterised by materials, roughness, coatings or the like
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/673Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere using specially adapted carriers or holders; Fixing the workpieces on such carriers or holders
    • H01L21/6735Closed carriers
    • H01L21/67369Closed carriers characterised by shock absorbing elements, e.g. retainers or cushions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/673Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere using specially adapted carriers or holders; Fixing the workpieces on such carriers or holders
    • H01L21/6735Closed carriers
    • H01L21/67389Closed carriers characterised by atmosphere control
    • H01L21/67393Closed carriers characterised by atmosphere control characterised by the presence of atmosphere modifying elements inside or attached to the closed carrierl

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Packaging Frangible Articles (AREA)
  • Packages (AREA)

Abstract

The invention reltes to a ready-for-dispatch packaging for semiconductor wafers, comprising (a) a closeable plastic container which is loaded with the semiconductor wafer and has a lid and a body, a seal between the lid and the body and a particle filter which is integrated in the container and allows the exchange of gas between the interior space of the container and the external environment of the container; (b) a first sheath made from plastic, which surrounds the container and bears closely against the container tests with the aid of reduced pressure; (c) means for binding moistures; (d) a second sheath made from coated plastic, with a coating which blocks the passage of moisture and bears tests closely against the first sheath and against the container with the aid of reduced pressure; (e) shock-absorbing elements which embed the sheathed container in a positive-fitting manner; and (f) an outer packaging which surrounds the double-sheathed and embedded container in a positive-fitting manner. The invention also relates to a method for the ready-for-dispatch packaging of semiconductor wafers in a packaging of this type.

Description

200535071 九、發明說明: 【發明所屬之技術領域】 半導體晶圓通常係由製造商發貨至買受人所在地。在長程運 輸期間必須加以覆蓋而且運輸工具必須經常變換。所以,該等敏 感之半導體晶圓極易遭到損壞。甚至雖無刮傷或破裂所引起之可 見損壞,雜質亦會對該等半導體晶圓造成不良影響或甚至使其無 法充作預期用途,例如:電子元件之製造。 【先前技術】· 美國專利6,1:31,739之申請專利範圍一項有關許多裝 有半導艎晶圓之容器之減震包裝專利,該減震包裝包括兩個泡沫 塑膠半殼且具有若干凹槽,該等凹槽可以完全合適之方式將該等 容器納入。在特殊工業界,可商購之容器習稱"前啟運輸箱 "(FOSBs)。舉例言之,美國專利加6,581,264中曾述及此種 類型之容器。 此種類型之減震包裝便於減低運輸期間半導體晶圓遭受機 械損害之風險。 【發明内容】 本發明之内容係一種半導體晶圓即期發貨包裝及在包裝作 業中實施半導體晶圓即期發貨包裝之方法。 本發明之目的係提供一種半導體晶圓即期發貨包裝,該即期 發貨包裝可進一步減低知害之風險並可實質上破保其中所運輸之 半導體晶圓自容器内取出時之情況實質上可對應於裝入該容器時 6 200535071 之半導體晶圓之情況。 本發明之技術内容係一半導體晶圓即期發貨包裝,其中包括 a) —可關閉塑膠容器,該可關閉塑膠容器内裝有半導體晶圓且 具有一護蓋、一本體,該護蓋與該本體之間有一密封栓及一微粒 過濾器,該微粒過濾器係整合在該容器内,且可使該容器内部空 間與該容器外部環境間實施氣體交換作用; _ b) —塑膠質第一鞘套,該鞘套環繞著該容器並藉助於減壓緊靠 在該容器上; d) 用以結合水氣之裝置; e) 一塗覆塑膠質之第二鞘套,利用一塗層該第二鞘套阻止水氣 之通過並藉助於減壓而緊靠該第一鞠套及倚靠該容器; f) 減震性元件類,該等元件係以完全合適之方式嵌入該經勒套 之容器内;及 • g)-外包裝’該外包裝以完全合適之方式環繞著該經雙重鞠套 及嵌入之容器。 本發明之另一技術内容係如申請專利範圍第丄' 2、3或4 項在包裝内實施半導體晶@即期發s包裝之方法,該方法包含下 列諸步驟: a) 清洗及烘乾許多容器類,該等容器形成一批量; b) 分析該批中之每個容器是否魏粒類、金屬類及有機物質類 所引起之雜質存在; 7 200535071 c) 若分析結果顯示各個雜質類低於所界定之極限值,將半導體 晶圓類裝入該批之其他容器内,並用護蓋類將該等容器關起來; d) 用該第一鞘套將該等容器套起來並在該第一鞠套内產生一 減壓直至該第一鞘套緊靠在該等容器上; e) 用該第二個鞘套將該等業經套起來之諸容器套起來,並在該 第二鞘套内產生一減壓直至該第二鞘套緊靠在該等業經套起來之 0 容器上; f) 至少於該等容器與該第一鞘套之間(於步驟d)期間)或於該 等業經套起來之諸容器與該第二鞘套之間(於步驟e)期間)送入 用以結合水氣之裝置; g) 將該等雙重套起來之容器嵌入減震諸元件内;及 h) 將該等業經雙重套起來及業經嵌入之容器包裝在該外包裝 内並將該外包裝關閉;或若步驟b)内所做之該等分析顯示各個雜 Φ 質並非完全低於所界定之極限值,則與本批之其他諸容器形成一 個新批,繼續實施步驟a)。 【實施方式】 本發明之包裝特別適於發貨半導體晶圓類,尤其適於發貨直 徑最低為300公厘之珍半導體晶圓類。其特別顯著之事實是··可 有效地保護該包裝内之半導體晶圓免於遭受振動所引起之損害及 免於任何類型外來物質所造成之污染。再者,該包裝之結構可使 該等半導體晶圓在自容器内取出時免於導致該等半導艘晶圓受到 污染。 8 200535071 明。考用x圖不該包裝特性之圖式將本發明作更詳細之說 半導趙晶圓類!係、位於可商購之塑膠容器2内該容器2包 -本體3及-護蓋4。適當之塑膠以聚碳酸醋⑽、聚對苯二 甲酸丁一醇g日(PBT)、聚婦彈性體類(p卿及聚乙基乙稀(咖) 為佳。本體3與護蓋4之間最好裝一密封栓(尤以一密封環5更 鲁佳卜以防開關護蓋4時因摩擦產生微粒並形成一屏障以阻擋外界 微粒之進人》該谷器2提供容納許多(通常為Μ個)半導體晶圓1 工門舉例β之’該等半導體晶u間隔規律、於具有側面導引 條片之狹槽内’且通常係藉簧片使其保持垂直站立位置,在護蓋 關閉後該等簧片即與護蓋結合成—個紐。再者,該容器2具有 至夕-個可通氣之開口,該開σ可將—留存微粒之過漶器6封閉 起來《該開口可設在該容器之護蓋4或本體3内。 • 該容器2至少係由兩個鞘套套起來。該第一鞘套7 (該鞘套7 係直接倚靠在該容器上,且以透明塑膠膜質者為佳,尤以聚乙烯 更佳。該膜最好用可以增加撕裂及穿刺抗力之塗層予以加強。尤 以包括一聚醯胺(ΡΑ)層或聚對苯二甲酸乙二醇酯(ρΕΤ)層或該 兩層之組合體更佳。該第二勒套8係由一經塗覆之塑膠所組成, 該經塗覆之塑膠亦以聚乙烯(ΡΕ)為佳,該塗層可增加機械強度 (尤其可增加撕裂及穿刺抗力),且形成一對抗外界水氣之屏障。 其中以塗鋁之塑膠膜為佳,尤以用可以增加撕裂及穿刺抗力之外 9 200535071 層予以額外增強之此類薄膜更佳。該外層以由聚醯胺(pA)或聚對 苯二甲酸乙二醇醋(PET)或該兩層之組合艘所組成為佳。為防止 内部水氣,裝一可結合水氣之裝置9 ,尤以一個或更多個充以可 萃取水氣之紙質或其他材料之小包為佳。該結合水氣裝置9最好 配置在第一鞘套與第二鞘套之間以吸收經由第一鞘套7擴散之水 氣。即使該裝置釋放出微粒亦不受影響,蓋因該等半導艘晶圓工 ,仍繼續受到容器2及第一鞘套7之保護。但,除容器2與第一鞘 套7之間之外,亦可以再增加或變通之方式配置該結合水氣裝置 9。該兩個鞠套及容器可各自設置標蕺。 該容器内部與(一方面)容器2及第一鞠套7間之空間及(另 一方面)與第一鞘套7及第二鞘套8間之空間有一壓力差,所以該 等鞠套可與該容器或彼此之間緊靠。如此亦可防止該等元件因其 變形以及業經稍套容器與該等元件間之可能相對運動(總是會產 齡生微粒)造成損傷。該壓力差以高達50毫巴為佳。最好有兩個減 震元件10置於稍套容器之相對兩側。該等減震元件10最好係由 泡沫塑膠或具有類似特性之材料所組成,尤以由聚乙稀(pp)、聚 苯乙烯(PS)或聚胺基甲酸酯(PU)製之減震元件更佳。該等元件具 有若干凹槽,該業經鞘套之容器係以完全適合之方式嵌入該等凹 槽内。該等元件之外尺寸對應於外包裝11之内尺寸。同樣以完全 適合之方式,該外包裝11將該等元件10及嵌入其内之勒套容器 2元全包袠起來。所以在運輸該等半導體晶圓1期間該容器2或 10 200535071 元件10不可能在外包裝11内發生移動。該外包裝最好係由硬紙 板材料或輕金屬製成。該外包裝之尺寸最好加以適當選擇俾如此 即可立即發貨且(也許)可堆放在活動貨架上。 在所述即期發貨包裝内該等半導體晶圓係以兩種方式加以 保護免受水氣之作用,亦即内部藉結合水氣之裝置9及外部藉該 第二鞘套8,該第二鞘套8形成一屏障以防止水氣之入侵。對防 _ 止微粒入侵所實施之特別保護作用係由該容器2之護蓋4及本體 3間之密封環5及由該容器壁内之過濾器(該過濾器可阻止微粒6 穿過)提供。對防止半導體晶圓受到有機物質、微量金屬及微粒污 染之保護作用係由使用不引起任何污染之容器及鞘套材料所提 供。有關該容器該保護作用係加以嚴格測試。該項測試方法係本 發明方法之一部分,以下將作更詳細之說明。 在該谷器裝入半導體晶圓之前,先將其加以清洗及烘乾。實 • 施清洗之方式是:充以清洗劑之浸沒浴或喷灑清洗劑在該容器上 之裝置。該清洗作用之實施最好歷經一限定之時段並在控制之外 界情況下,尤以業經設定限定溫度及大氣相對濕度之第10級或以 下之清洗室更佳。一經通過品質管制,容器内僅裝入半導體晶圓。 品質管制包括:微粒、微量金屬、微量離子及微量有機雜質之分 析,以及(也許)損傷及缺點之目視檢查,唯獨在分析及檢查結果 顯示未超過所定極限值及無損傷及缺點之情況下始算合格。藉分 析作用所實施之品質管制係對代表一批相同容器類之一個容器實 11 200535071 施。若此一品質管制結果係無不合格者,即可容許該批之其他容 器裝入半導體晶圓類。㈣’該批之其他容器必須再加以清洗及 烘乾或(也許)將其剔除不予進一步處理。 下列不應超過之極限值適用於: a) 液相微粒計數(LPC)試驗,其中將該容器充以無微粒超純水 並使其在一樞軸上旋轉,之後取出5〇毫升之試樣,並利用一可商 麟之雷射散射光量測裝置檢查微粒之存在(液相微粒計數,Lpc): 若測定直徑>1微米之微粒,以低於5〇個微粒為佳,尤以低 於10個微粒更佳; 右測定直徑>0·3微米之微粒,以低於1〇〇〇個微粒為佳, 尤以低於100個微粒更佳; 若測定直徑>0· 2微米之微粒,以低於2〇〇〇個微粒為佳, 尤以低於200個微粒更佳; b) 微量金屬及金屬離子試驗,其中將該容器充以5Q毫升無任 何雜質之超純水並使其在-純上旋轉,並_於ICp.(感應 偶合電衆-質譜儀)或藉助於CE (毛細管電泳)將該試樣加以分析·· 在藉ICP-MS測定時,金屬之總量至多為ι〇〇奈克,尤以至 多工〇奈克更佳; 在藉CE測定時,離子之總量至多為2〇〇奈克,尤以至多ι〇〇 奈克更佳; c) 有機雜質試驗,其中將容器材料加熱至高溫,藉氣相色譜法 12 200535071 將逸出之氣態有機雜質(例如:ε-氨基己内醯胺,四氫呋喃)加以 分析: 在藉氣相色譜法測定時,有機雜質之總濃度<S〇個百萬分 點,尤以<5個百萬分點更佳(以受測容器材料之重量為基準)。 將半導體晶圓類裝入容許裝貨之容器内並予以關閉。此項工 作最好藉助於一機器人。之後用第一鞘套將該容器加以鞘套,(也 許)於該容器與該鞘套之間放置一水氣萃取包,將該鞘套内部之壓 力予以減低並將該鞘套加以溶焊。該容器内出現之氣體環境最好 包括:空氣、氮、一惰性氣體或前述諸氣體之任何預期混合物。 之後,將該業經鞘套一次之容器再用第二鞘套將其鞘套加以熔 焊,(也許)於第一及第二鞠套之間放置一水氣萃取包,將第二鞘 套内之壓力減低並將該第二鞘套加以熔焊。該第二鞘套内存在之 氣體環境最好包括:空氣、氮、一惰性氣體或該等氣體之任何預 期混合物。將依照上述方式業經鞘套兩次之容器置入減震元件 内,將如此形成之包裝包入該外包裝内並將該外包裝關閉。 該即期發貨包裝之品質管制及結構可確保收貨人能將性能 對應於裝入容器時性能之半導體晶圓自包裝中取出。再者,該收 貨人對有關該等半導體晶圓之打開包裝仍具有極大之彈性。舉例 言之,即使在清潔室環境之外仍可移除外包裝,該等減震元件及 該第二鞘套。但,該容器之第一鞘套及尤其該容器之護蓋應在收 貨人所在地之清潔室内移除。 13 200535071 本發明可防止在該等半導體晶圓運輸期間有足夠量之揮發 性雜質凝結在半導趙晶Η上而對隨後電子元件(尤其線寬低於 ο·ι微米之電子耕)之製造工作產生不良影響。而且亦防止有殘 留水氣凝結下來(該凝結下來之殘留水氣同樣地對電子元件之製 造造成問題)。同時亦防止該等半導體晶圓在運輸期間受到來自包 裝之微粒污染,該項污染將同樣對電子元件之製造造成問題。再 者,尤其在包裝期間使用減壓可防止該容器因含有空氣而對外包 裝作相對運動,以致在有運輸引發振動之情況下,導致該等半導 體晶圓跳出簧片固定器,並以不適當之方式變得脆弱(尤其在邊緣 區内),因而增加發生破裂之風險(尤其在電子元件製造中實施有 關熱處理期間)。該無任何活動間隙之包裝亦可防止運輸期間對該 等鞠套造成損傷,因該等損傷可在打開包裝時對該等半導體晶圓 造成污染。 本發明確保:由外界物質所引起、呈局部化光散射點形式 (LPD,光點缺陷)、直徑超過〇·〇5微米、其中在該等半導體晶 圓包裝之前每個側面具有低於1〇個缺陷之半導體晶圓污染,即使 在該等半導體晶圓業經運輸及打開包裝之後亦不超過該標準。 14 200535071 【圖式簡單說明】 第1圖:本發明包裝特性之示意圖。200535071 IX. Description of the invention: [Technical field to which the invention belongs] Semiconductor wafers are usually shipped from the manufacturer to the buyer's location. It must be covered during long-haul transportation and the means of transport must be changed frequently. Therefore, these sensitive semiconductor wafers are easily damaged. Even though there is no visible damage caused by scratches or cracks, impurities can adversely affect these semiconductor wafers or even render them unfit for their intended use, such as the manufacture of electronic components. [Prior art] · US patent 6,1: 31,739 patent application scope a patent for shock-absorbing packaging of many containers containing semiconducting holmium wafers, the shock-absorbing packaging includes two foam plastic half shell Grooves which can incorporate the container in a completely suitable manner. In special industries, commercially available containers are commonly referred to as " front-open shipping containers " (FOSBs). By way of example, this type of container is described in U.S. Patent No. 6,581,264. This type of shock-absorbing packaging facilitates reducing the risk of mechanical damage to the semiconductor wafer during transportation. [Summary of the Invention] The content of the present invention is a method for immediate shipment of semiconductor wafers and a method for implementing immediate shipment of semiconductor wafers in packaging operations. The purpose of the present invention is to provide a spot shipment package for semiconductor wafers, which can further reduce the risk of knowing the damage and can substantially guarantee the condition of the semiconductor wafers transported therefrom when taken out of the container. The above corresponds to the case of a semiconductor wafer when the container is loaded. The technical content of the present invention is a semiconductor wafer immediate shipment package, which includes a) a plastic container that can be closed, the semiconductor container with a semiconductor wafer and a protective cover, a body, the protective cover and There is a sealing plug and a particulate filter between the body, the particulate filter is integrated in the container, and the gas exchange function can be implemented between the internal space of the container and the external environment of the container; _ b) — plastic first A sheath that surrounds the container and abuts against the container by means of decompression; d) a device for binding water and gas; e) a second plastic-coated sheath, which uses a coating to The second sheath prevents the passage of water and gas and abuts against the first sheath and against the container by means of decompression; f) shock-absorbing elements, which are fully embedded in the Lele sleeve. Inside the container; and • g)-Outer packaging 'The outer packaging surrounds the double sleeved and embedded container in a completely suitable manner. Another technical content of the present invention is a method for implementing a semiconductor crystal @ Simultaneous packaging in a package, such as item 丄 '2, 3, or 4 of the scope of the patent application, which method includes the following steps: a) cleaning and drying many Containers, these containers form a batch; b) Analyze whether each container in the batch has impurities caused by granules, metals and organic substances; 7 200535071 c) If the analysis results show that each impurity is lower than Defined limit values, the semiconductor wafers are packed into other containers of the batch, and the containers are closed with a cover; d) the containers are sheathed with the first sheath and placed in the first A decompression occurs in the jumbo until the first sheath abuts against the containers; e) the second sheath is used to enclose the containers of the warp and put in the second sheath Create a decompression until the second sheath abuts on the 0 containers of the warp sheaths; f) at least between the containers and the first sheath (during step d)) or between the warp sheaths The sleeved containers are sent between the second sheath (during step e)). A device for binding water and gas; g) the double sleeved containers are embedded in the shock absorbing elements; and h) the double sleeved and embedded containers are packaged in the outer package and the outer The package is closed; or if the analysis performed in step b) shows that each impurity is not completely lower than the defined limit value, form a new batch with other containers in this batch and continue to step a). [Embodiment] The packaging of the present invention is particularly suitable for the shipment of semiconductor wafers, and is particularly suitable for the shipment of rare semiconductor wafers with a diameter of at least 300 mm. Its particularly remarkable fact is that it can effectively protect the semiconductor wafers in the package from damage caused by vibration and from contamination by any type of foreign substances. Furthermore, the structure of the package prevents the semiconductor wafers from being contaminated when the semiconductor wafers are removed from the container. 8 200535071 Ming. Examining the present invention in more detail using the X-character pattern that should not be used for packaging characteristics. It is located in a commercially available plastic container 2. The container 2 includes a body 3 and a protective cover 4. Suitable plastics include polycarbonate, polybutylene terephthalate (PBT), polywomen elastomers (Ping and polyethylen (Ca)). Body 3 and cover 4 It is best to install a sealing bolt (especially a sealing ring 5 is more robust to prevent particles from being generated due to friction when the cover 4 is switched on and to form a barrier to prevent outside particles from entering). For M) semiconductor wafers 1 example of the gate β, "These semiconductor crystals are regularly spaced in a slot with side guide strips", and are usually held in a vertical standing position by means of a reed. After closing, the reeds are combined with the cover to form a button. In addition, the container 2 has a ventilated opening, and the opening σ can close the filter 6 that retains particles. The opening Can be placed in the container's cover 4 or body 3. • The container 2 is sheathed by at least two sheaths. The first sheath 7 (the sheath 7 rests directly on the container and is made of transparent plastic Film quality is preferred, especially polyethylene. The film is best coated with a coating that increases resistance to tearing and puncture Strong. Especially includes a polyamine (PA) layer or a polyethylene terephthalate (ρET) layer or a combination of the two layers. The second sleeve 8 is made of a coated plastic The coated plastic is preferably polyethylene (PE). The coating can increase the mechanical strength (especially the resistance to tear and puncture), and form a barrier against external moisture. A plastic film of aluminum is preferred, especially such films that can increase the tear and puncture resistance in addition to the 200535071 layer. The outer layer is made of polyamide (pA) or polyethylene terephthalate. Alcohol vinegar (PET) or a combination of these two layers is preferred. To prevent internal moisture, install a device capable of combining moisture 9, especially one or more paper or other filled with extractable moisture A small bag of material is preferred. The combined water and gas device 9 is preferably disposed between the first sheath and the second sheath to absorb the moisture diffused through the first sheath 7. Even if the device releases particles, it is not affected. Gein, these semi-conductor wafermakers, continue to be protected by container 2 and first sheath 7. However, in addition to the space between the container 2 and the first sheath 7, the combined water and gas device 9 may be further added or modified. The two sleeves and the container may be provided with labels. The inside of the container and ( On the one hand, there is a pressure difference between the space between the container 2 and the first holster 7 and (on the other hand) the space between the first sheath 7 and the second holster 8, so these holsters can be connected to the container or This is to prevent damage to these components due to their deformation and possible relative movement between the slightly covered container and these components (always producing aging particles). The pressure difference is as high as 50 mbar as It is best to have two shock-absorbing elements 10 on opposite sides of a slightly covered container. The shock-absorbing elements 10 are preferably composed of foam plastic or a material with similar characteristics, especially polyethylene (pp ), Polystyrene (PS) or polyurethane (PU) shock absorber. The components have a number of grooves into which the sheathed container is fitted in a perfectly suitable manner. The outside dimensions of these components correspond to the inside dimensions of the outer package 11. Also in a completely suitable manner, the outer package 11 encloses the components 10 and the sleeve container embedded therein. It is therefore impossible for the container 2 or 10 200535071 to move the semiconductor wafer 1 within the outer package 11 during the transportation of the semiconductor wafers 1. The outer package is preferably made of cardboard or light metal. The size of the outer packaging is preferably selected so that it can be shipped immediately and (maybe) stacked on a moving shelf. The semiconductor wafers in the immediate shipment package are protected from the effects of water and gas in two ways, that is, internally by a device 9 that combines water and gas and externally by the second sheath 8. The two sheaths 8 form a barrier to prevent the intrusion of moisture. The special protection effect against the intrusion of particles is provided by the sealing ring 5 between the cover 4 and the body 3 of the container 2 and the filter in the container wall (the filter can prevent the particles 6 from passing through). . The protection of semiconductor wafers from organic substances, trace metals and particulates is provided by the use of containers and sheath materials that do not cause any contamination. The protective effect of the container is rigorously tested. This test method is part of the method of the present invention and will be described in more detail below. Before the valley device is loaded into the semiconductor wafer, it is cleaned and dried. • The method of cleaning is: an immersion bath filled with cleaning agent or a device sprayed with cleaning agent on the container. The implementation of this cleaning effect preferably lasts for a limited period of time and under controlled external conditions, especially a cleaning room that has been set at a level 10 or below of the limited temperature and relative atmospheric humidity. Once the quality control is passed, only the semiconductor wafer is placed in the container. Quality control includes: analysis of particulates, trace metals, trace ions, and trace organic impurities, and (maybe) visual inspection of damage and defects, only if the analysis and inspection results show that the specified limits are not exceeded and there are no damage and defects Qualified at the beginning. The quality control implemented by analysis is implemented on a container representing a batch of the same container type. If there is no unqualified result in this quality control, other containers in the batch can be allowed to be loaded into the semiconductor wafer type. ㈣ ’The other containers in the batch must be washed and dried or (perhaps) rejected for further processing. The following limit values that should not be exceeded apply: a) Liquid particle count (LPC) test, in which the container is filled with particle-free ultrapure water and allowed to rotate on a pivot, and then 50 ml of the sample is taken out And use a commercially available laser scattered light measuring device to check the presence of particles (liquid phase particle count, Lpc): If the diameter is> 1 micron, it is better to use less than 50 particles, especially More than 10 particles are more preferable; right measurement particle diameter> 0.3 micron particles, preferably less than 10000 particles, especially less than 100 particles; if the measurement diameter> 0 · 2 Micron particles, preferably less than 2000 particles, especially less than 200 particles; b) Trace metal and metal ion test, in which the container is filled with 5Q ml of ultrapure water without any impurities And make it rotate on pure, and analyze the sample in ICp. (Inductively coupled electro-mass spectrometer) or with CE (capillary electrophoresis). When measuring by ICP-MS, the total metal The amount is at most ιιο nanometer, especially the most at most 0 nanogram; when measured by CE, the total amount of ions is at most 200 nanograms, especially at least 2.00 nanograms; c) Organic impurity test, in which the container material is heated to a high temperature, and the gaseous organic impurities that escape (for example: ε- Aminocaprolactam, tetrahydrofuran) for analysis: when measured by gas chromatography, the total concentration of organic impurities < S0 million points, especially < 5 million points The weight of the container material is used as the basis. The semiconductor wafers are placed in a container that can be loaded and closed. This work is best done with the help of a robot. After that, the container is sheathed with a first sheath, and (perhaps) a water vapor extraction bag is placed between the container and the sheath, the pressure inside the sheath is reduced, and the sheath is melt-welded. The gas environment present in the container preferably includes air, nitrogen, an inert gas, or any desired mixture of the foregoing gases. After that, the sheathed container was welded with a second sheath, and (maybe) a water vapor extraction bag was placed between the first and second sheaths, and the second sheath was placed inside. The pressure is reduced and the second sheath is welded. The gaseous environment present in the second sheath preferably includes air, nitrogen, an inert gas or any desired mixture of these gases. The container, which has been sheathed twice in the manner described above, is placed in the shock absorbing element, the packaging thus formed is enclosed in the outer packaging, and the outer packaging is closed. The quality control and structure of the immediate shipment package can ensure that the consignee can remove the semiconductor wafer with the performance corresponding to the performance when it is loaded into the container. Furthermore, the consignee still has great flexibility in unpacking the semiconductor wafers. For example, the outer packaging, the shock absorbing elements and the second sheath can be removed even outside the clean room environment. However, the first sheath of the container and especially the cover of the container should be removed in a clean room at the place of the consignee. 13 200535071 The present invention can prevent a sufficient amount of volatile impurities from condensing on the semiconducting semiconductor wafer during the transportation of these semiconductor wafers to manufacture subsequent electronic components (especially electronic farming with line widths below ο · ι microns). Work has an adverse effect. It also prevents residual moisture from condensing (the condensed residual moisture also causes problems for the manufacture of electronic components). It also prevents these semiconductor wafers from being contaminated with particles from the packaging during transportation, which will also cause problems in the manufacture of electronic components. Furthermore, the use of decompression, especially during packaging, can prevent the container from moving relative to the outer package due to the inclusion of air, which may cause these semiconductor wafers to jump out of the reed holders in the event of vibrations caused by transportation, and make it inappropriate. The method becomes fragile (especially in the marginal area), thereby increasing the risk of cracking (especially during the relevant heat treatment in the manufacture of electronic components). The packaging without any moving gap can also prevent damage to these sleeves during transportation, as these damages can cause contamination of these semiconductor wafers when the packaging is opened. The invention ensures that: caused by foreign matter, in the form of localized light scattering dots (LPD, light point defects), the diameter is more than 0.05 micrometers, wherein each side of the semiconductor wafer before the packaging has less than 1〇 Contamination of a defective semiconductor wafer does not exceed this standard even after the semiconductor wafer industry is transported and unpacked. 14 200535071 [Brief description of the drawings] Figure 1: Schematic diagram of the packaging characteristics of the present invention.

元件編號說明: 1 半導體晶圓 2 容器 3 本體 4 護蓋 5 密封環 6 過滤·器 7 第一稍套 8 第二鞘套 9 結合水氣裝置(包) 10 減震元件 11 外包裝 15Component number description: 1 semiconductor wafer 2 container 3 body 4 cover 5 seal ring 6 filter · filter 7 first sleeve 8 second sheath 9 combined with water and gas device (package) 10 shock absorber 11 outer package 15

Claims (1)

200535071 十、申請專利範圍: 1. 一種半導體晶圓即期發貨包裝,其中包括 a) 一可關閉塑膠容器,該可關閉塑膠容器内裝有半導體晶圓且 具有-護蓋一本體’該護蓋與該本想之間有—密封栓及一微粒 過濾器,該微粒過遽器係整合在該容器内,且可使該容器内部命 間與該容器外部環境間實施氣體交換作用; 籲⑴-塑膠質第-稍套’該鞘套環繞著該容器並藉助於減壓緊靠 在該容器上; c) 用以結合水氣之裝置; d) 一塗覆塑膠質之第二鞘套,利用一塗層該第二鞘套阻止水氣 之通過並藉助於減壓緊靠該第一鞘套及倚靠該容器; e) 減震性元件類,該等元件係以完全合適之方式嵌入該經鞘套 之容器内;及 鲁f)-外包裝’該外包裝以完全合適之;5Γ式魏著該經雙重勒套 及嵌入之容器。 2·如申請專利範圍項之包裝’其中該第一稍套係透明者。 3*如申請專利範圍第1或2項之包裝,其中該第二鞘套具有一 防撕裂之外塗層。 、 4·如中請專利範圍第1>2或3項之包裝,其中第—勒套與第 稍套及第一勒套外界環境間之減壓量高達毫巴。 5· 一種在如申請專利範圍第1、2、3或4項之包裝中實施半導 200535071 趙晶圓即期發貨包裝之方法,其中該方法包含下列諸步驟: ^ 許多容器類,該等容器形成一批量; M 每個抑是否有微粒類、金相及有機物質類 所引起之雜質存在; 〇若分析結果顯示各個雜質類低於所界定之極限值,將半導體 晶圓類裝人該批之其他容如,並用護蓋類將該等容關起來; d) 用該第-鞠套將該等容器套起來並在該第一鞠套内產生一 減壓直至該第一鞘套緊靠在該等容器上; e) 用該第二個勒套將該等業經套起來之諸容器套起來,並在該 第二勒套内產生-減壓直至該第二鞘套緊靠在該等業經套起來之 容器上; 至夕於該等a器與該第—勒套之間(於步驟⑴朗)或於該200535071 10. Scope of patent application: 1. A semiconductor wafer immediate shipment package, which includes a) a closeable plastic container, which contains a semiconductor wafer and has a protective cover and a body. There is a sealing plug and a particulate filter between the cover and the original idea. The particulate filter is integrated in the container, and allows gas exchange between the internal life of the container and the external environment of the container. -A plastic cap-a little sleeve; the sheath surrounds the container and abuts against the container by means of decompression; c) a device for binding water and gas; d) a plastic-coated second sheath, Using a coating of the second sheath to prevent the passage of water vapor and abutting against the first sheath and leaning against the container by means of decompression; e) shock-absorbing elements, which are fully embedded in the Inside the sheathed container; and Lu f)-Outer packaging 'The outer packaging is completely suitable; 5' Wei Wei writes the double sleeved and embedded container. 2. As for the package of the scope of patent application, wherein the first set is transparent. 3 * The packaging according to item 1 or 2 of the patent application scope, wherein the second sheath has a tear-resistant outer coating. 4. Packaging as described in item 1 or 2 of the patent scope, where the decompression between the first and second sleeves and the first and second sleeves is as high as mbar. 5. · A method for implementing semiconducting 200535071 Zhao wafer immediate shipment packaging in a package such as the scope of application for patents 1, 2, 3, or 4, wherein the method includes the following steps: ^ Many containers, such containers are formed One batch; M each, whether there are impurities caused by particulates, metallographic and organic substances; 〇 If the analysis results show that each impurity class is lower than the defined limit value, the semiconductor wafers are loaded into the batch. Other contents, such as, use a cover to close the contents; d) use the first sleeve to cover the containers and generate a decompression in the first sleeve until the first sheath is abutted against On the containers; e) use the second sleeve to wrap the containers of the warp and create and decompress in the second sleeve until the second sheath is abutted against the warp On the container that was put up; either between the a device and the first-leg cover 等業經套起來之諸容器與該第二勒套之間(於步称e)期間)送入 用以結合水氣之裝置; g)將該等雙重套起來之容器喪入減震諸元件内及 ⑴將該等業經雙重套起來及業經嵌入之容器包裝在該外包裝 :並將該;或若㈣b) _之料分析顯示各個雜 f並非完全低於所界定之極限值,與本批之其他諸抑形成一個 新批,繼續實施步驟a)。 其中下列諸極限值係針對步 6·如申請專利範圍第5項之方法, 称b)内所實施之分析而規定者·· 17 200535071 a) 在液相微粒計數(LPC)試驗内: 若測定直徑>1微米之微粒,數目低於50個微粒; 若測定直徑>0.3微米之微粒,數目低於1000個微粒; 若測定直徑>0.2微米之微粒,數目低於2000個微粒; b) 在微量金屬及金屬離子試驗中: 在藉ICP-MS測定時,金屬之總量至多為100奈克; 在藉CE測定時,離子之總量至多為200奈克; c) 在有機雜質試驗中: 在藉氣相色譜法測定時,有機雜質之總濃度<50個百萬分點 (以受測容器材料之重量為基準)。 18The containers that are put together by the industry and the second cover (during step e) are fed into a device for combining water and gas; g) the double-covered containers are buried in the shock-absorbing elements And ⑴ pack the industry and double-embedded containers in the outer packaging: and analyze the material; if ㈣b) _ shows that each miscellaneous f is not completely lower than the defined limit value, and Others form a new batch and continue with step a). The following limit values are specified for the analysis performed in step 6 as described in step 5 of the scope of patent application, called b). 17 200535071 a) In the liquid particle count (LPC) test: If the diameter is> 1 micron, the number is less than 50 particles; if the diameter is> 0.3 μm, the number is less than 1000 particles; if the diameter is> 0.2 μm, the number is less than 2000 particles; b ) In the trace metal and metal ion test: when measured by ICP-MS, the total amount of metal is up to 100 ng; when measured by CE, the total amount of ions is up to 200 ng; c) in the organic impurity test Middle: When measured by gas chromatography, the total concentration of organic impurities < 50 million points (based on the weight of the container material being tested). 18
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