TW200531167A - Method of manufacturing a semiconductor device and method of etching an insulating film - Google Patents

Method of manufacturing a semiconductor device and method of etching an insulating film Download PDF

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TW200531167A
TW200531167A TW094103575A TW94103575A TW200531167A TW 200531167 A TW200531167 A TW 200531167A TW 094103575 A TW094103575 A TW 094103575A TW 94103575 A TW94103575 A TW 94103575A TW 200531167 A TW200531167 A TW 200531167A
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TW094103575A
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Tadahiro Ohmi
Tetsuya Goto
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Tadahiro Ohmi
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
    • H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
    • H01L21/31138—Etching organic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Plasma & Fusion (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Description

200531167 九、發明說明： 【發明所屬之技術領域】 法。本發明係關於包含絕緣層_製程之半導體裝置的製造方 【先前技術】 在半導體裝置之製程中，必鉄要 裝置製造場效電晶體的情形；;°例如，以半導體 層間絕緣膜之材料的石夕氧化膜的絕緣膜、:將線時’在如 此時，在接觸孔底部之接=^線; ，與接觸徑成反比而上升。因此，隨阻ί 一定的 面積體化愈進展，接觸徑會微小化 麻=之被細化、 升傾向。特別是，接觸孔葬“ ^。，觸孔底σΡ之電阻率有上 化膜之爛作完而矽底材露出ΐ吊:矽成:為氧 子照射树底材，在此情況下 不純物的简有 iD = Λ，若在此p+層進行離子照射的話，由非活 使P層向P層接近。在此情況下，妙底材之電阻率則會 曰 如此，用以防止因離子照射造成矽底材電阻率之上 礒^顺導人損壞除去製程的方法，此方法係經過接觸孔姓 t光阻除去S程之後，將毅非雜化後之猶層细化學乾 虫刻除去，然後再度為了在高濃度摻雜不純物而進行注入離 子’更進行活化退火之方法。 另外’關顧靖決隨著電阻率上升而來之問題的1他先前 技術，有人提議零損壞2階段蝕刻，例如，、、The Ninth
Symposium on Semiconductor Manufacturing, Proceeding of ISSM2000, pp.102-105, Tokyo, September 2000”（以下稱先前技術 200531167 υ。此域歸紐之離子照射觸，且 間，將接觸孔之％%，設定自給偏a電壓（ν γ、_;加餘刻日守 6ίη來進一仃細，將接觸孔剩餘之10%設定為Vdp - l50v來進 5〇〇v 〜— 行I虫刻 CO、0 而 ，此時用以激發電漿所使用之導入氣體為Xe、 c4、f8 【發明内容】 發明所欲解決之問顆 上述之先前2個解決方式中，在細後除 ίί;之:f物，·質、活化退火、若再加上於此等;i:的i 羊備％間）會增加，而造成成本增大之問題。 ，一 ίΐΐ損壞2階段钱刻，依照本案發日月人等之研究、 =驗使用包3在先前技術！所記載之碳（c) =以零損壞2階段侧進行接觸孔之形成時，發覺產生了種^ 茂^先’若將接觸孔之90%，以一500〜—6_之自給偏壓帝 i二刻’且將氧化膜剩餘之1G%設定為以一 i辟χ t人發'見：剩餘ι〇%之氧化膜_時，在接觸孔之 離ΐ之率較大之碳的碳氟化合物系自由基不受高能量 敍刻氣體if f ’直齡積在㈣。吾人魏其結果是： 的象:?ϊίΐ接觸孔之底部，而是含有很多附著機率比碳小 勺氣之自由基述擇性地到達接觸孔之底部。 底材材露㈣，發酬謂躺孔底料歸成防止石夕 低材又離子衝擊之堅固碳氟化合物膜的現象。 刻，進行㈣崎，魏材何職地會· 之餘刻速；^ t材之侧選擇比（氧化膜之朗速率/石夕底材 200531167 比且她，編阻選擇 導體防止彻被不希望地侧的半 物膜本係提供在接觸孔底部有效地形成碳氟化合 造方法及射彳方法觸孔底部之€_變化的半導體裝置之製 解決問顥之丰埒 • g依照本發明，在包含藉由反應性離子蝕刻在絕缘膜將接觸π nr;?:導體裝置之製造方法或= 1第率定以 j程後;由開口在底材露出前實施，可得到丄二以上 供給量至少與—方面相異之組成及供給量之氣 為特徵的半導體裝置之製造方法或絕緣膜： 該接觸⑽形成於場效μ體之雜領域錢極領域 一方面之上的絕緣膜亦可。 、主夕 魯 又，該絕緣膜係矽氧化膜亦可。 供給在該第2製程將該供給氣體之 或是該供給氣體包含含有C和F之氣體與氧（〇2)，在 氧之供給量減至比該第1製程少，或在該第2製程將含 和F之氣體的供給量減至比該第i製程少，或將兩方減各少 該供給氣體包含含有C和F之氣體與氧，在該第2製程 含C*F之氣體與該氧之組成令其由該第丨製程變化亦可。、匕 該開口之最後的深度之一部份，例如至9〇%為止，在該第i 7 200531167 製程進行侧，之後再進行 物之厚度（第2製程比較難附著(費日d或壁面堆積 決定即可。主要在於做完蝕 姑之保護等之均衡來 製程即可。 練表面露出之前城成第2 佳，嫩 ;的厚;;以對：： 之^方用氣置 法:伴途中’改變該氣體之= 導體裝置之製造方法或材表面之狀態下令侧結束的半 材量的至少-方面之氣體的_可防止該底 本發明係藉由反應性離子_ 碳氟化合物膜。在此情況下，由於接觸 的之不^ 【實施方式】 里ϋί—施發明之晕佬形熊 先，用以容易理解本發明，說明關於本發明之原理。 +若參照圖1，顯示在高速蝕刻模式（Vdc=—550V)中矽氧化 ，之侧速輪c5f8流量之關係。在QF8添加氧（〇2)作為添加 氣體’顯不改變當該〇2之流量與C#8之流量時的矽氧化膜之蝕刻 速率（nm/分）。在圖例中，將〇2之流量*〇sccm改變為2.5、5、 8 200531167 QF8流量與#刻速率之關係各以曲線cl〜C5 分流動之流量。啦即為—分鐘標準狀態之氣體在1立方公 以上二率在~分程度 又，如曲線c5所一 n 一 寸C5lV"iLi必須在lOsccm以上。 以上。作、出你Ϊ不，2=15SCCm時，C#8流量則必須在8SCCm 擇比合ί化^ 2流量若超過10s_程度的話，對光阻選 =他:程度^進仰賴刻時，只要設定明=收咖、〇2 V)進仃蝕刻。此時，句合 v vac-〜 碳的碳氟化合物_自由基，不受高能量著2率大之 有很多附著機^^==^=孔底部，此，含 矽底材露a時形成無法形射防止底部’ 化合物膜之狀態。 7抵材被離子衝擊的堅固碳氟 在猓法形成堅固的碳氟化合物膜之狀 石夕底材也會侧，才發覺縣確保 g 的話’ 的活，碳氟化合物膜對側壁之堆積也會減少。 將c#8減少 因此，本案發明人等研討關於用以在接 ，化合物膜之方法’清楚了解在接觸孔底部以的 流量=光是變更自給偏_，而是變更供給氣物 將此列入考慮，供給氣體之_、流量可選擇對側壁之碳氣 200531167 班======== 若參照圖2，顯示Vdc= ~200V日本，料古广λ v 孔側壁之魏化合無_積速率i c i 之接觸 顯示在QF8戶斤添加〇2流量為tt、、;在圖士2， c5F8流量與魏化合物膜之堆積厚度（⑽）的Z H = cal、ca2、ca3、ca4)。|虫刻日專η在社細、 ’、（各在曲線 所需時間。對侧奴堆積物的厚度為 為接觸孔直徑之約1G%以下的話，碳之 達接觸孔底部，在接觸孔底部形成碳氟化ij 被離子衝擊。 w朕保邊矽底材不 0、、,t^tjV在圖2中，藉由將明流量設定為6SCCm以下， 2肌里為3〜5sccm (曲線ca3、ca4)，可將堆積厚产 以下。又，若將c5f8流量降至4sccm的話，由改變又〇2之法旦= J:由進行低糊，可將接觸:底部用堅固 歸納上述結果，將c5f8流量以版em，在光 化程度地將〇2流量設定為10sccm程 i二匕不曾劣 =流f，更用以保_底材亦可用減少〇2流量來 ^ 方法，可進行不需極端地增長钱刻時間，且 生二二此 ，。如此，零損壞纖非只是改變決 壓電壓，氣體組成（流量）亦同時非改變不可。b原之自給偏 以下，使用圖面說明本發明之實施形態。 在圖3 ’騎使用於本伽實麵之^應性離子 Rea—Etching (舰）用的微波電漿處理裝置之概略構成。 10 200531167 10 ^ 8 實現該處理室10 基板12之保持W ^ 板12在的Ϊ里_㈣台14上之被處理基 質所成之多數開耗電介 通過封環形成。更在該喷淋板20之外板2〇 數之開口邱151 =成有/、充電漿激發氣體之空間23，各該複 通過給通㈣ 基板在處理室^之魏板Μ與被處理 此時，將上部之喷淋杯〜28。此亦稱為下段喷淋板， 之料處職^給 放二、2;ΐ㈡1，ΓΓί喷淋板28下部設置多數喷嘴或由氣體 通二； 在被板f28#之喷嘴29向被處理基板12放射之處理氣體 200531167 淋板28間之空間向下段喷琳板28與被處理基板12間之 動。因此’由於可抑止處理氣體流人下段噴淋板28與被處 12間之空間，故可防正產生曝晒於高密度f漿之不要的離解二 <實施例1> 本實施例1係在圖4所示之P通道場效電晶體之製 發明之例。 ♦ 亦即’圖示之P通道場效電晶體在其表面所形成之絕緣膜 37，具有在祕觸孔錢極接麻各細彡狀領域巾光阻圖 所形成之光阻38。具體的說，圖示之p通道場效電 在〇
型石夕基板3G所形成之料31_成的源、祕領在P :之源極領域33、汲極領域34做成p—矽領域3〇1與〆矽領域3〇2 一層構^，源極領域33與汲極領域34間設置閘極絕緣膜35。 極絶緣朕35之上形成有閘極36。在此例中，閘極％之側面 面用絕緣膜覆蓋。更，源極領域33、祕領域34及_3 石夕氧化膜等之層間絕緣膜37所覆蓋，在層間絕緣膜37上雇 極領域33、汲極領域34之部分有施以開口之光阻％沉積著二"、 片3〇m構f之^造途/的p通道場效電晶體多數形成之矽晶 片3〇作為圖3之被處理基板π放置於保持台Μ上。*，源 域33與沒極領域34之ρ+石夕3〇2係2xl〇2〇cm_3之載流子濃度。居、 間絕緣膜37係用矽氧化膜構成，厚度是1//m。 曰 若和圖3—起參照的話，將晶片（圖4之3〇) 12放置於保持 台14後，通過上段喷淋板2〇導入將用以電漿激發之氣體 460sccm’ 由下段喷淋板 28 之 Ar、C5F8、02 各為 40sccm、l〇sccm、 lOsccm，壓力設定為40mT〇rr。 、其次，藉由無圖示之微波振盪器，將頻率2.45GHz之微波供 電給圖3所示之輪射槽孔天線27，來激發電漿，其次，藉由連接 該保持台14之RF電源21，將RF電力500W施加於該保持台14, 將自給偏壓電壓以絕對值令其產生550V程度，用高速蝕刻^式進 12 200531167 行Μ刻。 率’例如使用450kHZ或但並非限定於此頻 極領域34之上會形成接觸孔4卜42之—。在領域33、汲 =孔41、42之-部份，其深接 〜下奴賀淋板28供給之處理氣體的組成由誃+由 〇2 各改變成 40sccm、5sccm、3sccm，rie士 .1 5 8、 自給偏壓電壓之絕對值為雇_叫，減少奸電力，設定 昭Η ΐΓί 1ί L進行零損壞侧120秒，開口接觸孔41、幻（參 开接觸孔41、42底部亦即Ρ+石夕302上，如圖6所示， 合物膜45V简載流子的骑由離子 仙ΪΛ’由該上段喷淋板2〇將ΑΓ氣體660sccm，由該下段喷 ' 二Ar、〇2各供給40、lOsccm’將處理室10之麗力設定為 ，在該輕射槽孔天線27供給_微波，激發電裝3〇秒， 二ίΪ3阻38、該碳說化合物膜45、及無圖示之該接觸孔之側 土梢破堆積之碳氟化合物膜（參照圖7)。 製程中，也除去在ρ+矽3〇2表面堆積之該碳氟化合物膜 =^除去後該〆矽302表面係直接曝晒在電漿。然而，由於此時 知、射之電聚係電子溫度leV以下之低溫，硼不會由晶格點位置 =離而非活性化。其次，移轉至清洗製程及配線製程，在接觸孔 、、们内將接觸插頭48更在其上各形成金屬配線49來製造p通 道MOSFET (參照圖8)。 如此作成之p通道絕緣閘極場效電晶體，雖然並未進行損壞 13 200531167 觸=、42底部之心靡物好濃度可維持 搞日^ 思味可實現具備低電阻源、沒極之絕緣閘 木琢效电日日體。而，本貫施例顯示p通道場效電晶體之 ίίϊΐί1!斷’藉由接觸孔進行配線在其他半導體裝置，當然 本發明亦有效。 佳的氣體流量係由泵之排氣速率或氣體滯留時間 而受化，故本發明之效果並不限定於上述氣體之流量。
Ait上之利用可能吃 本叙明並非僅只是P通道場效電晶體之製造，亦可適用於具 有，觸!L之電極連接或進行配線之其他半導體裝置（包含液晶顯 讀置等之TFT)。又，本發明亦可適驗轉縣板或平面顯示 器之動態矩陣基板等的製造。 ^在該實施例只說明關於使用CSF8之蝕刻氣體，但使用各種碳 氟化合物膜氣體時，或使用其他蝕刻氣體時亦同樣可適用。 【圖式簡單說明】 圖1係顯示在添加〇2流量為〇sccm、2.5sccm、5sccm、lOsccm、 15sccm時’氧化膜蝕刻速率與c5F8氣體流量之關係的曲線。 士圖2係顯示在添加〇2流量為isccm、2sccm、3sccm、5sccm 時’對接觸孔側壁之碳氟化合物膜堆積量與匕巧流量之關係的曲 線。 圖3係顯示使用輻射槽孔天線之2段喷淋板構造微波激發電 漿處理裝置之概略構成的剖面圖。 圖4係顯示在本發明實施例丨中場效電晶體蝕刻前之狀態的 剖面圖。 圖5係顯示在本發明實施例丨中作完場效電晶體之蝕刻第1 製程後之狀態的剖面圖。 圖6係顯示在本發明實施例1製造途中作完場效電晶體之蝕 14 200531167 刻第2製程（零損壞蝕刻）後之狀態的剖面圖。 圖7係顯示在本發明實施例1製造途中作&场攻電晶體灰化 後之狀態的剖面圖。 ， 圖8係顯示藉岭發明實施例1中*^&方柄得到場效電 晶體的剖面圖。 ' 【主要元件符號說明】 30〜p型矽基板/石夕晶片 31〜N井 33〜源極領域 34〜及極領域 35〜閘極絕緣膜 36〜閘極 37〜層間絕緣膜 38〜光阻 41〜接觸孔 42〜接觸孔 45〜碳氟化合物膜 48〜接觸插頭 49〜金屬配線 301〜p —矽領域 302〜ρ + ί夕領域 15

Claims (1)

  1. 200531167 十、申凊專利範圍： 1· 一種半導體裝置之製造方 式於絕緣_行接觸孔之開 利5反應性離子钱刻方 造方法中，該I虫刻製程具備：第=2程/?半導體裝置之製 及第2製程，以士^衣表，以既疋之速率進行蝕刻； 係在比該第i 之速率進行蝕刻;該第2製程 f程所供“ 後且在猎由開σ而露出底材之前實施；在該第2 的組成及供給量，係與在該第1製程所供給之 虱體的組成及供給量的至少一方面相異。 2.如申請專利範圍第1項的半導體裝置之製造方法，其中該 蜀孔係至少在場效電晶體之源極領 域及汲極領威之一者的上方 之絕緣膜形成。 π^3·如申請專利範圍第1項之半導體裝置之製造方法，其中該 &緣膜係矽氧化膜。 #认t·如申請專利範圍第1項的半導體裝置之製造方法，其中該 氣體係至少包含C和F，在該第2製程將該供給氣體之供給 置比該第1製程減少。 ju仏^如申凊專利範圍第1項的半導體裝置之製造方法，其中該 二，氣體係包含含C*F之氣體與氧，在該第2製程將該氧之供 給1比該第1製程減少。 6·如申請專利範圍第1項的半導體裝置之製造方法，其中該 1〜給氣體係包含含C*F之氣體與氧，在該第2製程將該含有C ϋ F之氣體的供給量至比該第i製程減少。 7·如申請專利範圍第1項的半導體裝置之製造方法，其中該 16 200531167 j氣體係、包含含(^F之氣體與氧，在該 和F之氣體與該氧之組成令其由該第i |程改變^將包含含C 8·如申凊專利範圍第1項的半導 該開口之既定深度的_至95%= 其中至 之後再進行該第2製程。 衣知進行餘刻， 」·如申請專利範圍第j項的半導體 =性離作觸藉㈣微波練 ’其中該 激發之功率在第2製程設成比該第丨製^里衣置進仃，將電襞 10·如申請專利範圍第1項的半 制 Ξί 供給氣體之組成及供給量成其中在 之堆積物的厚度為該開π之直徑的10%以下 開°之側壁 底材表面形成保護膜。 〜’°里系璉擇成能在該開口之 形成紅法，其中 =於此彻糊之製 流量的至少-者產生變化，在保護底以:2下= —R如申請專利範圍第13項的半導體穿晋夕制 猎由該組成及流量的至少一者 ^ 衣造方法，其中 者改艾之耽體的飿刻，係可防止該底 200531167 材表面中之蝴的非活性化者。 is.如ϋ專利範圍第13項的半導體 該氣體至少包含C和F。 Κ衣仏万法，其中 16· —種#巴緣膜之名虫刻方法，女丨田;_卜t 成開口，；^此制料* —仙反應轉子侧在絕緣膜形 ，開口 ’於錢刻方法中，該侧包含：帛 率進行蝕刻；以及第2製程，以比該速率慢之二隹=之J 施；在m制f在由開而露出底材之前實 在料2衣域供給之氣體的組成及供給量 衣私所供給之氣體的組成及供給量的至少—方面相異:" 緣膜專利細16項的絕緣膜之糊方法，其中該絕 給概㈣16項的絕緣狀_方法，其中該供 該第。和F ’在該第2製程將該供給氣體之供給量比 19.如申請專利範圍第16項的絕緣膜之蝕 豆 含含C和F之氣體與氧，在該第2製程將該氧：量 比该第1製程減少。 认〆20·如申請專利範圍第16項的絕緣膜之蝕刻方法，其中該供 p6氣^係包含含C和F之氣體與氧，在該第2製程將該^該C和 之氣體的供給量比該第丨製程減少。 仏>21·如申凊專利範圍第16項的絕緣膜之姓刻方法，其中該供 給氣體包含含C和F之氣體與氧，在該第2製程將該含〔和F之 18 200531167 氣體與該氧的組成令其由該第1製程改變。 22·如申請專利範圍第16項的絕緣膜之蝕刻方法，其中1門 =既=度的8〇%至95%為止，以該第丨製程 刻，: 再進行該第2製程。 文 23·如申請專利範圍第16項的絕緣膜之蝕 反應性離子_以微波激發之電漿處理 亥 發之功率在第2製程設成比第！製程弱。 各丁將電漿激 當9 =如申5月專利範圍第16項的絕緣膜之餘刻方法，J:由产 乐2衣程所供給氣體之組成及供給量係選摆 /、中在該 之堆積物的厚度為該開口之直徑的成使在該開口之側壁 ^如申請專利範圍第16項的絕緣膜之 衣程賴給之氣體的組纽供給 = 中在該 材表面形成保護膜。 k擇成此在該開口之底 19
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