TW200529383A - Electrode package for semiconductor device - Google Patents

Electrode package for semiconductor device Download PDF

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Publication number
TW200529383A
TW200529383A TW093135467A TW93135467A TW200529383A TW 200529383 A TW200529383 A TW 200529383A TW 093135467 A TW093135467 A TW 093135467A TW 93135467 A TW93135467 A TW 93135467A TW 200529383 A TW200529383 A TW 200529383A
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package
electrode
resin plate
electrode package
semiconductor device
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TW093135467A
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English (en)
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TWI265607B (en
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Hiroshi Kimura
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Torex Semiconductor Ltd
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Publication of TW200529383A publication Critical patent/TW200529383A/zh
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Publication of TWI265607B publication Critical patent/TWI265607B/zh

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568Temporary substrate used as encapsulation process aid
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
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    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49861Lead-frames fixed on or encapsulated in insulating substrates
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    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
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    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
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    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2924/181Encapsulation

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

200529383 九、發明說明: 【發明所屬之技術領域】 本發明㈣_種用於半導體裝置的電極封裝體及使用該 琶㈣裝體的鑄模半導體裝置,尤其有關用於無引線表面 黏著型封裝體之樹脂鑄模 的私極封裝體及鑄模半導體裝 置。 【先前技術】 表面黏著技術是-種在㈣電路板±直接焊接黏著於半 導體裝置表面之電極的技術。使用此技術,便不需要使用 接針插人系統的穿透孔。此外,還可縮小電子組件、基板 曰力封衣&度。作為用於表面點著型半導體裝置的電極 于4體如圖5所示的電積框架,揭露於曰本專利申請案特 才a開第2002-16181號。電積框架配置具有複數個彼此隔 離的電極’如在撓性平坦金屬基板9上電積的金屬層以、 8b ° 具有電積框架且在無引線表面黏著型封裝體中鑄模之半 導體裝置的形成步驟說明如下。首先,如圖6A所示,在金 屬層8b上晶粒黏接半導體晶片2。然後,接線4可分別連接 半導體晶片2的焊墊12和金屬層心。各金屬層此先前已沉積 大於各半導體晶片2的底面。然後,利用環氧樹脂7封裝以 接線4接線的半導體晶片2。然後,如圖6B所示,可從樹脂 鑄模體11移除金屬基板9。因此,金屬層“、8b可曝露於樹 脂鑄模體11的底面上。然後,沿著割面線3切割樹脂鑄模體 11 ’即可將半導體晶片2分成個別的半導體裝置。 97185.doc 200529383 由於隔離金屬層8a、8b係以金屬基板9固定,因此必須將 電積框架送到具有如圖5所示之金屬基板9之半導體裝置的 製造商。因此,必須運送很重的電積框架,且運送成本报 高。此外,對於各製造商而言,製造半導體裝置時,必2 在半導體裝置的製程中移除金屬基板9。然而,因為鑄模電 積框架很薄(小於〇.7 mm),所以移除金屬基板9時通常會在 樹脂鑄模體11中產生裂痕。此外,除非對應於各種半導體 晶片2的各形狀修改金屬層8b的設計,否則很難縮小半導體 裝置。因此,由於必須最佳化各種半導體晶片2之各形狀的 電積框架,致使半導體裝置的生產成本增加。 為了解決上述問題’本發明之目的在於提供—種用於半 導體裝置的電極封裝體’以減少表面黏著型半導體裝置的 生產成本’另外還提供使用該電極封裝體的半導體裝置。 【發明内容】 為了達成目的’根據本發明之第一方面,其中提供:包 括-樹脂板的電極封裝體;複數個鑄模在該樹脂板中的隔 離電極’其才各電極係曝露於該樹脂板的上表面及下表面 上。 根據上述,可以製造表面黏著型半導體裝置如下。第一 在樹脂板的表面之—黏著半導體晶片。第二,導電接線 連接半導體晶片和樹脂板中鑄模的對應電極。第三,將 導體晶片封裝在樹脂封奘邮 丁月曰封衣粗中。因此,由於固定複數個 離電極的樹脂板,雷士 私極封裝體的製造可以不用金屬基板 因而重量也很輕。此外,你 ^ 使用此電極封裝體製造半導體 97i85.doc 200529383 置時,不必移除金屬基板。 根據本發明,其中較佳提供電極封裝體如下··皇中各带 極的截面積隨著樹脂板之—表面至另—表面的深度增加; 根據上述,使一表面向下及另一表面向上可讓電極很難 從樹脂板中掉落。 根據本發明,其中較佳提供電極封裝體如下:其中將各 具有相同形狀的電極配置成矩陣,且鑄模於樹脂板中。 根據上述’可將具有各種尺寸及形狀的半導體晶片黏著 在樹脂板上。因此,可以減少用於具有各種尺寸及形狀之 半導體晶片的電極封裝體數。 根據本發明,其中較佳提供電極封裝體如下:其中在樹 脂板的周邊上提供加強框架。 如果各製程之薄電極封裝體的剛性很小,則生產機器將 很難傳送封裝體。然而,根據上述的本發明,藉由提供加 強框架,即可增加電極封裝體的剛性。因此,在生產機器 傳送電極封裝體時,可防止電極封裝體受到損壞。 根據本發朋,其中較佳提供電極封裝體如下:其中藉由 其縱向上沿著樹脂板周邊配置的複數個支撑體來形成加強 框架,支撑體中相鄰支撑體的各端係在和縱向垂直的方向 中重疊。 根據上述結構,在施加因加強框架及鄰接加強框架之電 極封裝體之熱膨服係數間的差異而產生的力使電極封裝體 變形時,此力會在重疊部分抵消。因此,可以防止電極封 裝體的變形。 97185.doc 200529383 根據本發明的第二方面,其中提供一種半導體裝置,其 包括:上述電極封裝體、黏著在電極封裝體上及以導電接 線電連接至電極封裝體之對應電極的半導體晶片、及封裝 已接線之半導體晶片的樹脂封裝體。 根據上述,由於用於製造半導體裝置的電極封裝體,因 此在生產期間不必移除金屬基板。因此,可以減少半導體 裝置的生產成本。 根據本發明的第三方面,其中提供的半導體裝置包括: 上述電極封裝體、黏著在電極封裝體之樹脂板的另一表面 上及以‘電接線電連接至電極封裝體之對應電極的半導體 晶片、及封裝已接線之半導體晶片的樹脂封裝體。 根據上述’由於用於製造半導體裝置的電極封裝體,因 此在生產期間不必移除金屬基板。此外,在電極封裝體之 樹脂板的另一表面上黏著半導體晶片,即使半導體晶片及 電極間的黏接斷裂,其上黏著半導體晶片的電極也很難從 樹脂板中掉落。因此,可以進一步減少半導體裝置的生產 成本。 _ 【實施方式】 根據本發明之電極封裝體及使用該電極封裝體的半導體 裝置將參考圖1八至1(:、2A至2F、3A至3C、及4進行說明。 此處本發明有關一種無引線表面黏著型樹脂鑄模半導體 裝置,及將會說明用於樹脂鑄模半導體裝置之製程的電極 封裝體。 如圖1A所示,電極封裝體2〇包括樹脂板21。複數個具有 97185.doc 200529383 相同^/狀的離金屬層22(電極)係配置成矩陣及鑄模於樹 脂板2 1中。 此外,金屬層22係曝露於樹脂板21的上表面及下表面上。 此外,各金屬層22的截面積會隨著樹脂板21之上表面至下 表面的深度增加。 各金屬層22係配置具有··在上表面具有高可焊性的(金) 或Sn(錫)薄層(未顯示),如圖1A所示;能夠連接至下表面之 AU接線的Au或八§(銀)薄層(未顯示),如圖1B所示;及藉由 電積形成且位於該等兩個薄層之間的见(鎳)、Ni/c〇(鈷)、 或Cu(銅)薄層(未顯示)。Ni、Ni/c〇、或Cu層及Au、“、或 Ag層的厚度分別為2〇至5〇 μιη及〇 〇5至i〇 。 此外在電極封裝體20中,在其縱向中以複數個支撑體 23a、23b、23c、23d形成的加強框架係沿著樹脂板21鑄模 的周邊進行配置。例如,支撑體23&、23b、23c、23d及金 屬層22係同時以電積形成。 如圖1A所示之電極封裝體2〇之生產方法的具體實施例將 參考圖2A至2F的橫截面圖進行說明。首先,如圖2A所示, 準備用於製造電極封裝體2〇的撓性平坦金屬基板3〇。金屬 基板30疋不鏽鋼薄板,具有〇1 厚度。然後,除了要形 成金屬層22或支撑體23a、23b、23c、23d的特定區域之外, 在金屬基板30的表面上形成光阻膜31。另外,光阻膜31係 在截面積隨著其表面至金屬基板3〇的深度減少的形狀中形 成。 然後,將金屬基板3〇浸入電積槽中。然後,在電積槽中, 97i85.doc 200529383 在金屬基板30及電極之間施加電流。依此方式,使用如圖 册斤不的電鑄程序,藉由連續電積Αιι或Ag; Ni、Ni/c〇、 , Sn,即可在金屬基板30未形成光阻膜3 1的區 域上,形成配置有薄Ai^Ag,犯、沁/以或a,及八以或“ 薄膜(未顯示)的金屬層22及支撑體23a、23b、23c、23d。* 上述,由於光阻膜31係在截面積隨著其表面至金屬基板3〇 之深度減少的形狀中形成,各金屬層22相反地在截面積隨 著其表面至金屬基板30之深度增加的形狀中形成。 —接著,如圖2C所示,移除光阻膜31。然後,如圖2D所示, 藉由如疑塗塗布樹脂21。然後,如圖2e所示,會移除樹脂 21薄膜的整個表面以曝露樹脂21薄膜之上表面的金屬層 然後,如圖2F所示,會移除金屬基板30以形成電極封 裝體2〇。由於金屬層22及支撑體23a、23b、23c、23d係使 用私鑄^序電積於金屬基板3〇上,及金屬基板3〇在平面形 狀中為撓性,因此很容易即可從電極封裝體2〇移除金屬基 板3 0 〇 另外,本發明的製程不限於上述程序。例如,可以採用 以下程序··使用如快速蒸發方法電積或汽相沉積Au或Ag; • Ni/Co或Cu ,及Au或Sn之薄層(未顯示),然後再藉由 蝕刻移除除了金屬層22及支撑體23&、23b、23c、23d以外 的溥膜。又例如,可採用以下程序:第一,只用樹脂塗布 Ni Ni/Co、或Cu的一個薄層;第二,從樹脂板移除金屬基 板3 0,第二,將樹脂板浸入電積槽,以同時在樹脂板的上 表面及下表面的一層上電積薄層。 97185.doc -10- 200529383 可將上述電極封裝體20送至半導體裝置的製造商。在製 造商處’會將半導體晶片黏著在電極封裝體2〇上以生產半 導體裝置。下文,將參考圖3A至3C說明使用電極封裝體20 之半導體裝置的生產方法。首先,如圖3 A所示,在電極封 裝體20的向上之下表面上黏著及晶粒黏接半導體晶片32。 焊塾32a係形成於各半導體晶片32的表面上。 在黏著半導體晶片32後,如圖3B所示,Αιι接線33可電連 接各半導體晶片32的焊墊32a和金屬層22 Mu接線33可藉由 超音波黏接或其類似物來連接。然後,會將其上黏著及接 線黏接半導體晶片32的電極封裝體2〇附著於上方鑄模34 上。 會經由在上方鑄模34上形成的凹洞,將環氧樹脂注入上 方鑄模34及下方鑄模(電極封裝體20)間之封裝的内部空間。 在此鑄模組中,電極封裝體2〇可當作下方鑄模組。在此程 序中,會將和接線33連接的半導體晶片32封裝在樹脂中, ,會形成具有如圖3C所示之半導體晶片32及金屬層22的樹 日封衣體35 然、後,沿著割面線s切割,即可從樹脂封裝體 35分離半導體裝置32。 根據本發明如訊所示的電極封裝體2〇,複數個彼此隔 離的金屬層22係以樹脂板21固定。因此,不用習用的金屬 基板即可製造電極封裝體2〇,而且重量比較輕。因此,可 以減少將電極封裝體2G送至半導體裝置製造商的運送成 、制Y外根據本發明,如圖3A至3C所示,在半導體裝置 、衣私中不必移除金屬基板(例如,圖5的參考數字9)。因此, 97185.doc 200529383 半導體裝置的各製造商不必擁有移除金屬基板的設備。因 此,可以減少半導體裝置的生產成本。 如圖1C所示,各該等金屬層22的截面積會隨著樹脂板21 之上表面至下表面的深度增加。因此,以電極封裝體2〇向 下的方式運送,可防止金屬層22從樹脂板21中掉落。因此, 可穩定電極封裝體20的品質,以減少半導體裝置的生產成 本。 如圖1Α及1Β所示,可將具有相同形狀的金屬層22配置成 矩陣,並鑄模於電極封裝體20的樹脂板21中。因此,可將 具有各種尺寸及形狀的半導體晶片32黏著在樹脂板21上。 因此,可以減少用於具有各種尺寸及形狀之半導體晶片” 的電極封裝體20的數目。這也可以減少半導體裝置32的生 產成本。 如圖1Β所示,可藉由沿著樹脂板21之周邊的複數個支撑 體23a、23b、23c、23d形成加強框架。電極封裝體2〇很薄, 約25 μπι厚,且其剛性很低。因此,加強框架的提供可增加 電極封裝體20的剛性。因此,因電極封裝體2〇變形所造成 的缺陷電極封裝體數會減少,因而可減少半導體裝置的生 產成本。 在電極封裝體20中,在其縱向中以複數個支撑體、 23b、23c、23d形成的加強框架係沿著樹脂板以的周邊進行 配置。此外,如圖4所示,相鄰支撑體23a、23b、&、 的各對末端會在和縱向垂直的方向γι中重疊。根據此配置, 例如,即使支撑體23a、23b、23c、23d以樹脂製成,金屬 層22及樹脂板21(均為電極封裝體2()的組件)之熱膨服係數 97185.doc -12- 200529383 間的差異,會造成電極封裝體20及支撑體23卜23b、汩c 23d之熱膨脹係數間的差異。因此,如果將力f施加於支撑 體23a、23b、23c、23d各邊緣至各中央之方向中的電極封 裝體20’則力F會在各重疊部分處抵消。因在匕,要使電極封 裝體20變形會變得比較難。 如f3A至3C所示,會將半導體曰曰曰片32黏著在金屬層22具 有較寬截面積之電極封裝體2〇的下表面上。據此,即使半 導體晶片32及其上分別黏著半導體晶片”之金屬層22間的 黏接斷裂,半導體晶片32也很難從樹脂板22上掉落。因此, 可以減 >、缺卩曰半導體裝置的數目,及也可以減少半導體裝 置的生產成本。 & 在上述的具體實施例中,各金屬層22係配置有:具有高 可焊性的Au或Sn薄層;可連接sAu接線的Au*Ag薄層; 及位在該等兩個薄層之間的薄Ni、Ni/c〇、或^層。麸而, 也可以採用純配置。例如,在黏著半導體晶片32的程序 中,在沉積薄膜時,金屬層22可以只配置有Ni、Ni/c〇、或 Cu的薄膜,或配置有該等薄膜的兩個及八口或“薄膜中的任 何員或Au或Ag薄膜。此外,金屬層22的材料不限於 上述材料,也可以採用各種各可以是電極的材料。 【圖式簡單說明】 圖1A為顯示根據本發明之電極封裝體之具體實施例的正 面平面圖; 圖1B為顯示圖丨八之電極封裝體的背面平面圖; 圖1C為截取自圖1A直線,的橫截面圖; 圖2A至2F為顯示圖1A電極封裝體之生產方法之具體實 97l85.doc -13- 200529383 施例的橫截面圖; 圖3A至3C為顯示使用圖1A電極封裝體之半導體裝置之 生產方法之具體實施例的橫截面圖; 圖4為說明施加於圖1Ai支撑體23 〇及23 d之力ρ的解說 圖; 圖5為顯示習用電極封裝體之具體實施例之電積框架的 橫截面圖;及 圖6A及6B為顯示使用圖5之電積框架之半導體裝置之習 用生產方法之具體實施例的橫截面圖。 【主要元件符號說明】 2 > 32 半導體晶片 4 接線 7 環氧樹脂 8a、8b、22 金屬層 9 ^ 30 金屬基板 11 樹脂鑄模體 12 焊墊 20 ' 電極封裝體 21 樹脂板 23a、23b、23c、23d 支撑體 31 光阻膜 32a 焊墊 33 Au接線 34 上方鑄模 35 樹脂封裝體 97i85.doc -U-

Claims (1)

  1. 200529383 十、申請專利範園·· 1 · 一種電極封裝體,其包含·· 一樹脂板;及 複數個鑄模於該樹脂板中的隔離電極, 藉此各該等電極可曝露於該樹脂板的上表面及下表面 上。 2·如請求項1之電極封裝體, 其中各該等電極的截面積會隨著該樹脂板之上(第一) 表面或下(第二)表面至另一個表面的深度增加。 3 ·如請求項1之電極封裝體, 其中該等電極具有配置成一矩陣的一相同形狀,及鑄 模於該樹脂板中。 4·如請求項1之電極封裝體, 其中一加強框架係提供於該樹脂板的一周邊上。 5 ·如請求項4之電極封裝體, 其中該加強框架係由複數個支撑體製成,該等在其縱 向中的支_體係沿著該樹脂板的周邊配置,該等支撑體 之相鄰支撑體的各端在和縱向垂直的方向中彼此重疊。 6· —種半導體裝置,其包含: 如請求項1至5中任何一項的電極封裝體; 半V體曰a片,其係設於該電極封裝體上及以導電接 線電連接至該電極封裝體對應的電極;及 一樹脂封裝體,以封裝該已接線的半導體晶片。 7· —種半導體裝置,其包含·· 97185.doc 200529383 如明求項2之電極封裝體; 一半導體晶片,其係黏著於該電極封裝體之樹脂板的 該另一表面及以導電接線電連接至該電極封裝體對應的 電極;及 一樹脂封裝體’以封裝該已接線的半導體晶片。 97185.doc
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US7947535B2 (en) * 2005-10-22 2011-05-24 Stats Chippac Ltd. Thin package system with external terminals
US8594763B1 (en) 2010-05-25 2013-11-26 Neurowave Systems Inc. Physiological electrode assembly for fast application
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