TW200524154A - Structure and manufacturing method of thyristor - Google Patents

Structure and manufacturing method of thyristor Download PDF

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TW200524154A
TW200524154A TW93100192A TW93100192A TW200524154A TW 200524154 A TW200524154 A TW 200524154A TW 93100192 A TW93100192 A TW 93100192A TW 93100192 A TW93100192 A TW 93100192A TW 200524154 A TW200524154 A TW 200524154A
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diffusion layer
impurity diffusion
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TW93100192A
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TWI285952B (en
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Meng-Lung Sung
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Concord Semiconductor Corp
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Abstract

The present invention discloses a structure and manufacturing method of thyristor. In order to decrease the junction capacitance, the present invention decreases the doping concentration of the substrate, but in the mean time, the breakdown voltage or switching voltage would increase. This is not acceptable in some application. In order to solve this contradiction, the present invention adds another medium doped impurity diffusion layer to the anode. The doping concentration of this layer is higher than the doping concentration of the substrate. Therefore decreasing the switching voltage. A low junction capacitance as well as the desired switching voltage can be obtained.

Description

20052415十 五、發明說明(1) 1.發明所屬之技術領域 本發明係有關於閉流體構造之改良,尤指一種基板# 雜濃度降低以降低接面電容後,在陽極增加一層中声彳參雜 之雜質擴散層以降低切入電壓(swi tching voltage^/广 先前技術 閘流體(Thyristor)亦稱矽控整流器(si 1 ic〇n Control rectifier, SCR)。係利用其具有較高之顺向阻斷 (blocking)或開路阻抗(OFF impedance),而在順向導通 (break over)或切入(switching)發生時可通過甚大之電 流,故工業上之用途甚廣,主要為電力控制。閘流體之習 知構造如第1圖所示,為一 npnp或pnpn結構,通常在一 η型 基體106上,在兩面以離子植入中度摻雜之層1)1層1〇4及以 層108,再於陽極以以離子植入或擴散法形成η1層1〇2,再 於陽極及陰極(kathode)形成接觸。 參考第2圖’第2圖為習知構造之閘流體在加上順向偏 壓時之電壓降及空乏區之示意圖。在加上順向偏壓時,第 一np接面202乃為順向偏壓,但第二pn接面204 J2則為逆 向偏壓’而Pl之摻雜濃度大於%之摻雜濃度,因而大部分 之之空乏區在〜之一侧,又第三叫搔面206 J3為順向偏 壓。〜之摻雜濃度決定凡之崩潰電壓或切入電壓\,由下式20052415 15. Description of the invention (1) 1. The technical field to which the invention belongs The present invention relates to the improvement of closed-fluid structures, especially a substrate # After the impurity concentration of the substrate is reduced to reduce the junction capacitance, a layer of acoustic noise is added to the anode The impurity impurity diffusion layer is used to reduce the switching voltage (/ switch technology), which is also known as si 1 icon control rectifier (SCR). It has a higher forward blocking ( blocking or OFF impedance, and can pass through a large amount of current when break-through or switching occurs, so it is widely used in industry, mainly for power control. The structure is as shown in Figure 1. It is an npnp or pnpn structure, usually on a n-type substrate 106, with a layer doped with ion implantation on both sides. 1) 1 layer 104 and layer 108, and then The anode is formed with the η1 layer 102 by an ion implantation or diffusion method, and then contacts are formed between the anode and the cathode. Refer to FIG. 2 'FIG. 2 is a schematic diagram of a voltage drop and a dead zone of a conventionally constructed gate fluid when a forward bias voltage is applied. When forward bias is applied, the first np junction 202 is forward biased, but the second pn junction 204 J2 is reverse biased and the doping concentration of Pl is greater than the doping concentration of%, so Most of the empty area is on one side, and the third surface 206 J3 is forward biased. The doping concentration of ~ determines the breakdown voltage or cut-in voltage of \, by the following formula

第5頁 200524154 五、發明說明(2) 表示: V £s £m2 / 2qNB (1) 其中£s為半導體之介電係數(permitivity), 為最大電場,q為電子之電荷,Νβ為%之摻雜濃度,由(1 ) 式可知1¾ (式中之NB)之摻雜濃度低,切入電壓高,反之,% 之摻濃度高,則切入電壓低,故一般為得到例如3 〇 〇伏特 之切入電壓’基板之摻雜濃度仏一般都在1 X丨〇1δ at〇m/cm3 或電阻係數(resistivity)在5D-cm左右,且在切入導通 時’J2至Ja並未完全空乏,或未衝穿(pUnch through),故 其切入電壓係由仏之摻雜濃度決定。另外一個重要參數為 接面電容(depletion-layer capacitane,C),由下式表 不 · C=(q £s NB/2(Vbi ± V))i/2 其中Vbi為内建電位(built-in potential),V為外加電 壓’ NB為之摻雜濃度。由(2 )式可知,接面電容與n之換 雜濃度之開平方成正比,亦即摻雜濃度高,接面電^高, 摻雜濃度低,接面電容亦低。若接面L之電容為q,接面工Page 5 200524154 V. Description of the invention (2) means: V £ s £ m2 / 2qNB (1) where £ s is the permittivity of the semiconductor, which is the maximum electric field, q is the charge of the electron, and Nβ is the percentage of From the formula (1), we know that the doping concentration of 1¾ (NB in the formula) is low and the cut-in voltage is high. Conversely, if the doping concentration of% is high, the cut-in voltage is low, so it is generally to obtain, for example, 300 volts. The cut-in voltage 'doping concentration of the substrate is generally 1 X 丨 〇1δ at〇m / cm3 or the resistivity is about 5D-cm, and when the cut-in is turned on,' J2 to Ja are not completely empty, or not PUnch through, so its cut-in voltage is determined by the doping concentration of ytterbium. Another important parameter is the depletion-layer capacitane (C), which is expressed by the following formula: C = (q £ s NB / 2 (Vbi ± V)) i / 2 where Vbi is the built-in potential (built- in potential), V is the applied voltage, and NB is the doping concentration. From the formula (2), it can be known that the junction capacitance is directly proportional to the square of the impurity concentration of n, that is, the doping concentration is high, the junction voltage is high, the doping concentration is low, and the junction capacitance is also low. If the capacitance of junction L is q,

第6頁 200524154 五、發明說明(3) 之電容為(:2,接面j3之電容為c3,則因q、C2及(:3係串 聯其總電C為·· C-l/Cl/Q +1/C2 +1/C3) (3) 但ci及匕皆甚大,故C与C2,亦即整個閘流體之電容等於接 面A之電容,由n2之摻雜濃度決定。 第3圖為先前技術之閘流體之構造剖面圖。為簡化敘 述,僅示其内部結構,其他如金屬接觸,封裝等皆未圖 示。在決定閘流體之切入電壓後,選擇一具有所要之崩潰 (切入)電壓之ir型掺雜之矽晶片3〇2,例如切入電壓之規格 為300伏特,則取仏之摻雜濃度為! X i〇15at〇m/cm3,或電阻 係數為5 Ω - cm ’在晶片兩側皆植入p型掺雜306及310,一 般植入鎵(Gallium),其摻雜濃度係為5x 1〇15at〇m/cm3s5 x l〇16atom/cm3,經高溫活化(activati〇n)或擴散後,其接 面深度約為40 //m至50 ,然後在第一面以擴散形成陽極 n+304,在第二面不相對之處形成陽極#“?,使第一面有 n+304之部分形成n+p^p2之閘流體結構,而第二面有 之部分形成n+hhh之閘流體結構。此先前技術有一缺 因其切入電壓需要高摻雜之%基板,故其接面電容 '女, 約在80〜85ρί之間。對需求低接面電容之客戶, 因此有-需求,希望降低閘流體之電容而仍能保口持切。 壓於一定之值。 冤Page 6 200524154 V. Description of the invention (3) The capacitance of (3) is (: 2, and the capacitance of junction j3 is c3, so since q, C2 and (: 3 are connected in series, the total electricity C is ·· Cl / Cl / Q + 1 / C2 + 1 / C3) (3) However, ci and dagger are very large, so the capacitance of C and C2, that is, the capacitance of the entire gate fluid is equal to the capacitance of junction A, which is determined by the doping concentration of n2. Figure 3 is the previous The structural cross-section of the sluice of technology. To simplify the description, only its internal structure is shown. Others such as metal contact and packaging are not shown. After determining the cut-in voltage of the sluice, choose one with the desired breakdown (cut-in) voltage Ir-type doped silicon wafer 3 02, for example, the cut-in voltage specification is 300 volts, then the doping concentration of ytterbium is taken as! X i〇15at〇m / cm3, or the resistivity is 5 Ω-cm 'in the wafer Both sides are implanted with p-type doping 306 and 310, and gallium (Gallium) is generally implanted. The doping concentration is 5 x 1015at〇m / cm3s5 x 1016 atom / cm3, which is activated by high temperature (activation) or After the diffusion, the depth of the junction is about 40 // m to 50, and then the anode n + 304 is formed by diffusion on the first side, and the anode # "? Is formed where the second side is not opposite. A part with n + 304 on one side forms a gate fluid structure of n + p ^ p2, and a part on the second side forms a gate fluid structure of n + hhh. This prior art has a deficiency because its cut-in voltage requires a highly doped% substrate Therefore, its junction capacitance 'female' is between 80 ~ 85ρί. For customers who require low junction capacitance, there is a demand for it, hoping to reduce the capacitance of the sluice fluid and still keep the cut. Pressed to a certain value Injustice

200524154200524154

五、發明說明(4) 3.發明内容 本發明之目的在提供一種 基板摻雜濃度降低以降低接面 本發明之另一目的在提供 法,在射極區另行植入一層中 摻雜,並驅入其接面至其下之 降低切入電壓。 閘流體結構及製造方法,使 電容, 一種閘流體結構及製造方 度摻雜之第一型(例如η型) 第一型(例如ρ型)之下,以 為達成上述目的及其他目的,並改進先前技術不能同 時降低電容及保持切入電壓之缺點,本發明之第一觀點提 供一種閘流體構造’在基板摻雜濃度降低以降低接面電容 後,在陽極增加一層中度摻雜之雜質擴散層,於閘流體在 順向偏壓時’第二接面為逆向偏壓,其崩潰電壓由中度摻 雜之雜質擴散層決定’以降低切入電壓(switching voltage),至少包含:一第1型基板,其摻雜濃度適合所 需較小之接面電容;基板之正反面之第2型第一雜質擴散 層,由擴散係數較低之雜質形成,其接面J2之深度為; 基板之正反面之第第2型第一雜質擴散層下之第1型第二中 度摻雜之雜質擴散層,正反面之第1型第二中度摻雜之雜 質擴散層不相對而相互交錯,其擴散深於第2型第一雜質 擴散層,而在第2型第一雜質擴散層之下,其接面深度為砬V. Description of the invention (4) 3. Summary of the invention The purpose of the present invention is to provide a substrate with a lower doping concentration to reduce the junction. Another object of the present invention is to provide a method of implanting a dopant in a separate layer in the emitter region, and Drive in its junction to lower the cut-in voltage. Gate fluid structure and manufacturing method to make capacitor, a gate fluid structure and manufacturing method doped first type (such as n-type) under the first type (such as p-type), in order to achieve the above and other purposes, and improve Disadvantages of the prior art that cannot simultaneously reduce capacitance and maintain cut-in voltage, a first aspect of the present invention provides a sluice fluid structure 'after the substrate doping concentration is reduced to reduce the junction capacitance, a moderately doped impurity diffusion layer is added to the anode. When the gate fluid is forward biased, 'the second junction is reverse biased, and its breakdown voltage is determined by the moderately doped impurity diffusion layer' to reduce the switching voltage, at least including: a type 1 The substrate has a doping concentration suitable for the required small junction capacitance; the second type first impurity diffusion layer on the front and back of the substrate is formed of impurities with a lower diffusion coefficient, and the depth of the junction J2 is: The first type 2 second moderately doped impurity diffusion layer under the second type 1 first impurity diffusion layer on the reverse side, and the first type 2 second moderately doped impurity diffusion layers on the front and back sides do not face each other and intersect each other. Diffused deeper than a first-type second impurity diffusion layer and under the first-type second impurity diffusion layer of the junction depth La

第8頁 ^200524154 五、發明說明(5) " ' 2 ;基板之正反面之第1型第三雜質擴散層,位於第2型第一 雜質擴散層内,為高濃度摻雜,與金屬形成歐姆接觸。 本發明之第二觀點提供一種製造閘流體之方法,在基 板摻雜濃度降低以降低接面電容,並在陽極增加一層中度 摻雜之雜質擴散層’於閘流體在順向偏壓時,第二接面為 逆向偏壓’在苐1¾第一中度推雜擴散層到達崩潰電壓時' 即導通,以降低切入電壓(switch ing voltage),至少包 含下列步驟:(a)準備一第1型基板,選擇其摻雜濃度使適 合所舄較小之接面電谷,(b )在基板之正反面利用離子植 入形成第1型第二中度摻雜之雜質擴散層,正反面之第二 中度摻雜之雜質擴散層不相對而相互交錯,其接面之深度 為4 ;(c)在基板之正反面利用離子植入第2型第一雜質擴 散層,由擴散係數較低之雜質形成,其接面乙之深度為 i ; (d)在第1型第二中度摻雜之雜質擴散層内利用離子植入 形成第1型高濃度摻雜之第三雜質擴散層,以與金屬形成 歐姆接觸;(e)完成金屬化、蝕刻、隔離、封裝等製程。 4.實施方式 本發明之内容可經由下述實施例配合其相關圖式之闡 述而予揭示。參考第4圖,第4圖係依據本發明之一實施例 之閘流體構造之平面圖。為簡化描述,僅示其晶圓之内部 構造’其他例如金屬接觸,封裝等皆未圖示。在基板5〇2Page 8 ^ 200524154 V. Description of the invention (5) "'2; The first type of third impurity diffusion layer on the front and back of the substrate is located in the second type of first impurity diffusion layer, which is doped with high concentration and interacts with metal Form an ohmic contact. A second aspect of the present invention provides a method for manufacturing a gate fluid, in which the doping concentration of the substrate is reduced to reduce the junction capacitance, and a moderately doped impurity diffusion layer is added to the anode. When the gate fluid is forward biased, The second junction is reverse biased 'when 第一 1¾ the first moderately doped diffusion layer reaches the breakdown voltage', which is turned on to reduce the switching voltage. It includes at least the following steps: (a) Prepare a first Type substrate, choose its doping concentration to suit the smaller junction valley, (b) use ion implantation on the front and back sides of the substrate to form a type 1 second moderately doped impurity diffusion layer. The second moderately doped impurity diffusion layers do not face each other and are staggered with each other, and the depth of the interface is 4; (c) The second type impurity diffusion layer is implanted with ions on the front and back sides of the substrate, which has a lower diffusion coefficient. Impurity formation, the depth of junction B is i; (d) using ion implantation to form a first type high-concentration doped third impurity diffusion layer in a first type second moderately doped impurity diffusion layer, To form ohmic contact with the metal; (e) complete metallization and etching Carving, isolation, packaging and other processes. 4. Embodiment The content of the present invention can be disclosed through the following embodiments in conjunction with the description of its related drawings. Referring to FIG. 4, FIG. 4 is a plan view of a sluice fluid structure according to an embodiment of the present invention. In order to simplify the description, only the internal structure of the wafer 'is shown. Others such as metal contacts, packages, etc. are not shown. On the substrate 50

第9頁 20052415^ 五、發明說明(6) -- 上有第1型(本例為n型)濃摻雜之#接觸區5〇4、513,在第2 型(本例為p型)Pl層之下之第i型摻雜層111512、514(請參考 第5圖(c)),其面積僅為閘流體面積之1/2以下,另一半基 板502之虛線表示之11+接觸區513及111層514係在基板5〇2之 反面,為另一閘流體。此正反面之閘流體為對稱。正面之 閘流體負責正半波,反面之閘流體負責負半波之控制及整 參考第5圖’第5圖係依據本發明之實施例之閘流體緣 第4圖之A - A線之製造流程之剖面圖。如第5圖(a )所示,在 決定閘流體之接面電容較適合之值後,選擇具有所要之阻 斷時之最小接面電容之摻雜濃度之第1型(本例為η型)基板 5 0 2,例如希望將接面電容降低一倍,則公式(2 )在一定之 外加電壓下’ ΝΒ應減少1 〇倍,例如原來之摻雜濃度為1 X l〇15at〇m/cm3,則降至5x 1〇13at〇m/cm3s9x 1〇14at〇in/cm3, 亦即將電阻係數p自5 Q-cin增加為6 Ω-cm至100 Ω-cm,使 電容值減少10倍,但此時之崩潰電壓%,如第(3)式所示, 則增加至約1 000伏特以上(參考SM· Sge,”Physics ofPage 9 20052415 ^ V. Description of the invention (6)-There is a first type (n-type in this example) heavily doped #contact region 5504, 513, and in the second type (p-type in this example) The i-type doped layers 111512, 514 under the Pl layer (refer to Figure 5 (c)), whose area is only less than 1/2 of the gate fluid area, and the 11+ contact area indicated by the dashed line of the other half of the substrate 502 The 513 and 111 layers 514 are on the opposite side of the substrate 502 and are another gate fluid. The front and back gate fluids are symmetrical. The front sluice fluid is responsible for the positive half wave, and the negative sluice fluid is responsible for the control of the negative half wave. Refer to FIG. 5 'FIG. 5 is the manufacture of the A-A line of the sluice fluid edge according to the embodiment of the present invention. Sectional view of the process. As shown in Figure 5 (a), after determining the appropriate value of the interface capacitance of the sluice fluid, choose the first type (the n type in this example) that has the minimum doping concentration of the interface capacitance at the desired blocking. ) Substrate 5 0 2 For example, if you want to double the junction capacitance, then formula (2) should be reduced by 10 times under a certain applied voltage. For example, the original doping concentration is 1 X 1015at〇m / cm3, it will be reduced to 5x 1013at〇m / cm3s9x 1014at〇in / cm3, that is, the resistivity p will be increased from 5 Q-cin to 6 Ω-cm to 100 Ω-cm, which will reduce the capacitance value by 10 times. However, the breakdown voltage% at this time, as shown in equation (3), increases to about 1 000 volts or more (refer to SM · Sge, "Physics of

Semiconductor Devices” page 115 FIG·23),已不合需 求規格’此即本發明要解決之問題之二,然後以離子植入 濃度較高(例如較NB多10倍以上,例如5 X i〇14at〇m/cm3至5 X 1015at〇m/Cm3)之第i型第二中度摻雜之ηι層512、514於正 反面之預定區域,此第二中度摻雜之ηι層5丨2、5丨4之面積 較閘流體之面積小,僅為閘流體面積之丨/ 2至丨/ 5,使接面Semiconductor Devices "page 115 FIG. 23), which has not met the required specifications. This is the second problem to be solved by the present invention, and then the ion implantation concentration is higher (for example, 10 times more than NB, such as 5 X 〇14at〇). m / cm3 to 5 X 1015at〇m / Cm3), i-type second moderately doped ηm layers 512, 514 are in a predetermined area on the front and back sides, and this second moderately doped ηm layer 5 丨 2, 5 The area of 4 is smaller than the area of the sluice fluid, which is only / 2 of the area of the sluice fluid.

第10頁 200524154 五、發明說明(7) 電谷不致增加。且其在正反面之位置不相對而互相交錯, 如第5圖(a)所示。然後如第5圖(b)所示,以習知方法在晶 片兩面皆植入第2型(本例為p型)摻雜5〇6、510,此層之雜 質宜選擇擴散係數較小者,一般p型植入鎵化“丨丨⑽),n 型植入珅(Asenic) ’其摻雜濃度約為5χ l〇i5at〇m/cm3至5x 1016atom/cm3,經高溫活化或擴散後,其接面深度為屯,一 般約為40 //m至50 //Hi,此時因第2型摻雜之濃度較第j型第 二中度摻雜之512、514為高,故在第2型摻雜之第丨型摻雜 被中和而仍為第2型摻雜。第1型第二中度摻雜層僅存在於 Pji接面附近、如第5圖(b)及(c)所示。最後再以擴散法將、 第1型间濃度摻雜之第三雜質擴散進入第2型之雜質擴散層 5 0 6 5 1 0 ’形成重摻雜之接觸區$ 〇 4、5 1 3以作歐姆接觸之 需。最後完成蝕刻U形隔離溝槽516、金屬化、保護層 (passivation)、封裝等後續製程,皆係習知者,在此不 第6圖係依據本發明之實施例之閘流體在順向阻斷狀 L下外加電壓在閘流體内之電位及空乏區(depiet丨⑽ reg10n)之示意圖。於陽極A至陰極κ順向偏壓下,第工接面 乃為順向偏壓,在第2型擴散層5 06、510内之*多f之淡芦 ,可以略而不計,第2接面L因係逆向偏2,二在第广 二中度摻雜擴散層512、514到達崩潰電壓時即導通, H通Λ壓較基體之崩潰電壓低,雖然接面電容加大,但 因第1型第二中度摻雜擴散層512、514之面積較閘流體之Page 10 200524154 V. Description of the invention (7) Electric valley will not increase. And its positions on the front and back sides are not opposite and intersect each other, as shown in Figure 5 (a). Then, as shown in Figure 5 (b), the conventional method is to implant the second type (p-type in this example) doped with 506 and 510 on both sides of the wafer. The impurity of this layer should be the one with the lower diffusion coefficient. In general, p-type implanted gallium "丨 丨 ⑽", n-type implanted 珅 (Asenic) 'the doping concentration is about 5x10i5at〇m / cm3 to 5x1016atom / cm3, after activation or diffusion at high temperature, The junction depth is about 40 // m to 50 // Hi. At this time, because the concentration of type 2 doping is higher than that of 512 and 514 of the second moderate doping of j type, The second type doping is neutralized and is still the second type doping. The second moderate doping layer of the first type exists only near the Pji junction, as shown in Figure 5 (b) and (c). ). Finally, the third impurity doped with the inter-type 1 concentration is diffused into the second-type impurity diffusion layer 5 0 6 5 1 0 ′ by the diffusion method to form a heavily doped contact region $ 〇4, 5 13 for the ohmic contact. Finally, the subsequent processes such as etching the U-shaped isolation trench 516, metallization, passivation, packaging, etc. are all known to the person. Here, FIG. 6 is based on the present invention. Examples of brake fluid Schematic diagram of the potential of the applied voltage in the sluice fluid and the depleted region (depiet ⑽ reg10n) under the blocking L. Under the forward bias of the anode A to the cathode κ, the first junction is the forward bias. The type 2 diffusion layer 5 in 06 and 510 can be ignored, and the second junction L is reversely biased to 2, and the second wide-doped diffusion layer 512 and 514 reach the breakdown voltage. It is turned on immediately, and the H through Λ voltage is lower than the breakdown voltage of the substrate. Although the junction capacitance is increased, the area of the first type second moderately doped diffusion layers 512 and 514 is larger than that of the gate fluid.

200524154200524154

五、發明說明(8) 面積小’故電容並未增加,反可減少。此一機制為本發明 之重大發現。在降低基板摻雜濃度使接面電容減少之後, 利用離子植入之第1型第二中度摻雜擴散層位於第2型擴散 層5 0 6、5 1 0之下,其摻雜濃度較高,使崩潰電壓由%決定 得以降低,使切入電壓降低至原來之額定值。 ' 第7圖係依據本發明之實施例之二閘流體在順向導通 狀態下之接面電容之等效電路圖。於順向偏壓下,第丨、3 接面乃、Js之電容,設為Q,第2接面八因係逆向偏壓,其 電容設為匕,此二電容為串聯,如第7圖左邊之等效電路、, 右邊為反面之另一閘流體之電容,設為,、&,。此正反 ,之電容並聯即為閘流體之電』。依據本發 特、基板之摻雜濃度為lx 1〇15aWcm3,其等電效=〇◦伙 ,;若用本發明之結構,基板之摻雜濃=面電, 20% » ^-1 # ^ 又杉雜所佔之面積為總面積之1/5,即 2〇% 則電谷應為C = 85pfx 0.2+85X 0.8 = 24pf。故# + 貫施例,切人電壓可保持為300 P故依此一 少侧之水準,有效解決接面電容太大接之面問電:。亦可減 楚描述本創作之特徵^ ⑯例之_ 34,係希望能更加清 具體實例來對本發而並2以上述所揭露的較佳 希望能涵蓋各種嘴加以限制。相反的,其目的是 變及具相等性的安排於本發明所欲申請V. Description of the invention (8) The area is small, so the capacitance has not increased, but can be reduced instead. This mechanism is a significant discovery of the present invention. After the substrate doping concentration is reduced to reduce the junction capacitance, the first type second moderately doped diffusion layer using ion implantation is located below the second type diffusion layers 5 0 6 and 5 1 0. High, the breakdown voltage can be reduced by%, and the cut-in voltage can be reduced to the original rated value. 'Figure 7 is an equivalent circuit diagram of the junction capacitance of the second gate fluid in the forward conduction state according to the embodiment of the present invention. Under forward bias, the capacitance of junction 丨, 3, and Js is set to Q, and the second junction is due to reverse bias, and its capacitance is set to d. The two capacitors are connected in series, as shown in Figure 7 The equivalent circuit on the left, and the capacitance of the other sluice fluid on the right, are set to ,, &,. If the positive and negative capacitances are connected in parallel, the electricity of the sluice fluid is obtained. According to the present invention, the doping concentration of the substrate is 1 × 1015aWcm3, and its equivalent electrical efficiency is equal to 0 °. If the structure of the present invention is used, the doping concentration of the substrate = surface electricity, 20% »^ -1 # ^ The area occupied by Shanshan is 1/5 of the total area, that is, 20%. The valley of electricity should be C = 85pfx 0.2 + 85X 0.8 = 24pf. So # + throughout the example, the cut-in voltage can be maintained at 300 P, so based on this low level, it can effectively solve the problem of too much contact capacitance: It is also possible to reduce the description of the characteristics of this creation ^ ⑯ 例 的 _34. It is hoped that more specific examples can be used to limit the present disclosure and 2 with the better hopes disclosed above. On the contrary, the purpose is to change and arrange the same

200524154 五、發明說明(9) 之專利範疇内。 limi -200524154 圖式簡單說明 5 ·圖式簡單說明: 第1圖顯示先前技術閘流體之習知構造。 第2圖為習知構造之閘流體在加上順向偏壓時之電壓降及 空乏區之示意圖。 第3圖為先前技術之閘流體之構造剖面圖。 第4圖係依據本發明之一實施例之閘流體構造之平面圖。 第5圖係依據本發明之實施例之閘流體緣第4圖之A_A線之 製造流程之剖面圖。 第6圖係依據本發明之實施例之閘流體在順向阻斷狀態下 外加電壓在閘流體内之電位及空乏區(depletion region)之示意圖。 第7圖係依據本發明之實施例之二閘流體在順向導通狀離、 下之接面電容之等效電路圖。 符號說明: 1 02 η型層 106 η型基體 202第一ηρ接面 206第三ηρ接面 3 0 4 陽極 31 0 ρ型摻雜 104 108 204 302 306 312 Ρ型層 Ρ型層 第二Ρη接面 陽極200524154 V. Description of invention (9) within the scope of patent. limi -200524154 Brief description of the diagram 5 · Brief description of the diagram: Figure 1 shows the conventional structure of the prior art brake fluid. Figure 2 is a schematic diagram of the voltage drop and empty region of the conventionally constructed sluice fluid when a forward bias is applied. FIG. 3 is a cross-sectional view of the structure of the prior art sluice fluid. FIG. 4 is a plan view of a sluice structure according to an embodiment of the present invention. Fig. 5 is a cross-sectional view of the manufacturing process of line A_A in Fig. 4 of the sluice edge according to the embodiment of the present invention. FIG. 6 is a schematic diagram of a potential and a depletion region of an applied voltage in the sluice fluid in a forward blocking state according to an embodiment of the present invention. Fig. 7 is an equivalent circuit diagram of the junction capacitance of the second gate fluid in the forward and backward directions according to the embodiment of the present invention. DESCRIPTION OF SYMBOLS: 1 02 η-type layer 106 η-type substrate 202 first ηρ junction 206 third ηρ junction 3 0 4 anode 31 0 ρ-type doping 104 108 204 302 306 312 P-type layer P-type layer second Pη-connection Face anode

20052415七 圖式簡單說明 502第1型基板 504、513 第1型高濃度摻雜之第三雜質擴散層 506、510 第2型第一擴散層 512、514 第1型第二中度摻雜層 5 1 6 U形隔離溝槽20052415 Seven diagrams briefly explain 502 type 1 substrates 504, 513 type 1 highly doped third impurity diffusion layers 506, 510 type 2 first diffusion layers 512, 514 type 1 second moderately doped layers 5 1 6 U-shaped isolation trench

第15頁Page 15

Claims (1)

200524154 六、申請專利範圍 ' '" 1二 種閘流體構造’在基板摻雜濃度降低以降低接 面電容後,在陽極增加/層中度摻雜之雜質擴散層,於閘 流體在順向偏壓時,第二接面為逆向偏壓,其崩潰電壓由 中度摻雜之雜質擴散層決定,以降低切入電壓(switching voltage),至少包含: 一弟1型基板,其摻雜濃度適合所需較小之接面電 容; ^基板之正反面之第2型第一雜質擴散層,由擴散係數 較低之雜質形成,其接面A之深度為山; 基板之正反面之第2型第一雜質擴散層下之第1型第二 中度摻雜之雜質擴散層,正反面之第1型第二中度摻雜之 1質擴散層不相對而相互交錯,其擴散深於第2型第一雜 質擴散層,而在第2型第一雜質擴散層之下,其接面深度 為d2 ; 基板之正反面之第1型第三雜質擴散層,位於第2型第 雜質擴政層内’為高濃度摻雜,與金屬形成歐姆接觸。 2 ·如申請專利範圍第1項之閘流體構造,其中第1型基 板為矽基板。 3 ·如申請專利範圍第1項之閘流體構造,其中第1型基 反之推雜濃度為5x l〇13atom /cm3 至9x 1014at〇ffl/cm3。 4·如申請專利範圍第丨項之閘流體構造,其中第2型第200524154 VI. Application scope of patent '" 1 Two types of gate fluid structure' After the substrate doping concentration is reduced to reduce the junction capacitance, an anode diffusion layer with a moderately doped impurity diffusion layer is added to the gate fluid. When biasing, the second junction is reverse biased, and its breakdown voltage is determined by the moderately doped impurity diffusion layer to reduce the switching voltage. At least: a type 1 substrate with a suitable doping concentration Smaller junction capacitance required; ^ Type 2 first impurity diffusion layer on the front and back sides of the substrate, formed of impurities with a lower diffusion coefficient, and the depth of the junction A is mountain; Type 2 on the front and back sides of the substrate The first type second moderately doped impurity diffusion layer under the first impurity diffusion layer, and the first type second moderately doped first mass diffusion layers on the front and back sides are not opposed to each other and intersect with each other, and the diffusion is deeper than that of the second type. The first impurity diffusion layer of the first type, and the junction depth below the second type of the first impurity diffusion layer is d2; the first type of the third impurity diffusion layer on the front and back of the substrate is located on the second type of the second impurity diffusion layer. Inside 'is a high concentration doping, forming an ohmic connection with the metal touch. 2 · The sluice fluid structure of item 1 of the patent application scope, in which the type 1 substrate is a silicon substrate. 3. The sluice fluid structure of item 1 in the scope of patent application, in which the type 1 base conversely has a dopant concentration of 5 x 1013 atom / cm3 to 9 x 1014 at 0ffl / cm3. 4. If the gate fluid structure of the scope of patent application item 丨, type 2 第16頁 200524154 六、申請專利範圍 一雜質擴散層之雜質為鎵(Gal 1 ium)。 5 ·如申請專利範圍第1項之閘流體構造,其中第2型第 一雜質擴散層之雜質為硼(B〇ron)。 6 ·如申請專利範圍第1項之閘流體構造,其中第2型第 一雜質擴散層之雜質若為η型則為磷(ph〇shorous)。 7.如申請專利範圍第1項之閘流體構造,其中第2型第 一雜質擴散層之摻雜濃度為5 X 1 〇14at〇m/cm3至5 χ 1 〇15 atom/cm3 〇 8 ·如申請專利範圍第1項之閘流體構造,其中第2型第 一雜質擴散層之接面深度dl為1〇 至20 //in。 9.如申請專利範圍第1項之閘流體構造,其中第1型第 二中度摻雜之雜質擴散層之摻雜濃度為5χ 至5 X 1015atom/cm3 〇 1 0 ·如申請專利範圍第丨項之閘流體構造,其中第i型 第二中度掺雜之雜質擴散層之之面積為閘流體面積之1/2 至 1/5。 11·如申請專利範圍第i項之閘流體構造,其中第1型Page 16 200524154 6. Scope of patent application The impurity of the impurity diffusion layer is gallium (Gal 1 ium). 5. The sluice fluid structure according to item 1 of the scope of patent application, wherein the impurity of the second type impurity diffusion layer is boron. 6. The gate fluid structure of item 1 of the scope of patent application, wherein the impurity of the second type first impurity diffusion layer is phosphorous (phoshorous) if it is n-type. 7. The sluice fluid structure according to item 1 of the scope of patent application, wherein the doping concentration of the second type first impurity diffusion layer is 5 X 1 〇14at〇m / cm3 to 5 χ 1 〇15 atom / cm3 〇8 The sluice fluid structure of the first item of the patent application scope, wherein the junction depth d1 of the second type first impurity diffusion layer is 10 to 20 // in. 9. For example, the gate fluid structure of the scope of the patent application, wherein the doping concentration of the type 1 second moderately doped impurity diffusion layer is 5χ to 5 X 1015 atom / cm3 〇1 0 The sluice fluid structure of the item, wherein the area of the i-type second moderately doped impurity diffusion layer is 1/2 to 1/5 of the sluice fluid area. 11. The gate fluid structure of item i in the scope of patent application, of which type 1 第17頁. 200524154 六、申請專利範圍 第二中度摻雜之雜質擴散層之擴散深度d2為4〇 //m至50 β m 〇 1 j ·種製造閘流體之方法,在基板摻雜濃度降低以 降低接面電容,並在陽極增加一層中度摻雜之雜質擴散 九/货於閘流體在順向偏壓時,第二接面為逆向偏壓,在第 聖第一中度摻雜擴散層到達崩潰電壓時即導通崩潰前導 二步:降低切入電壓(switching voltage)’至少包含下 小之(:)面準電備容一第1型基板’選擇其摻雜濃度使適合所需較 換雜lb 在^基板之正反面利用離子植入形成第1型第二中度 不相對而相St層’正反面之第二中度摻雜之雜質擴散層 不相對而相互交錯’其接面之深度為屯; 一雜板之/反面利用擴散方式或離子植人第2型第 深ΠΓ 散係數較低之雜質❹,其接面J2之 式或(離d)子在植第2^:中度摻雜之雜質擴散層内利用擴散方 以與金屬形成歐姆接觸; 4之第二雜質擴散層, (〇完成金屬化、蝕刻、隔離、封裝等製程。 石夕基1 板3·。如申請專利範圍第12項之方法,其中第1型基板為 -200524154 六、申請專利範圍 1 4·如申請專利範圍第丨2項之方法,其中第1型基板之 摻雜濃度為5χ l〇13at〇m/cm3 至 l〇14at〇m/Cffl3。 1 5·如申請專利範圍第丨2項之方法,其中第2型第一雜 貝擴月欠層之雜質為錄(Galium)。 1 6·如申請專利範圍第丨2項之方法,其中第2型第一雜 質擴散層之雜質為硼(Boron)。 17·如申請專利範圍第12項之方法,其中第2型第一雜 吳擴政層之雜質若為η型則為填(phoshorous)。 18·如申請專利範圍第12項之方法,其中第2型第一雜 質擴散層之摻雜濃度為5x 1〇15atom/cm3至5x i〇16at〇m/cm 3 〇 1 9·如申請專利範圍第丨2項之方法,其中第2型第一雜 質擴散層之接面深度屯為20//111至40//m。 20.如申請專利範圍第12項之方法,其中第1型第二中 度4雜之雜貝擴政層之推雜濃度為i〇i4at〇/cm3至1〇 15atom/cm3 °Page 17. 200524154 Sixth, the scope of the patent application The second moderately doped impurity diffusion layer has a diffusion depth d2 of 4 // m to 50 β m 〇1 j · A method for manufacturing a gate fluid, doping concentration on the substrate Reduce to reduce the junction capacitance, and add a layer of moderately doped impurities to the anode. When the gate fluid is forward biased, the second junction is reverse biased and moderately doped in the first. When the diffusion layer reaches the breakdown voltage, it will turn on and collapse. The first two steps: reduce the switching voltage (at least including the lower (:) plane quasi-electrical reserve capacity-a type 1 substrate). Select its doping concentration to suit the required The impurity lb is formed on the front and back sides of the substrate by ion implantation to form a type 1 second moderately non-opposed and phase St layer. The second moderately doped impurity diffusion layers on the front and back sides are not opposed and staggered with each other. The depth of the surface is Tun; a heterogeneous plate / the reverse side uses the diffusion method or ion implantation of the second type of the second deep ΠΓ impurity coefficient with a lower dispersion coefficient, the interface J2 formula or (from d) on the second planting ^: Diffusion is used in the moderately doped impurity diffusion layer to form ohmic contact with the metal; 4 The second impurity diffusion layer (0 completes the processes of metallization, etching, isolation, packaging, etc.) Shi Xiji 1 Board 3. If the method of applying for the scope of the patent No. 12, wherein the type 1 substrate is -200524154 VI. Application Patent scope 1 4 · As in the method of applying for patent scope item 丨 2, wherein the doping concentration of the type 1 substrate is 5 × 1013at〇m / cm3 to 1014at〇m / Cffl3. 1 5 · If the scope of patent application The method according to item 丨 2, in which the impurities of the second type of the first miscellaneous expansion layer are Galium. 1 6 · As in the method of item No. 丨 2 in the scope of patent application, wherein the second type is the first impurity diffusion layer The impurity is boron. 17 · If the method of the scope of patent application No. 12, wherein the impurities of the second type of the first heterogeneous Wuzheng layer is η-type, then it is phoshorous. 18 · If the scope of patent application is the 12th The method of item 2, wherein the doping concentration of the second type first impurity diffusion layer is 5x1015 atom / cm3 to 5x1016at〇m / cm3 〇1. 9 The method of the second item of the patent application, wherein The junction depth of the second type first impurity diffusion layer is 20 // 111 to 40 // m. The method of 2 items, in which the impurity concentration of the type 1 second medium 4 miscellaneous shell expansion layer is i0i4at〇 / cm3 to 1〇15atom / cm3 ° 第19頁 20052415^ 六、申請專利範圍 2 1.如申請專利範圍第1 2項之方法,其中第1型第二中 度摻雜之雜質擴散層之之面積為閘流體面積之1 / 5至1 / 2。 2 1.如申請專利範圍第1 2項之方法,其中第1型第二中 度摻雜之雜質擴散層之接面深度d2為40//111至50//m。Page 19, 20052415 ^ VI. Patent Application Range 2 1. The method as described in item 12 of the patent application range, wherein the area of type 1 second moderately doped impurity diffusion layer is 1/5 of the area of the gate fluid 1/2. 2 1. The method according to item 12 of the scope of patent application, wherein the junction depth d2 of the first type second moderately doped impurity diffusion layer is 40 // 111 to 50 // m. 第20頁Page 20
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CN109841690A (en) * 2017-11-27 2019-06-04 百福林企业股份有限公司 Low two end brake fluid of capacitor construction and its manufacturing method

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TWI704689B (en) * 2017-09-06 2020-09-11 百福林企業股份有限公司 A structure and manufacturing method of low capacitance two terminal thyristor

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109841690A (en) * 2017-11-27 2019-06-04 百福林企业股份有限公司 Low two end brake fluid of capacitor construction and its manufacturing method

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