TW200520382A - Dynamic logic return-to-zero latching mechanism - Google Patents

Dynamic logic return-to-zero latching mechanism

Info

Publication number
TW200520382A
TW200520382A TW093137336A TW93137336A TW200520382A TW 200520382 A TW200520382 A TW 200520382A TW 093137336 A TW093137336 A TW 093137336A TW 93137336 A TW93137336 A TW 93137336A TW 200520382 A TW200520382 A TW 200520382A
Authority
TW
Taiwan
Prior art keywords
logic
evaluation
latching
zero
signal
Prior art date
Application number
TW093137336A
Other languages
English (en)
Other versions
TWI301357B (en
Inventor
James R Lundberg
Original Assignee
Ip First Llc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ip First Llc filed Critical Ip First Llc
Publication of TW200520382A publication Critical patent/TW200520382A/zh
Application granted granted Critical
Publication of TWI301357B publication Critical patent/TWI301357B/zh

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/096—Synchronous circuits, i.e. using clock signals
    • H03K19/0963—Synchronous circuits, i.e. using clock signals using transistors of complementary type
TW093137336A 2003-12-06 2004-12-03 Dynamic logic return-to-zero latching mechanism TWI301357B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/730,168 US7173456B2 (en) 2002-12-10 2003-12-06 Dynamic logic return-to-zero latching mechanism

Publications (2)

Publication Number Publication Date
TW200520382A true TW200520382A (en) 2005-06-16
TWI301357B TWI301357B (en) 2008-09-21

Family

ID=34523008

Family Applications (1)

Application Number Title Priority Date Filing Date
TW093137336A TWI301357B (en) 2003-12-06 2004-12-03 Dynamic logic return-to-zero latching mechanism

Country Status (4)

Country Link
US (1) US7173456B2 (zh)
EP (1) EP1542365B1 (zh)
CN (1) CN1331307C (zh)
TW (1) TWI301357B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI387201B (zh) * 2005-06-30 2013-02-21 Intellectual Venture Funding Llc 動態電路閂鎖器

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7002374B2 (en) * 2003-02-12 2006-02-21 Stmicroelectronics, Inc. Domino logic compatible scannable flip-flop
JP2007096907A (ja) * 2005-09-29 2007-04-12 Matsushita Electric Ind Co Ltd 半導体集積回路
WO2009033184A2 (en) * 2007-09-06 2009-03-12 Picogem Corp. Clock guided logic with reduced switching
US8836371B2 (en) * 2013-01-22 2014-09-16 Freescale Semiconductor, Inc. Systems and methods for reduced coupling between digital signal lines
US10581410B2 (en) * 2015-09-10 2020-03-03 Samsung Electronics Co., Ltd High speed domino-based flip flop

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3940916A1 (de) * 1989-12-12 1991-06-13 Stabilus Gmbh Teleskopierbare verstelleinrichtung mit loesbarer arretierung
US5075386A (en) 1990-04-12 1991-12-24 Eastman Kodak Company Cross-linkable hot-melt adhesive and method of producing same
JPH09511117A (ja) * 1995-01-25 1997-11-04 アドバンスド マイクロ デバイシズ，インコーポレーテッド 複数の伝達ゲートを有する高速ラッチ回路及びそれを用いるパイプライン化されたマイクロプロセッサー
US5774005A (en) * 1995-09-11 1998-06-30 Advanced Micro Devices, Inc. Latching methodology
US5889979A (en) * 1996-05-24 1999-03-30 Hewlett-Packard, Co. Transparent data-triggered pipeline latch
US6002285A (en) * 1996-05-28 1999-12-14 International Business Machines Corporation Circuitry and method for latching information
US5796282A (en) * 1996-08-12 1998-08-18 Intel Corporation Latching mechanism for pulsed domino logic with inherent race margin and time borrowing
US5828234A (en) * 1996-08-27 1998-10-27 Intel Corporation Pulsed reset single phase domino logic
CA2303297C (en) 1997-09-16 2008-11-25 Information Resource Engineering, Inc. Cryptographic co-processor
US6075386A (en) 1997-10-22 2000-06-13 Hewlett-Packard Company Dynamic logic gate with relaxed timing requirements and output state holding
US6133759A (en) * 1998-06-16 2000-10-17 International Business Machines Corp. Decoupled reset dynamic logic circuit
US6111444A (en) * 1998-08-20 2000-08-29 International Business Machines Corporation Edge triggered latch
US6181180B1 (en) * 1999-06-28 2001-01-30 Intel Corporation Flip-flop circuit
US6201415B1 (en) * 1999-08-05 2001-03-13 Intel Corporation Latched time borrowing domino circuit
US6265897B1 (en) * 1999-12-17 2001-07-24 Hewlett-Packard Company Contention based logic gate driving a latch and driven by pulsed clock
US6775776B1 (en) 2000-06-27 2004-08-10 Intel Corporation Biometric-based authentication in a nonvolatile memory device
US6549038B1 (en) * 2000-09-14 2003-04-15 University Of Washington Method of high-performance CMOS design
US6498514B2 (en) * 2001-04-30 2002-12-24 Intel Corporation Domino circuit
US6956406B2 (en) * 2001-07-02 2005-10-18 Intrinsity, Inc. Static storage element for dynamic logic
GB0121013D0 (en) * 2001-08-30 2001-10-24 Micron Technology Inc Combined dynamic logic gate and level shifter and method employing same
US6693459B2 (en) * 2001-09-17 2004-02-17 Fujitsu Limited Method and system for improving speed in a flip-flop
US6686775B2 (en) * 2002-04-22 2004-02-03 Broadcom Corp Dynamic scan circuitry for B-phase
US6791365B2 (en) * 2002-11-29 2004-09-14 Texas Instruments Incorporated Dynamic logic circuits using transistors having differing threshold voltages and delayed low threshold voltage leakage protection
US7212039B2 (en) * 2003-08-27 2007-05-01 Via Technologies, Inc. Dynamic logic register

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI387201B (zh) * 2005-06-30 2013-02-21 Intellectual Venture Funding Llc 動態電路閂鎖器

Also Published As

Publication number Publication date
EP1542365B1 (en) 2012-05-02
CN1617448A (zh) 2005-05-18
TWI301357B (en) 2008-09-21
US20050055538A1 (en) 2005-03-10
EP1542365A1 (en) 2005-06-15
US7173456B2 (en) 2007-02-06
CN1331307C (zh) 2007-08-08

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