TW200520191A - Structure and method for reinforcing a bond pad on a chip - Google Patents
Structure and method for reinforcing a bond pad on a chipInfo
- Publication number
- TW200520191A TW200520191A TW093116709A TW93116709A TW200520191A TW 200520191 A TW200520191 A TW 200520191A TW 093116709 A TW093116709 A TW 093116709A TW 93116709 A TW93116709 A TW 93116709A TW 200520191 A TW200520191 A TW 200520191A
- Authority
- TW
- Taiwan
- Prior art keywords
- bonding pad
- chip
- reinforcing
- dielectric layer
- bond pad
- Prior art date
Links
- 230000003014 reinforcing effect Effects 0.000 title abstract 2
- 238000004873 anchoring Methods 0.000 abstract 1
- 238000005336 cracking Methods 0.000 abstract 1
- 238000013031 physical testing Methods 0.000 abstract 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H—ELECTRICITY
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
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- H01L2224/05001—Internal layers
- H01L2224/05073—Single internal layer
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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- H01L2224/05001—Internal layers
- H01L2224/05075—Plural internal layers
- H01L2224/0508—Plural internal layers being stacked
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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- H01L2224/05599—Material
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
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- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/852—Applying energy for connecting
- H01L2224/85201—Compression bonding
- H01L2224/85205—Ultrasonic bonding
- H01L2224/85207—Thermosonic bonding
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- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/85399—Material
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- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2924/01013—Aluminum [Al]
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- H01L2924/01014—Silicon [Si]
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- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
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- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/731,983 US7081679B2 (en) | 2003-12-10 | 2003-12-10 | Structure and method for reinforcing a bond pad on a chip |
Publications (2)
Publication Number | Publication Date |
---|---|
TW200520191A true TW200520191A (en) | 2005-06-16 |
TWI319227B TWI319227B (en) | 2010-01-01 |
Family
ID=34652785
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW093116709A TWI319227B (en) | 2003-12-10 | 2004-06-10 | Structure and method for reinforcing a bond pad on a chip |
Country Status (2)
Country | Link |
---|---|
US (1) | US7081679B2 (zh) |
TW (1) | TWI319227B (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI612648B (zh) * | 2009-07-29 | 2018-01-21 | 台灣積體電路製造股份有限公司 | 正面受光型影像感測器 |
Families Citing this family (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060009038A1 (en) * | 2004-07-12 | 2006-01-12 | International Business Machines Corporation | Processing for overcoming extreme topography |
JP4517843B2 (ja) * | 2004-12-10 | 2010-08-04 | エルピーダメモリ株式会社 | 半導体装置 |
US7241636B2 (en) * | 2005-01-11 | 2007-07-10 | Freescale Semiconductor, Inc. | Method and apparatus for providing structural support for interconnect pad while allowing signal conductance |
TWI288464B (en) * | 2005-11-25 | 2007-10-11 | Richtek Technology Corp | Circuit under pad and method of forming a pad |
US20070212867A1 (en) * | 2006-03-07 | 2007-09-13 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method and structure for improving bonding reliability in bond pads |
US20070267748A1 (en) * | 2006-05-16 | 2007-11-22 | Tran Tu-Anh N | Integrated circuit having pads and input/output (i/o) cells |
US7808117B2 (en) * | 2006-05-16 | 2010-10-05 | Freescale Semiconductor, Inc. | Integrated circuit having pads and input/output (I/O) cells |
US7276435B1 (en) * | 2006-06-02 | 2007-10-02 | Freescale Semiconductor, Inc. | Die level metal density gradient for improved flip chip package reliability |
US20080093749A1 (en) * | 2006-10-20 | 2008-04-24 | Texas Instruments Incorporated | Partial Solder Mask Defined Pad Design |
US7749885B2 (en) * | 2006-12-15 | 2010-07-06 | Micron Technology, Inc. | Semiconductor processing methods, methods of forming contact pads, and methods of forming electrical connections between metal-containing layers |
US8134235B2 (en) * | 2007-04-23 | 2012-03-13 | Taiwan Semiconductor Manufacturing Co., Ltd. | Three-dimensional semiconductor device |
JP4953132B2 (ja) * | 2007-09-13 | 2012-06-13 | 日本電気株式会社 | 半導体装置 |
US7786584B2 (en) * | 2007-11-26 | 2010-08-31 | Infineon Technologies Ag | Through substrate via semiconductor components |
US8053900B2 (en) * | 2008-10-21 | 2011-11-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Through-substrate vias (TSVs) electrically connected to a bond pad design with reduced dishing effect |
US8446006B2 (en) | 2009-12-17 | 2013-05-21 | International Business Machines Corporation | Structures and methods to reduce maximum current density in a solder ball |
US9214385B2 (en) | 2009-12-17 | 2015-12-15 | Globalfoundries Inc. | Semiconductor device including passivation layer encapsulant |
KR101123802B1 (ko) * | 2010-04-15 | 2012-03-12 | 주식회사 하이닉스반도체 | 반도체 칩 |
CN201780975U (zh) * | 2010-07-30 | 2011-03-30 | 国基电子(上海)有限公司 | 焊盘及具有该焊盘的封装芯片 |
US8492892B2 (en) | 2010-12-08 | 2013-07-23 | International Business Machines Corporation | Solder bump connections |
US20120281377A1 (en) * | 2011-05-06 | 2012-11-08 | Naveen Kini | Vias for mitigating pad delamination |
US9508617B2 (en) * | 2012-03-02 | 2016-11-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Test chip, test board and reliability testing method |
US9773732B2 (en) | 2013-03-06 | 2017-09-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and apparatus for packaging pad structure |
CN107845622B (zh) * | 2017-12-04 | 2022-04-08 | 长鑫存储技术有限公司 | 具有硅穿孔的芯片堆叠体及其制造方法 |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08293523A (ja) * | 1995-02-21 | 1996-11-05 | Seiko Epson Corp | 半導体装置およびその製造方法 |
JP3482779B2 (ja) * | 1996-08-20 | 2004-01-06 | セイコーエプソン株式会社 | 半導体装置およびその製造方法 |
JP3121311B2 (ja) * | 1998-05-26 | 2000-12-25 | 日本電気株式会社 | 多層配線構造及びそれを有する半導体装置並びにそれらの製造方法 |
JP2974022B1 (ja) * | 1998-10-01 | 1999-11-08 | ヤマハ株式会社 | 半導体装置のボンディングパッド構造 |
US6037668A (en) * | 1998-11-13 | 2000-03-14 | Motorola, Inc. | Integrated circuit having a support structure |
US6657302B1 (en) * | 1999-01-12 | 2003-12-02 | Agere Systems Inc. | Integration of low dielectric material in semiconductor circuit structures |
US6028367A (en) * | 1999-05-07 | 2000-02-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bonds pads equipped with heat dissipating rings and method for forming |
US6306749B1 (en) * | 1999-06-08 | 2001-10-23 | Winbond Electronics Corp | Bond pad with pad edge strengthening structure |
US6198170B1 (en) * | 1999-12-16 | 2001-03-06 | Conexant Systems, Inc. | Bonding pad and support structure and method for their fabrication |
JP2001196413A (ja) * | 2000-01-12 | 2001-07-19 | Mitsubishi Electric Corp | 半導体装置、該半導体装置の製造方法、cmp装置、及びcmp方法 |
US6362531B1 (en) * | 2000-05-04 | 2002-03-26 | International Business Machines Corporation | Recessed bond pad |
TW484196B (en) * | 2001-06-05 | 2002-04-21 | United Microelectronics Corp | Bonding pad structure |
JP2003031575A (ja) * | 2001-07-17 | 2003-01-31 | Nec Corp | 半導体装置及びその製造方法 |
US6680484B1 (en) * | 2002-10-22 | 2004-01-20 | Texas Instruments Incorporated | Space efficient interconnect test multi-structure |
US7023090B2 (en) * | 2003-01-29 | 2006-04-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bonding pad and via structure design |
JP3802002B2 (ja) * | 2003-03-27 | 2006-07-26 | 三星電子株式会社 | 半導体装置の製造方法 |
CN1601735B (zh) * | 2003-09-26 | 2010-06-23 | 松下电器产业株式会社 | 半导体器件及其制造方法 |
-
2003
- 2003-12-10 US US10/731,983 patent/US7081679B2/en not_active Expired - Lifetime
-
2004
- 2004-06-10 TW TW093116709A patent/TWI319227B/zh active
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI612648B (zh) * | 2009-07-29 | 2018-01-21 | 台灣積體電路製造股份有限公司 | 正面受光型影像感測器 |
Also Published As
Publication number | Publication date |
---|---|
US20050127529A1 (en) | 2005-06-16 |
TWI319227B (en) | 2010-01-01 |
US7081679B2 (en) | 2006-07-25 |
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