TW200520150A - A method for forming dummy structures for improved CMP and reduced capacitance - Google Patents
A method for forming dummy structures for improved CMP and reduced capacitanceInfo
- Publication number
- TW200520150A TW200520150A TW093118493A TW93118493A TW200520150A TW 200520150 A TW200520150 A TW 200520150A TW 093118493 A TW093118493 A TW 093118493A TW 93118493 A TW93118493 A TW 93118493A TW 200520150 A TW200520150 A TW 200520150A
- Authority
- TW
- Taiwan
- Prior art keywords
- dummy structures
- reduced capacitance
- forming
- forming dummy
- cmp
- Prior art date
Links
- 238000000034 method Methods 0.000 title abstract 4
- 238000005498 polishing Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/926—Dummy metallization
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/728,999 US6849549B1 (en) | 2003-12-04 | 2003-12-04 | Method for forming dummy structures for improved CMP and reduced capacitance |
Publications (2)
Publication Number | Publication Date |
---|---|
TW200520150A true TW200520150A (en) | 2005-06-16 |
TWI241682B TWI241682B (en) | 2005-10-11 |
Family
ID=34080863
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW093118493A TWI241682B (en) | 2003-12-04 | 2004-06-25 | A method for forming dummy structures for improved CMP and reduced capacitance |
Country Status (2)
Country | Link |
---|---|
US (1) | US6849549B1 (zh) |
TW (1) | TWI241682B (zh) |
Families Citing this family (48)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4005873B2 (ja) * | 2002-08-15 | 2007-11-14 | 株式会社東芝 | 半導体装置 |
US7176144B1 (en) | 2003-03-31 | 2007-02-13 | Novellus Systems, Inc. | Plasma detemplating and silanol capping of porous dielectric films |
US7241704B1 (en) | 2003-03-31 | 2007-07-10 | Novellus Systems, Inc. | Methods for producing low stress porous low-k dielectric materials using precursors with organic functional groups |
US7265061B1 (en) | 2003-05-09 | 2007-09-04 | Novellus Systems, Inc. | Method and apparatus for UV exposure of low dielectric constant materials for porogen removal and improved mechanical properties |
US7390537B1 (en) | 2003-11-20 | 2008-06-24 | Novellus Systems, Inc. | Methods for producing low-k CDO films with low residual stress |
US7381662B1 (en) | 2004-03-11 | 2008-06-03 | Novellus Systems, Inc. | Methods for improving the cracking resistance of low-k dielectric materials |
US7341761B1 (en) | 2004-03-11 | 2008-03-11 | Novellus Systems, Inc. | Methods for producing low-k CDO films |
US7781351B1 (en) | 2004-04-07 | 2010-08-24 | Novellus Systems, Inc. | Methods for producing low-k carbon doped oxide films with low residual stress |
US7253125B1 (en) | 2004-04-16 | 2007-08-07 | Novellus Systems, Inc. | Method to improve mechanical strength of low-k dielectric film using modulated UV exposure |
US7622400B1 (en) | 2004-05-18 | 2009-11-24 | Novellus Systems, Inc. | Method for improving mechanical properties of low dielectric constant materials |
US20060024958A1 (en) * | 2004-07-29 | 2006-02-02 | Abbas Ali | HSQ/SOG dry strip process |
US7326444B1 (en) | 2004-09-14 | 2008-02-05 | Novellus Systems, Inc. | Methods for improving integration performance of low stress CDO films |
US9659769B1 (en) | 2004-10-22 | 2017-05-23 | Novellus Systems, Inc. | Tensile dielectric films using UV curing |
US7695765B1 (en) | 2004-11-12 | 2010-04-13 | Novellus Systems, Inc. | Methods for producing low-stress carbon-doped oxide films with improved integration properties |
US7166531B1 (en) | 2005-01-31 | 2007-01-23 | Novellus Systems, Inc. | VLSI fabrication processes for introducing pores into dielectric materials |
US7510982B1 (en) | 2005-01-31 | 2009-03-31 | Novellus Systems, Inc. | Creation of porosity in low-k films by photo-disassociation of imbedded nanoparticles |
KR100732288B1 (ko) * | 2005-04-15 | 2007-06-25 | 주식회사 하이닉스반도체 | 반도체 소자의 제조 방법 |
US8889233B1 (en) | 2005-04-26 | 2014-11-18 | Novellus Systems, Inc. | Method for reducing stress in porous dielectric films |
US7892985B1 (en) | 2005-11-15 | 2011-02-22 | Novellus Systems, Inc. | Method for porogen removal and mechanical strength enhancement of low-k carbon doped silicon oxide using low thermal budget microwave curing |
US7381644B1 (en) | 2005-12-23 | 2008-06-03 | Novellus Systems, Inc. | Pulsed PECVD method for modulating hydrogen content in hard mask |
US7378308B2 (en) * | 2006-03-30 | 2008-05-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | CMOS devices with improved gap-filling |
US7923376B1 (en) | 2006-03-30 | 2011-04-12 | Novellus Systems, Inc. | Method of reducing defects in PECVD TEOS films |
US7736936B2 (en) * | 2006-08-29 | 2010-06-15 | Semiconductor Energy Laboratory Co., Ltd. | Method of forming display device that includes removing mask to form opening in insulating film |
JP5193542B2 (ja) * | 2007-09-20 | 2013-05-08 | パナソニック株式会社 | 半導体装置の製造方法 |
US20090121353A1 (en) * | 2007-11-13 | 2009-05-14 | Ramappa Deepak A | Dual damascene beol integration without dummy fill structures to reduce parasitic capacitance |
US8129095B2 (en) | 2009-04-08 | 2012-03-06 | International Business Machines Corporation | Methods, photomasks and methods of fabricating photomasks for improving damascene wire uniformity without reducing performance |
TWI503942B (zh) * | 2009-11-11 | 2015-10-11 | United Microelectronics Corp | 一種電路佈局結構 |
CN104362138B (zh) * | 2009-11-23 | 2017-04-12 | 联华电子股份有限公司 | 一种电路布局结构 |
CN102969271A (zh) * | 2011-08-31 | 2013-03-13 | 上海华力微电子有限公司 | 半导体器件及其制作方法 |
CN102446825A (zh) * | 2011-09-23 | 2012-05-09 | 上海华力微电子有限公司 | 一种去除金属层冗余金属填充的制造工艺 |
CN102446827A (zh) * | 2011-09-23 | 2012-05-09 | 上海华力微电子有限公司 | 一种去除金属层冗余金属填充的制造工艺 |
CN102456615B (zh) * | 2011-09-23 | 2014-02-05 | 上海华力微电子有限公司 | 一种去除金属层冗余金属填充的制造工艺 |
CN102446828B (zh) * | 2011-09-23 | 2014-02-05 | 上海华力微电子有限公司 | 一种去除金属层冗余金属填充的制造工艺 |
US8673770B2 (en) * | 2011-10-25 | 2014-03-18 | Globalfoundries Inc. | Methods of forming conductive structures in dielectric layers on an integrated circuit device |
CN102332428A (zh) * | 2011-10-25 | 2012-01-25 | 上海华力微电子有限公司 | 大马士革结构制作方法 |
CN102339792A (zh) * | 2011-10-29 | 2012-02-01 | 上海华力微电子有限公司 | 半导体器件制作方法 |
CN102354682B (zh) * | 2011-10-29 | 2014-04-09 | 上海华力微电子有限公司 | 半导体器件制作方法 |
CN102361019A (zh) * | 2011-10-29 | 2012-02-22 | 上海华力微电子有限公司 | 一种半导体器件制作方法 |
CN102339790A (zh) * | 2011-10-29 | 2012-02-01 | 上海华力微电子有限公司 | 半导体器件制作方法 |
US8883638B2 (en) * | 2012-01-18 | 2014-11-11 | United Microelectronics Corp. | Method for manufacturing damascene structure involving dummy via holes |
US8697515B2 (en) | 2012-06-06 | 2014-04-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of making a FinFET device |
CN102779782A (zh) * | 2012-08-16 | 2012-11-14 | 上海华力微电子有限公司 | 双大马士革浅冗余金属制备工艺 |
US20140342553A1 (en) * | 2013-05-14 | 2014-11-20 | United Microelectronics Corp. | Method for Forming Semiconductor Structure Having Opening |
CN104347583A (zh) * | 2013-07-31 | 2015-02-11 | 国际商业机器公司 | 半导体制造方法、掩模形成方法和半导体结构 |
US9281192B2 (en) * | 2014-03-13 | 2016-03-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | CMP-friendly coatings for planar recessing or removing of variable-height layers |
US9859156B2 (en) * | 2015-12-30 | 2018-01-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Interconnection structure with sidewall dielectric protection layer |
CN108962873B (zh) * | 2018-09-04 | 2023-07-04 | 长鑫存储技术有限公司 | 复合双大马士革结构及其制备方法 |
CN111099554A (zh) * | 2019-11-29 | 2020-05-05 | 杭州臻镭微波技术有限公司 | 一种微系统模组中硅空腔下tsv地互联孔结构的制作方法 |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW396524B (en) * | 1998-06-26 | 2000-07-01 | United Microelectronics Corp | A method for fabricating dual damascene |
US6214745B1 (en) * | 1998-11-19 | 2001-04-10 | United Microelectronics Corp. | Method of improving surface planarity of chemical-mechanical polishing operation by forming shallow dummy pattern |
-
2003
- 2003-12-04 US US10/728,999 patent/US6849549B1/en not_active Expired - Lifetime
-
2004
- 2004-06-25 TW TW093118493A patent/TWI241682B/zh active
Also Published As
Publication number | Publication date |
---|---|
US6849549B1 (en) | 2005-02-01 |
TWI241682B (en) | 2005-10-11 |
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