CN104347583A - 半导体制造方法、掩模形成方法和半导体结构 - Google Patents
半导体制造方法、掩模形成方法和半导体结构 Download PDFInfo
- Publication number
- CN104347583A CN104347583A CN201310328842.5A CN201310328842A CN104347583A CN 104347583 A CN104347583 A CN 104347583A CN 201310328842 A CN201310328842 A CN 201310328842A CN 104347583 A CN104347583 A CN 104347583A
- Authority
- CN
- China
- Prior art keywords
- described metal
- wiring layer
- dielectric
- metal
- filled
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
- H01L21/76892—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances modifying the pattern
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
Claims (19)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201310328842.5A CN104347583A (zh) | 2013-07-31 | 2013-07-31 | 半导体制造方法、掩模形成方法和半导体结构 |
US14/328,760 US9087880B2 (en) | 2013-07-31 | 2014-07-11 | Removing metal fills in a wiring layer |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201310328842.5A CN104347583A (zh) | 2013-07-31 | 2013-07-31 | 半导体制造方法、掩模形成方法和半导体结构 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN104347583A true CN104347583A (zh) | 2015-02-11 |
Family
ID=52426942
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201310328842.5A Pending CN104347583A (zh) | 2013-07-31 | 2013-07-31 | 半导体制造方法、掩模形成方法和半导体结构 |
Country Status (2)
Country | Link |
---|---|
US (1) | US9087880B2 (zh) |
CN (1) | CN104347583A (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN114121793A (zh) * | 2021-11-26 | 2022-03-01 | 长电集成电路(绍兴)有限公司 | 一种多层金属布线层及其制备方法、封装结构 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6608335B2 (en) | 2000-05-25 | 2003-08-19 | Sun Microsystems, Inc. | Grounded fill in a large scale integrated circuit |
US6867127B1 (en) | 2002-12-19 | 2005-03-15 | Lsi Logic Corporation | Diamond metal-filled patterns achieving low parasitic coupling capacitance |
US6849549B1 (en) * | 2003-12-04 | 2005-02-01 | Taiwan Semiconductor Manufacturing Co., Ltd | Method for forming dummy structures for improved CMP and reduced capacitance |
US8129095B2 (en) * | 2009-04-08 | 2012-03-06 | International Business Machines Corporation | Methods, photomasks and methods of fabricating photomasks for improving damascene wire uniformity without reducing performance |
US8138607B2 (en) | 2009-04-15 | 2012-03-20 | International Business Machines Corporation | Metal fill structures for reducing parasitic capacitance |
US8790975B2 (en) * | 2011-03-04 | 2014-07-29 | Globalfoundries Inc. | Semiconductor device comprising a capacitor formed in the metallization system based on dummy metal features |
-
2013
- 2013-07-31 CN CN201310328842.5A patent/CN104347583A/zh active Pending
-
2014
- 2014-07-11 US US14/328,760 patent/US9087880B2/en not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN114121793A (zh) * | 2021-11-26 | 2022-03-01 | 长电集成电路(绍兴)有限公司 | 一种多层金属布线层及其制备方法、封装结构 |
Also Published As
Publication number | Publication date |
---|---|
US20150035153A1 (en) | 2015-02-05 |
US9087880B2 (en) | 2015-07-21 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
TA01 | Transfer of patent application right | ||
TA01 | Transfer of patent application right |
Effective date of registration: 20171101 Address after: Grand Cayman, Cayman Islands Applicant after: GLOBALFOUNDRIES INC. Address before: American New York Applicant before: Core USA second LLC Effective date of registration: 20171101 Address after: American New York Applicant after: Core USA second LLC Address before: American New York Applicant before: International Business Machines Corp. |
|
RJ01 | Rejection of invention patent application after publication | ||
RJ01 | Rejection of invention patent application after publication |
Application publication date: 20150211 |