TW200511319A - Arrangement of non-volatile memory cell transistors, memory array comprising the same and method of making - Google Patents
Arrangement of non-volatile memory cell transistors, memory array comprising the same and method of makingInfo
- Publication number
- TW200511319A TW200511319A TW093117034A TW93117034A TW200511319A TW 200511319 A TW200511319 A TW 200511319A TW 093117034 A TW093117034 A TW 093117034A TW 93117034 A TW93117034 A TW 93117034A TW 200511319 A TW200511319 A TW 200511319A
- Authority
- TW
- Taiwan
- Prior art keywords
- floating gate
- gate
- transistors
- pairs
- arrangement
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 239000002356 single layer Substances 0.000 abstract 1
- 239000000758 substrate Substances 0.000 abstract 1
- 230000005641 tunneling Effects 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7887—Programmable transistors with more than two possible different levels of programmation
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/60—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the control gate being a doped region, e.g. single-poly memory cell
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
- G11C16/0416—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
- G11C2216/02—Structural aspects of erasable programmable read-only memories
- G11C2216/10—Floating gate memory cells with a single polysilicon layer
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
- Read Only Memory (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/465,718 US6888192B2 (en) | 2003-04-25 | 2003-06-18 | Mirror image non-volatile memory cell transistor pairs with single poly layer |
Publications (1)
Publication Number | Publication Date |
---|---|
TW200511319A true TW200511319A (en) | 2005-03-16 |
Family
ID=33551401
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW093117034A TW200511319A (en) | 2003-06-18 | 2004-06-14 | Arrangement of non-volatile memory cell transistors, memory array comprising the same and method of making |
Country Status (5)
Country | Link |
---|---|
US (2) | US6888192B2 (zh) |
EP (1) | EP1636849A2 (zh) |
CN (1) | CN100454574C (zh) |
TW (1) | TW200511319A (zh) |
WO (1) | WO2005001840A2 (zh) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6888192B2 (en) * | 2003-04-25 | 2005-05-03 | Atmel Corporation | Mirror image non-volatile memory cell transistor pairs with single poly layer |
US6998670B2 (en) * | 2003-04-25 | 2006-02-14 | Atmel Corporation | Twin EEPROM memory transistors with subsurface stepped floating gates |
US20070247915A1 (en) * | 2006-04-21 | 2007-10-25 | Intersil Americas Inc. | Multiple time programmable (MTP) PMOS floating gate-based non-volatile memory device for a general-purpose CMOS technology with thick gate oxide |
US7903465B2 (en) * | 2007-04-24 | 2011-03-08 | Intersil Americas Inc. | Memory array of floating gate-based non-volatile memory cells |
US7688627B2 (en) * | 2007-04-24 | 2010-03-30 | Intersil Americas Inc. | Flash memory array of floating gate-based non-volatile memory cells |
US7773423B1 (en) * | 2007-09-27 | 2010-08-10 | National Semiconductor Corporation | Low power, CMOS compatible non-volatile memory cell and related method and memory array |
KR101087830B1 (ko) * | 2009-01-05 | 2011-11-30 | 주식회사 하이닉스반도체 | 반도체 소자의 레이아웃 |
CN107293582B (zh) * | 2017-07-10 | 2020-04-24 | 东南大学 | 面向物联网的硅基具有热电转换功能的bjt器件 |
KR102472339B1 (ko) * | 2017-08-07 | 2022-12-01 | 에스케이하이닉스 주식회사 | 3차원 구조의 반도체 메모리 장치 |
Family Cites Families (30)
Publication number | Priority date | Publication date | Assignee | Title |
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US4814594A (en) * | 1982-11-22 | 1989-03-21 | Drexler Technology Corporation | Updatable micrographic pocket data card |
IT1191566B (it) * | 1986-06-27 | 1988-03-23 | Sgs Microelettronica Spa | Dispositivo di memoria non labile a semiconduttore del tipo a porta non connessa (floating gate) alterabile elettricamente con area di tunnel ridotta e procedimento di fabbricazione |
US5108939A (en) * | 1990-10-16 | 1992-04-28 | National Semiconductor Corp. | Method of making a non-volatile memory cell utilizing polycrystalline silicon spacer tunnel region |
JP2541087B2 (ja) * | 1992-10-30 | 1996-10-09 | 日本電気株式会社 | 不揮発性半導体記憶装置のデ―タ消去方法 |
JP2725564B2 (ja) * | 1993-09-27 | 1998-03-11 | 日本電気株式会社 | 半導体記憶装置及びそのデータ書込み方法 |
US5808338A (en) * | 1994-11-11 | 1998-09-15 | Nkk Corporation | Nonvolatile semiconductor memory |
DE69521203T2 (de) * | 1995-07-31 | 2006-01-12 | Stmicroelectronics S.R.L., Agrate Brianza | Flash-EEPROM mit gesteuerter Entladungszeit der Wortleitungs- und Sourcespannungen nach der Löschung |
US6674470B1 (en) * | 1996-09-19 | 2004-01-06 | Kabushiki Kaisha Toshiba | MOS-type solid state imaging device with high sensitivity |
US5761126A (en) | 1997-02-07 | 1998-06-02 | National Semiconductor Corporation | Single-poly EPROM cell that utilizes a reduced programming voltage to program the cell |
JP3183396B2 (ja) | 1997-11-20 | 2001-07-09 | 日本電気株式会社 | 不揮発性半導体記憶装置およびその製造方法 |
US6385689B1 (en) * | 1998-02-06 | 2002-05-07 | Analog Devices, Inc. | Memory and a data processor including a memory |
JP3474758B2 (ja) * | 1998-02-16 | 2003-12-08 | 株式会社東芝 | 不揮発性半導体記憶装置 |
US6243289B1 (en) | 1998-04-08 | 2001-06-05 | Micron Technology Inc. | Dual floating gate programmable read only memory cell structure and method for its fabrication and operation |
US6043530A (en) | 1998-04-15 | 2000-03-28 | Chang; Ming-Bing | Flash EEPROM device employing polysilicon sidewall spacer as an erase gate |
US6180461B1 (en) * | 1998-08-03 | 2001-01-30 | Halo Lsi Design & Device Technology, Inc. | Double sidewall short channel split gate flash memory |
US6160287A (en) * | 1998-12-08 | 2000-12-12 | United Microelectronics Corp. | Flash memory |
EP1703520B1 (en) * | 1999-02-01 | 2011-07-27 | Renesas Electronics Corporation | Semiconductor integrated circuit and nonvolatile memory element |
US6597047B2 (en) * | 2000-03-22 | 2003-07-22 | Matsushita Electric Industrial Co., Ltd. | Method for fabricating a nonvolatile semiconductor device |
JP3699886B2 (ja) * | 2000-07-14 | 2005-09-28 | 沖電気工業株式会社 | 半導体記憶回路 |
US6465306B1 (en) | 2000-11-28 | 2002-10-15 | Advanced Micro Devices, Inc. | Simultaneous formation of charge storage and bitline to wordline isolation |
US6479351B1 (en) | 2000-11-30 | 2002-11-12 | Atmel Corporation | Method of fabricating a self-aligned non-volatile memory cell |
US6468863B2 (en) * | 2001-01-16 | 2002-10-22 | Taiwan Semiconductor Manufacturing Co., Ltd | Split gate field effect transistor (FET) device employing dielectric barrier layer and method for fabrication thereof |
US6563733B2 (en) * | 2001-05-24 | 2003-05-13 | Winbond Electronics Corporation | Memory array architectures based on a triple-polysilicon source-side injection non-volatile memory cell |
TW513759B (en) * | 2001-12-28 | 2002-12-11 | Nanya Technology Corp | Manufacturing method of floating gate and control gate of flash memory |
TWI267980B (en) * | 2002-04-16 | 2006-12-01 | Macronix Int Co Ltd | Method for fabricating non-volatile memory having P-type floating gate |
US6831325B2 (en) * | 2002-12-20 | 2004-12-14 | Atmel Corporation | Multi-level memory cell with lateral floating spacers |
US6998670B2 (en) * | 2003-04-25 | 2006-02-14 | Atmel Corporation | Twin EEPROM memory transistors with subsurface stepped floating gates |
US6888192B2 (en) * | 2003-04-25 | 2005-05-03 | Atmel Corporation | Mirror image non-volatile memory cell transistor pairs with single poly layer |
US6919242B2 (en) * | 2003-04-25 | 2005-07-19 | Atmel Corporation | Mirror image memory cell transistor pairs featuring poly floating spacers |
US7098106B2 (en) * | 2004-07-01 | 2006-08-29 | Atmel Corporation | Method of making mirror image memory cell transistor pairs featuring poly floating spacers |
-
2003
- 2003-06-18 US US10/465,718 patent/US6888192B2/en not_active Expired - Fee Related
-
2004
- 2004-05-18 CN CNB2004800234634A patent/CN100454574C/zh not_active Expired - Fee Related
- 2004-05-18 EP EP04752639A patent/EP1636849A2/en not_active Withdrawn
- 2004-05-18 WO PCT/US2004/015651 patent/WO2005001840A2/en active Search and Examination
- 2004-06-14 TW TW093117034A patent/TW200511319A/zh unknown
-
2005
- 2005-03-21 US US11/085,387 patent/US20050164452A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
CN1836336A (zh) | 2006-09-20 |
US20040212004A1 (en) | 2004-10-28 |
WO2005001840A3 (en) | 2005-11-24 |
EP1636849A2 (en) | 2006-03-22 |
US6888192B2 (en) | 2005-05-03 |
CN100454574C (zh) | 2009-01-21 |
US20050164452A1 (en) | 2005-07-28 |
WO2005001840A2 (en) | 2005-01-06 |
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