US20050164452A1 - Mirror image non-volatile memory cell transistor pairs with single poly layer - Google Patents
Mirror image non-volatile memory cell transistor pairs with single poly layer Download PDFInfo
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- US20050164452A1 US20050164452A1 US11/085,387 US8538705A US2005164452A1 US 20050164452 A1 US20050164452 A1 US 20050164452A1 US 8538705 A US8538705 A US 8538705A US 2005164452 A1 US2005164452 A1 US 2005164452A1
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7887—Programmable transistors with more than two possible different levels of programmation
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
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- H—ELECTRICITY
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
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- H—ELECTRICITY
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/60—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the control gate being a doped region, e.g. single-poly memory cell
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
- G11C16/0416—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
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- G—PHYSICS
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- G11C—STATIC STORES
- G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
- G11C2216/02—Structural aspects of erasable programmable read-only memories
- G11C2216/10—Floating gate memory cells with a single polysilicon layer
Definitions
- the invention relates to non-volatile memory transistors and, in particular, to a compact arrangement of such memory cells for an array and a method of making them.
- the multibit charge storage structures of the prior art attempt to achieve good data density in a memory array without giving up valuable chip space.
- One of the problems that is encountered in the prior art is an amount of crosstalk between storage sites. Because the charge storage structures are so small, one charge storage location can sometimes influence another. On the other hand, separation of charge storage sites gives up chip space. The ultimate separation is one dedicated transistor for each data bit. Accordingly, an object of the invention was to provide ultimate separation for data bits afforded by dedicated transistors yet achieve the compactness of multibit charge storage structures for a non-volatile memory array.
- MOS non-volatile memory transistor construction wherein a pair of transistors shares a common well in a semiconductor substrate for subsurface electrode formation in a memory array, whereby two compact transistors can be formed in place of one in most prior art arrays.
- This is achieved by construction of pairs of floating polysilicon gate transistors facing each other, with underlying channels and laterally adjacent subsurface sources and drains for each floating gate transistor.
- the floating gates extend back to form a capacitive relation with a word line and forward to form a band-to-band tunneling relation with the subsurface electrodes.
- a non-volatile memory array described in top projection by orthogonal stripes has parallel pairs of stripes in one direction, being word lines, and pairs of stripes in the orthogonal direction, being bit lines, the intersection resembling a tic-tac-toe pattern.
- the pair of MOS memory transistors is formed using only a single layer of poly for floating gate formation, with each floating gate extending from a respective word line to which it is electrically coupled.
- Sources and drains are symmetrically formed on opposite lateral sides of the forward portion of the poly but within the semiconductor substrate. The sources and drains are in contact with two parallel bit lines.
- the bit lines may be phased to provide a high electrode and a low electrode, with the transistor channel therebetween, and then reversed in polarity.
- the voltage between source and drain in the write mode is low, yet sufficient to generate hot electrons that are driven to the floating gate. While the sources and drains are laterally symmetric, the pair of memory transistors are symmetric about an imaginary line running across the center of the pattern, parallel to the word lines.
- the array is suitable for use as a flash memory.
- FIG. 1 is a circuit diagram of a memory array of the present invention.
- FIG. 2 is a top projection of non-volatile memory cells in the memory array of FIG. 1 schematically illustrating layout of memory transistors in the array.
- FIG. 3 is a top projection of a pair of facing memory transistors illustrating construction of two adjacent symmetric memory cells in the memory array of FIG. 2 .
- FIGS. 4-11 are side sectional views taken along lines A-A in FIG. 3 illustrating progressive construction steps for making two adjacent symmetric memory cells.
- FIG. 12 is a side sectional view taken along lines B-B in FIG. 3 illustrating construction steps for making two adjacent symmetric memory cells.
- FIG. 13 is a side sectional view taken along lines C—C in FIG. 3 illustrating construction of a single memory transistor having a single poly layer.
- a MOS memory array featuring a plurality of memory transistors 11 , 13 , 15 , 21 , 23 , 25 , 31 , 33 , 35 , and so on.
- Memory transistors 11 , 13 and 15 are aligned in a first column 102 .
- Memory transistors 21 , 23 and 25 are aligned in a second column 104 .
- Memory transistors 31 , 33 , and 35 are aligned in a third column 106 .
- Memory transistors 11 , 21 , and 31 are aligned in a first row.
- Memory transistors 13 , 23 and 33 are aligned in a second row.
- Memory transistors 15 , 25 and 35 are aligned in a third row, and so on.
- Each memory transistor such as memory transistor 11 , includes a capacitor 12 associated with a floating gate transistor 14 .
- Each floating gate transistor in a column is connected between two bit lines, including a first bit line 10 and a second bit line 20 in the column with memory transistors 11 , 13 and 15 .
- two bit lines 16 and 18 are associated with the next column having memory transistors 21 , 23 and 25 with bit line 16 on the left side of the memory transistors and bit line 18 on the right side.
- two memory transistors 11 and 13 are symmetrically built together, as explained below, in a transistor region indicated by dashed line 100 .
- the two devices 11 and 13 are independent, but in construction the two devices are constructed almost like a single device, as described below.
- a first word line 22 is associated with a first row of memory transistors 11 , 21 , 31 , and so on.
- a second word line 24 is associated with a second row of memory transistors 13 , 23 and 33 .
- Each word line, such as the zero order word line 22 is connected to a capacitor 12 associated with memory transistor 14 .
- Capacitor 12 is illustrated like a transistor because it is fabricated like a transistor, but with the substrate bulk or body connected to source and drain electrodes, using processes to define a capacitor plate 26 which, with an extension, explained below, forms gate 28 of transistor 14 .
- Gate 28 is a floating gate, i.e. a charge storage structure where charge, or lack of charge, is indicative of the state of the transistor.
- a sense amplifier associated with each word line, not shown, is used to read the state of the floating gate.
- Each charge storage transistor can be addressed individually using row and column decoders, not shown, connected to sense transistors.
- Source 32 of transistor 14 is connected to the zero order bit line with phase one, 10
- drain 34 is connected to the zero order bit line with phase two, 20 . Phasing of the bit lines in optional. Other voltage application schemes are known in the art.
- FIGS. 2 and 3 active regions of devices are shown, with FIG. 2 showing an array and FIG. 3 showing the top projection within dashed line 100 of FIG. 2 and of FIG. 1 . Regions outside of the active regions are separated by isolation techniques, such as shallow trench isolation (STI), LOCOS oxidation, or similar techniques.
- isolation techniques such as shallow trench isolation (STI), LOCOS oxidation, or similar techniques.
- a first n+ implant into the substrate establishes all of the word lines as parallel stripes, shaded by forward diagonal lines, including first word line 22 WL ⁇ ( ⁇ 1 ) and second word line 24 WL ⁇ ( ⁇ 2 ).
- the word lines are co-extensive with the width of the array.
- an n-well implant is made, defining a region 30 , shaded by regular stippling, where two symmetric memory transistors will be built.
- This implant has an almost square shape with a length approximately twice the length of each of the two memory transistors that are mirror-image symmetric relative to an imaginary line M, shown as a wavy line, joining contacts 36 and 38 .
- the approximate size of this square is 2 ⁇ 2 microns on a side, depending upon equipment and process technology used.
- the contact regions 36 and 38 in the middle of the bit lines shown in the construction region defined by dashed line 100 , are places where metal plugs will contact the surface of the substrate so that electrical communication is had with implanted subsurface source and drain regions 32 and 34 shaded as solid horizontal lines. These are perpendicular to the word lines 22 and 24 , making contact with bit lines 10 and 20 , having a length co-extensive with columns of the memory array.
- each of the bit lines 10 and 20 has associated implanted source and drain regions, forming source and drain electrodes 32 and 34 , respectively, for transistor 14 , with similar implanted electrodes for its mirror-image partner, transistor 30 .
- source and drain electrodes 32 and 34 respectively, for transistor 14
- similar implanted electrodes for its mirror-image partner, transistor 30 transistor 30 .
- Each memory cell has a T-shaped deposit of polysilicon over the oxide covering the substrate, most clearly seen in FIG. 2 .
- the T-shape is shaded with short parallel segments, with each poly deposit having a T-base 42 in both FIGS. 2 and 3 , and a T-top 40 superposed over the word line.
- the T-top 40 is a stripe deposit parallel to the word line 22 and is generally superposed over the word line 22 orthogonal to bit lines 10 and 20 .
- a single poly T-shape layer 81 is seen to have a T-top 83 and a T-base 85 .
- the T-base 42 has an underlying oxide layer spacing the T-base 42 from the substrate, with source 32 and drain 34 on opposite lateral sides of the T-base.
- the T-top acts in capacitive relation with the underlying word line, conducting during forward bias conditions.
- Two symmetric memory transistors are built in N-well region 30 , namely transistors 11 and 13 seen in FIG. 1 , with the two transistors mirrored across an imaginary line M in FIG. 3 which is parallel to two adjacent word lines and midway therebetween.
- the two transistors have sources 32 and drains 34 which are implanted into the N-well after the T-base is constructed, so that sources and drains are self-aligned with the poly T-base.
- the two transistors are symmetric about an imaginary line M passing through the midpoint between the two facing T-bases in the direction of a line drawn through contact regions 36 , 38 . Perfect geometric symmetry is not essential nor attainable, but preferred as a design objective because it facilitates mask design and fabrication processes.
- substrate 10 is seen having shallow trench isolation (STI) regions 51 - 55 for two facing memory cells, including the transistors proximate to T-base 42 and T-base 44 in FIG. 3 , with supporting word and bit lines.
- STI regions are boundaries or walls that define active areas as regions between STI boundaries and are formed after the initial doping of the substrate.
- the remaining figures show a sequence of important steps in formation of the devices. Steps of lesser importance, or steps well-known to those skilled in the art are not shown.
- N-well photomask portions 56 and 57 are placed over left and right zones of the two facing memory cells, leaving open a central zone between the marks so that an ion beam, I, can deliver negative ions implanted in regions 58 and 59 .
- the implant has been driven into the substrate such that the depth of N-well 61 extends at least to the depth of trench 53 and extends between trenches 52 and 54 .
- the N-well can be shared by two symmetric memory transistors, with one to be built on each side of isolation region 53 .
- photomask portions 56 and 57 have been removed.
- a photomask 63 is applied over the N-well and ion beams J and K deliver a concentration of negative ions into regions 65 and 67 for establishing word lines 24 and 22 in FIG. 3 .
- the implanted regions are driven in so that word lines 24 and 22 are seen in the p-substrate 10 .
- the word lines are linear, running across the width of the memory array, as seen in FIG. 2 .
- Active regions of the substrate are covered with gate oxide 69 to a thickness of 50-80 Angstroms, as seen in FIG. 9 .
- the gate oxide layer 69 will insulate the n-well 67 and its contents from a polysilicon layer 71 , seen in FIG.
- the poly layer 71 behaves as one plate of a capacitor, as previously mentioned.
- the second plate of the capacitor is the associated word line. This is a T-top region of the poly.
- the poly region furthest from the word line is the T-base region, forming the floating gate of a transistor with nearby source and drain in the substrate.
- the poly layer 71 is masked, as seen in FIG. 11 where mask regions 73 and 75 protect the polysilicon except over the central isolation region 53 and also where transistors are separated, as in region 70 .
- Polysilicon is etched above the central isolation region so that two separate symmetric memory transistors can be formed sharing the same N-well.
- FIG. 12 Switching to the sectional view of FIG. 12 (along lines B-B of FIG. 3 ) it is seen that the single polysilicon layer 71 is etched back to the region of isolation trenches 52 and 54 . Also seen for the first time is a p+ doping region 77 in the N-well forming source and drain electrodes of a memory transistor which is connected to bit line 10 in FIG. 3 . A deposition of inter-layer dielectric material 79 (ILD) is placed over poly 71 with a central opening 81 . This opening will be used for a metal plug to make contact with the bit line. The metal filler is shown as contact 36 in FIG. 3 .
- ILD inter-layer dielectric material
- the polysilicon region 71 a floating gate
- the floating gate is spaced between two p+ diffusions or implants 83 and 85 in the N-well 61 .
- the T-base region is spaced from the substrate by gate oxide and is, therefore, electrically floating.
- the source and drain regions 83 and 85 extend laterally away from the T-base region toward the bit lines 10 and 20 seen in FIG. 3 .
- the bit lines bias control conduction in the channel by setting the threshold voltage. Voltages on the source and drain can bias junctions to induce band-to-band tunneling relative to the floating gate. Charge accumulations trapped on the floating gate indicate a memory state.
- the bit line is used to sense the state of charge of the floating gate.
- Band-to-band tunneling occurs partly because of the small dimensions of the cell and appropriate concentration of dopants in regions 83 , 85 and 61 .
- the channel length is approximately 0.25-0.35 microns, while the distance between STI regions 54 are defined by minimum design rules of whatever processing technology is used. In this tight environment, holes in the source or drain become sufficiently energetic to cause electrons to be pulled from the floating gate. Alternatively, hot electrons can be placed on the floating gate with an opposite bias.
- relatively low voltages may be used to program the memory transistors, such as 2.5V.
- High voltages such as 5V may be used in the interior of the chip. Note that the left and right bit lines are not held at the same voltage for program and erase, but are phase alternates relative to ground. Phase alternating allows the two mirror-image transistors to share the same source and drain.
- Examples of voltages are as follows: BLOCK PROGRAM READ (ROW) ERASE BL0 (L) +5 V +2.5 V ⁇ 5 V BL0 (R) Floating 0 V ⁇ 5 V WL0 +5 V 0 V +2.5 V to +5 V N-WELL +5 V +3 V to +5 V 0 V P-SUBS 0 V 0 V 0 V BL1 (L) +5 V ⁇ 5 V BL1 (R) Floating ⁇ 5 V WL1 0 V +2.5 V to +5 V N-WELL +5 V 0 V P-SUBS 0 V 0 V BLN (L) 0 V +2.5 V ⁇ 5 V BLN (R) 0 V 0 V ⁇ 5 V WLN 0 V +2.5 V to +5 V N-WELL 0 V +3 V to +5 V 0 V P-SUBS 0 V +3 V 0 V 0 V
- block erase and erase are the same except that in block erase, the N-well and the p-substrate are held at ground.
- the block erase mode enables the array to operate similar to a flash EEPROM.
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Abstract
An arrangement of non-volatile memory transistors constructed in symmetric pairs within the space defined by intersecting pairs of word and bit lines of a memory array. The transistors have spaced apart sources and drains separated by a channel and having a floating gate over the channel characteristic of electrically erasable programmable read only memory transistors, except that there is no second poly gate. Only a single poly gate is used as a floating charge storage gate. This floating gate is placed sufficiently close to the source or drain of the device as to enable band-to-band tunneling. The floating gate is extended over the substrate to cross a word line where the floating gate is in a capacitive relation. The word line is used to program and erase the floating gate in combination with a source or drain electrode. A block erase mode is available so that the arrangement of transistors can operate as a flash memory. The single layer of poly has a T-shape, with the T-top used as the communication member with the word line and a T-base used as a floating gate. Both T-members are at the same potential. The intersecting pairs of word and bit lines resemble a tic-tac-toe pattern, with a central clear zone wherein pairs of symmetric non-volatile memory transistors are built.
Description
- This is a divisional of pending U.S. patent application Ser. No. 10/465,718 filed Jun. 18, 2003 which is a continuation-in-part of prior application Ser. No. 10/423,637 filed Apr. 25, 2003.
- The invention relates to non-volatile memory transistors and, in particular, to a compact arrangement of such memory cells for an array and a method of making them.
- In prior application Ser. No. 10/423,637 entitled “Mirror Image Memory Cell Transistor Pairs Featuring Poly Floating Spacers”, assigned to the assignee of the present invention, B. Lojek described an arrangement of non-volatile MOS memory transistors for a memory array wherein symmetric pairs of transistors were built in a memory array. Transistor pairs shared a drain electrode in a common well but were otherwise completely independent. The pair was manufactured between a pair of isolation regions and so shared the same substrate region, almost as if a single transistor were constructed there.
- In the prior art, single MOS floating gate transistors that stored two data bits have been devised as a way to achieve compactness. Since millions of data bits are frequently stored in non-volatile memory arrays, small savings of space are multiplied significantly over the array. In prior application Ser. No. 10/327,336 entitled “Multi-Level Memory Cell with Lateral Floating Spacers”, assigned to the assignee of the present invention, B. Lojek described how two spacers, on opposite sides of a conductive gate, behave as independent charge storage regions for separate binary data, thereby allowing a single non-volatile MOS transistor to store two binary bits. Each memory cell is connected to two bit lines and one word line. The bit lines are phased so that during a single clock cycle, first one bit line is active and then the other while a word line is active for the entire cycle. In this manner, both storage areas may be accessed for a read or write operation in a single clock cycle.
- In U.S. Pat. No. 6,043,530 to M. Chang, a MOS memory transistor construction is shown employing band-to-band tunneling. In U.S. Pat. No. 6,323,088 to F. Gonzalez et al., a multibit charge storage transistor addressing scheme is shown with phased bit lines.
- In summary, the multibit charge storage structures of the prior art attempt to achieve good data density in a memory array without giving up valuable chip space. One of the problems that is encountered in the prior art is an amount of crosstalk between storage sites. Because the charge storage structures are so small, one charge storage location can sometimes influence another. On the other hand, separation of charge storage sites gives up chip space. The ultimate separation is one dedicated transistor for each data bit. Accordingly, an object of the invention was to provide ultimate separation for data bits afforded by dedicated transistors yet achieve the compactness of multibit charge storage structures for a non-volatile memory array.
- The above object has been met with an MOS non-volatile memory transistor construction wherein a pair of transistors shares a common well in a semiconductor substrate for subsurface electrode formation in a memory array, whereby two compact transistors can be formed in place of one in most prior art arrays. This is achieved by construction of pairs of floating polysilicon gate transistors facing each other, with underlying channels and laterally adjacent subsurface sources and drains for each floating gate transistor. The floating gates extend back to form a capacitive relation with a word line and forward to form a band-to-band tunneling relation with the subsurface electrodes.
- A non-volatile memory array described in top projection by orthogonal stripes has parallel pairs of stripes in one direction, being word lines, and pairs of stripes in the orthogonal direction, being bit lines, the intersection resembling a tic-tac-toe pattern. In the center of this pattern, the pair of MOS memory transistors is formed using only a single layer of poly for floating gate formation, with each floating gate extending from a respective word line to which it is electrically coupled. Sources and drains are symmetrically formed on opposite lateral sides of the forward portion of the poly but within the semiconductor substrate. The sources and drains are in contact with two parallel bit lines. The bit lines may be phased to provide a high electrode and a low electrode, with the transistor channel therebetween, and then reversed in polarity. The voltage between source and drain in the write mode is low, yet sufficient to generate hot electrons that are driven to the floating gate. While the sources and drains are laterally symmetric, the pair of memory transistors are symmetric about an imaginary line running across the center of the pattern, parallel to the word lines. The array is suitable for use as a flash memory.
-
FIG. 1 is a circuit diagram of a memory array of the present invention. -
FIG. 2 is a top projection of non-volatile memory cells in the memory array ofFIG. 1 schematically illustrating layout of memory transistors in the array. -
FIG. 3 is a top projection of a pair of facing memory transistors illustrating construction of two adjacent symmetric memory cells in the memory array ofFIG. 2 . -
FIGS. 4-11 are side sectional views taken along lines A-A inFIG. 3 illustrating progressive construction steps for making two adjacent symmetric memory cells. -
FIG. 12 is a side sectional view taken along lines B-B inFIG. 3 illustrating construction steps for making two adjacent symmetric memory cells. -
FIG. 13 is a side sectional view taken along lines C—C inFIG. 3 illustrating construction of a single memory transistor having a single poly layer. - With reference to
FIG. 1 , a MOS memory array is shown featuring a plurality ofmemory transistors Memory transistors first column 102.Memory transistors second column 104.Memory transistors third column 106.Memory transistors Memory transistors Memory transistors memory transistor 11, includes acapacitor 12 associated with afloating gate transistor 14. Each floating gate transistor in a column is connected between two bit lines, including afirst bit line 10 and asecond bit line 20 in the column withmemory transistors bit lines memory transistors bit line 16 on the left side of the memory transistors andbit line 18 on the right side. - In construction, two
memory transistors line 100. In the memory array, the twodevices - A
first word line 22 is associated with a first row ofmemory transistors second word line 24 is associated with a second row ofmemory transistors order word line 22, is connected to acapacitor 12 associated withmemory transistor 14.Capacitor 12 is illustrated like a transistor because it is fabricated like a transistor, but with the substrate bulk or body connected to source and drain electrodes, using processes to define a capacitor plate 26 which, with an extension, explained below, formsgate 28 oftransistor 14.Gate 28 is a floating gate, i.e. a charge storage structure where charge, or lack of charge, is indicative of the state of the transistor. A sense amplifier, associated with each word line, not shown, is used to read the state of the floating gate. Each charge storage transistor can be addressed individually using row and column decoders, not shown, connected to sense transistors.Source 32 oftransistor 14 is connected to the zero order bit line with phase one, 10, whiledrain 34 is connected to the zero order bit line with phase two, 20. Phasing of the bit lines in optional. Other voltage application schemes are known in the art. - In
FIGS. 2 and 3 , active regions of devices are shown, withFIG. 2 showing an array andFIG. 3 showing the top projection within dashedline 100 ofFIG. 2 and ofFIG. 1 . Regions outside of the active regions are separated by isolation techniques, such as shallow trench isolation (STI), LOCOS oxidation, or similar techniques. - In a wafer p-substrate a first n+ implant into the substrate establishes all of the word lines as parallel stripes, shaded by forward diagonal lines, including
first word line 22 WLØ (φ1) andsecond word line 24 WLØ (φ2). The word lines are co-extensive with the width of the array. Between lines L1 and L2 an n-well implant is made, defining aregion 30, shaded by regular stippling, where two symmetric memory transistors will be built. This implant has an almost square shape with a length approximately twice the length of each of the two memory transistors that are mirror-image symmetric relative to an imaginary line M, shown as a wavy line, joiningcontacts contact regions line 100, are places where metal plugs will contact the surface of the substrate so that electrical communication is had with implanted subsurface source and drainregions bit lines electrodes transistor 14, with similar implanted electrodes for its mirror-image partner,transistor 30. Thus far, no structures are over the substrate, except that a layer of oxide is grown over the substrate. - Each memory cell has a T-shaped deposit of polysilicon over the oxide covering the substrate, most clearly seen in
FIG. 2 . InFIG. 3 , the T-shape is shaded with short parallel segments, with each poly deposit having a T-base 42 in bothFIGS. 2 and 3 , and a T-top 40 superposed over the word line. The T-top 40 is a stripe deposit parallel to theword line 22 and is generally superposed over theword line 22 orthogonal tobit lines FIG. 2 , at the right side of the drawing, a single poly T-shape layer 81 is seen to have a T-top 83 and a T-base 85. As previously mentioned, the T-base 42 has an underlying oxide layer spacing the T-base 42 from the substrate, withsource 32 and drain 34 on opposite lateral sides of the T-base. The T-top acts in capacitive relation with the underlying word line, conducting during forward bias conditions. - Two symmetric memory transistors are built in N-
well region 30, namelytransistors FIG. 1 , with the two transistors mirrored across an imaginary line M inFIG. 3 which is parallel to two adjacent word lines and midway therebetween. Returning toFIG. 1 , the two transistors havesources 32 and drains 34 which are implanted into the N-well after the T-base is constructed, so that sources and drains are self-aligned with the poly T-base. The two transistors are symmetric about an imaginary line M passing through the midpoint between the two facing T-bases in the direction of a line drawn throughcontact regions - With reference to
FIG. 4 ,substrate 10 is seen having shallow trench isolation (STI) regions 51-55 for two facing memory cells, including the transistors proximate to T-base 42 and T-base 44 inFIG. 3 , with supporting word and bit lines. These STI regions are boundaries or walls that define active areas as regions between STI boundaries and are formed after the initial doping of the substrate. The remaining figures show a sequence of important steps in formation of the devices. Steps of lesser importance, or steps well-known to those skilled in the art are not shown. - In
FIG. 5 , N-well photomask portions regions FIG. 6 , the implant has been driven into the substrate such that the depth of N-well 61 extends at least to the depth oftrench 53 and extends betweentrenches isolation region 53. At the sametime photomask portions - In
FIG. 7 , aphotomask 63 is applied over the N-well and ion beams J and K deliver a concentration of negative ions intoregions word lines FIG. 3 . InFIG. 8 , the implanted regions are driven in so that word lines 24 and 22 are seen in the p-substrate 10. The word lines are linear, running across the width of the memory array, as seen inFIG. 2 . Active regions of the substrate are covered withgate oxide 69 to a thickness of 50-80 Angstroms, as seen inFIG. 9 . Thegate oxide layer 69 will insulate the n-well 67 and its contents from apolysilicon layer 71, seen inFIG. 10 , having a thickness of 1500-2000 Angstroms. Thepoly layer 71 behaves as one plate of a capacitor, as previously mentioned. The second plate of the capacitor is the associated word line. This is a T-top region of the poly. The poly region furthest from the word line is the T-base region, forming the floating gate of a transistor with nearby source and drain in the substrate. Later, thepoly layer 71 is masked, as seen inFIG. 11 wheremask regions central isolation region 53 and also where transistors are separated, as inregion 70. Polysilicon is etched above the central isolation region so that two separate symmetric memory transistors can be formed sharing the same N-well. - Switching to the sectional view of
FIG. 12 (along lines B-B ofFIG. 3 ) it is seen that thesingle polysilicon layer 71 is etched back to the region ofisolation trenches p+ doping region 77 in the N-well forming source and drain electrodes of a memory transistor which is connected to bitline 10 inFIG. 3 . A deposition of inter-layer dielectric material 79 (ILD) is placed overpoly 71 with acentral opening 81. This opening will be used for a metal plug to make contact with the bit line. The metal filler is shown ascontact 36 inFIG. 3 . - In the transverse sectional view of
FIG. 13 thepolysilicon region 71, a floating gate, is the T-base 42 inFIG. 3 . The floating gate is spaced between two p+ diffusions orimplants well 61. Recall that the T-base region is spaced from the substrate by gate oxide and is, therefore, electrically floating. The source and drainregions FIG. 3 . Thus, the bit lines bias control conduction in the channel by setting the threshold voltage. Voltages on the source and drain can bias junctions to induce band-to-band tunneling relative to the floating gate. Charge accumulations trapped on the floating gate indicate a memory state. The bit line is used to sense the state of charge of the floating gate. Band-to-band tunneling occurs partly because of the small dimensions of the cell and appropriate concentration of dopants inregions STI regions 54 are defined by minimum design rules of whatever processing technology is used. In this tight environment, holes in the source or drain become sufficiently energetic to cause electrons to be pulled from the floating gate. Alternatively, hot electrons can be placed on the floating gate with an opposite bias. - In this application, the invention was described with reference to a p-substrate with an N-well. These polarities could have been reversed.
- In operation, relatively low voltages may be used to program the memory transistors, such as 2.5V. High voltages, such as 5V may be used in the interior of the chip. Note that the left and right bit lines are not held at the same voltage for program and erase, but are phase alternates relative to ground. Phase alternating allows the two mirror-image transistors to share the same source and drain. Examples of voltages are as follows:
BLOCK PROGRAM READ (ROW) ERASE BL0 (L) +5 V +2.5 V −5 V BL0 (R) Floating 0 V −5 V WL0 +5 V 0 V +2.5 V to +5 V N-WELL +5 V +3 V to +5 V 0 V P-SUBS 0 V 0 V 0 V BL1 (L) +5 V −5 V BL1 (R) Floating −5 V WL1 0 V +2.5 V to +5 V N-WELL +5 V 0 V P-SUBS 0 V 0 V BLN (L) 0 V +2.5 V −5 V BLN (R) 0 V 0 V −5 V WLN 0 V +2.5 V to +5 V N-WELL 0 V +3 V to +5 V 0 V P-SUBS 0 V +3 V 0 V - Note that the voltages for block erase and erase are the same except that in block erase, the N-well and the p-substrate are held at ground. The block erase mode enables the array to operate similar to a flash EEPROM.
Claims (9)
1. A method of making a memory storage device in a semiconductor substrate for a non-volatile memory array comprising,
establishing spaced apart parallel word lines running in a first direction within the substrate,
establishing spaced apart parallel bit lines running in a second direction within the substrate orthogonal to the first direction and intersecting the word lines, forming a tic-tac-toe pattern having a central zone,
forming a mirror-image MOS charge store transistor pair within the central zone, each transistor having a first electrode communicating with a bit line and a second electrode communicating with a word line.
2. This method of claim 1 further defined by forming said paid of mirror-image transistors across an imaginary line parallel to the word lines.
3. The method of claim 2 further defined wherein said imaginary line is midway between the word lines.
4. The method of claim 2 further defined by forming each transistor of said pair with the electrodes having a cross-section parallel to said imaginary line.
5. The method of claim 1 further defined by forming each transistor with only a single layer of poly.
6. The method of claim 5 further defined by spacing said layer of poly in a capacitive relation to the substrate.
7. The method of claim 6 further defined by spacing said layer of poly in a relation to said electrodes to induce band-to-band tunneling.
8. The method of claim 1 further defined by applying voltage to the bit lines in phases within a clock cycle.
9. The method of claim 1 further defined by making a memory array having rows and columns of mirror-image MOS storage transistor pairs within tic-tac-toe patterns formed by intersecting pairs of word and bit lines.
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US11/085,387 US20050164452A1 (en) | 2003-04-25 | 2005-03-21 | Mirror image non-volatile memory cell transistor pairs with single poly layer |
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US10/423,637 US6919242B2 (en) | 2003-04-25 | 2003-04-25 | Mirror image memory cell transistor pairs featuring poly floating spacers |
US10/465,718 US6888192B2 (en) | 2003-04-25 | 2003-06-18 | Mirror image non-volatile memory cell transistor pairs with single poly layer |
US11/085,387 US20050164452A1 (en) | 2003-04-25 | 2005-03-21 | Mirror image non-volatile memory cell transistor pairs with single poly layer |
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US10/465,718 Division US6888192B2 (en) | 2003-04-25 | 2003-06-18 | Mirror image non-volatile memory cell transistor pairs with single poly layer |
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US11/085,387 Abandoned US20050164452A1 (en) | 2003-04-25 | 2005-03-21 | Mirror image non-volatile memory cell transistor pairs with single poly layer |
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EP (1) | EP1636849A2 (en) |
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US20100171159A1 (en) * | 2009-01-05 | 2010-07-08 | Hynix Semiconductor Inc. | Layout of semiconductor device |
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US6888192B2 (en) * | 2003-04-25 | 2005-05-03 | Atmel Corporation | Mirror image non-volatile memory cell transistor pairs with single poly layer |
US6998670B2 (en) * | 2003-04-25 | 2006-02-14 | Atmel Corporation | Twin EEPROM memory transistors with subsurface stepped floating gates |
US20070247915A1 (en) * | 2006-04-21 | 2007-10-25 | Intersil Americas Inc. | Multiple time programmable (MTP) PMOS floating gate-based non-volatile memory device for a general-purpose CMOS technology with thick gate oxide |
US7903465B2 (en) * | 2007-04-24 | 2011-03-08 | Intersil Americas Inc. | Memory array of floating gate-based non-volatile memory cells |
US7688627B2 (en) * | 2007-04-24 | 2010-03-30 | Intersil Americas Inc. | Flash memory array of floating gate-based non-volatile memory cells |
US7773423B1 (en) * | 2007-09-27 | 2010-08-10 | National Semiconductor Corporation | Low power, CMOS compatible non-volatile memory cell and related method and memory array |
CN107293582B (en) * | 2017-07-10 | 2020-04-24 | 东南大学 | Silicon-based BJT device with thermoelectric conversion function and oriented to Internet of things |
KR102472339B1 (en) * | 2017-08-07 | 2022-12-01 | 에스케이하이닉스 주식회사 | Three dimensional semiconductor memory device |
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Also Published As
Publication number | Publication date |
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WO2005001840A2 (en) | 2005-01-06 |
EP1636849A2 (en) | 2006-03-22 |
WO2005001840A3 (en) | 2005-11-24 |
TW200511319A (en) | 2005-03-16 |
CN100454574C (en) | 2009-01-21 |
US6888192B2 (en) | 2005-05-03 |
US20040212004A1 (en) | 2004-10-28 |
CN1836336A (en) | 2006-09-20 |
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