TW200509126A - Coupled body contacts for SOI differential circuits - Google Patents

Coupled body contacts for SOI differential circuits

Info

Publication number
TW200509126A
TW200509126A TW093112942A TW93112942A TW200509126A TW 200509126 A TW200509126 A TW 200509126A TW 093112942 A TW093112942 A TW 093112942A TW 93112942 A TW93112942 A TW 93112942A TW 200509126 A TW200509126 A TW 200509126A
Authority
TW
Taiwan
Prior art keywords
soi
body contacts
fets
differential circuits
coupled body
Prior art date
Application number
TW093112942A
Other languages
English (en)
Other versions
TWI306601B (en
Inventor
Yuen H Chan
Rajiv V Joshi
Antonio R Pelella
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of TW200509126A publication Critical patent/TW200509126A/zh
Application granted granted Critical
Publication of TWI306601B publication Critical patent/TWI306601B/zh

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Memories (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
TW093112942A 2003-05-12 2004-05-07 Integrated circuit chip and sram for soi TWI306601B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/436,432 US6868000B2 (en) 2003-05-12 2003-05-12 Coupled body contacts for SOI differential circuits

Publications (2)

Publication Number Publication Date
TW200509126A true TW200509126A (en) 2005-03-01
TWI306601B TWI306601B (en) 2009-02-21

Family

ID=33417166

Family Applications (1)

Application Number Title Priority Date Filing Date
TW093112942A TWI306601B (en) 2003-05-12 2004-05-07 Integrated circuit chip and sram for soi

Country Status (2)

Country Link
US (1) US6868000B2 (zh)
TW (1) TWI306601B (zh)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7295457B2 (en) * 2002-11-29 2007-11-13 International Business Machines Corporation Integrated circuit chip with improved array stability
US7173875B2 (en) * 2002-11-29 2007-02-06 International Business Machines Corporation SRAM array with improved cell stability
US7035159B2 (en) * 2004-04-01 2006-04-25 Micron Technology, Inc. Techniques for storing accurate operating current values
US7404071B2 (en) * 2004-04-01 2008-07-22 Micron Technology, Inc. Memory modules having accurate operating current values stored thereon and methods for fabricating and implementing such devices
JP4110115B2 (ja) * 2004-04-15 2008-07-02 株式会社東芝 半導体記憶装置
US8098536B2 (en) * 2008-01-24 2012-01-17 International Business Machines Corporation Self-repair integrated circuit and repair method
US8420460B2 (en) 2008-03-26 2013-04-16 International Business Machines Corporation Method, structure and design structure for customizing history effects of SOI circuits
US8410554B2 (en) 2008-03-26 2013-04-02 International Business Machines Corporation Method, structure and design structure for customizing history effects of SOI circuits
US7964467B2 (en) * 2008-03-26 2011-06-21 International Business Machines Corporation Method, structure and design structure for customizing history effects of soi circuits
DE102008045037B4 (de) * 2008-08-29 2010-12-30 Advanced Micro Devices, Inc., Sunnyvale Statischer RAM-Zellenaufbau und Mehrfachkontaktschema zum Anschluss von Doppelkanaltransistoren
US8345468B2 (en) * 2009-08-18 2013-01-01 Southeast University Capacity and density enhancement circuit for sub-threshold memory unit array

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5898617A (en) * 1997-05-21 1999-04-27 Motorola, Inc. Sensing circuit and method
US6061268A (en) * 1999-10-27 2000-05-09 Kuo; James B. 0.7V two-port 6T SRAM memory cell structure with single-bit-line simultaneous read-and-write access (SBLSRWA) capability using partially-depleted SOI CMOS dynamic-threshold technique
US6724681B2 (en) * 2000-02-02 2004-04-20 Broadcom Corporation Asynchronously-resettable decoder with redundancy

Also Published As

Publication number Publication date
US20040228160A1 (en) 2004-11-18
US6868000B2 (en) 2005-03-15
TWI306601B (en) 2009-02-21

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees