TW200501276A - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device

Info

Publication number
TW200501276A
TW200501276A TW092136958A TW92136958A TW200501276A TW 200501276 A TW200501276 A TW 200501276A TW 092136958 A TW092136958 A TW 092136958A TW 92136958 A TW92136958 A TW 92136958A TW 200501276 A TW200501276 A TW 200501276A
Authority
TW
Taiwan
Prior art keywords
well region
ions
forming
semiconductor device
implanting
Prior art date
Application number
TW092136958A
Other languages
Chinese (zh)
Other versions
TWI254994B (en
Inventor
Noh-Yeal Kwak
Original Assignee
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Publication of TW200501276A publication Critical patent/TW200501276A/en
Application granted granted Critical
Publication of TWI254994B publication Critical patent/TWI254994B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H01L21/2652—Through-implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate

Abstract

The present invention is provided to manufacture a method of manufacturing a semiconductor device, comprising the steps of: forming a first well region by performing an ion implantation process for implanting first ions into a semiconductor substrate, and then forming a second well region in the first well region by performing an ion implantation process for implanting second ions having larger mass than the first ions; and forming a well region by performing an annealing process on the result structure. Therefore, it is possible to prevent TED phenomenon generated due to the high-energy heat treatment process to be performed later and to provide the increased activation ratio of ions compared to the conventional source/drain region in which only the ions having large mass are implanted by performing an annealing process after the first well region and the second well region are formed.
TW092136958A 2003-06-30 2003-12-26 Method of manufacturing semiconductor device TWI254994B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR10-2003-0043627A KR100524465B1 (en) 2003-06-30 2003-06-30 Method of manufacturing in semiconductor device

Publications (2)

Publication Number Publication Date
TW200501276A true TW200501276A (en) 2005-01-01
TWI254994B TWI254994B (en) 2006-05-11

Family

ID=33536400

Family Applications (1)

Application Number Title Priority Date Filing Date
TW092136958A TWI254994B (en) 2003-06-30 2003-12-26 Method of manufacturing semiconductor device

Country Status (4)

Country Link
US (1) US6927151B2 (en)
JP (1) JP4276057B2 (en)
KR (1) KR100524465B1 (en)
TW (1) TWI254994B (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7250313B2 (en) * 2004-09-30 2007-07-31 Solid State Measurements, Inc. Method of detecting un-annealed ion implants
WO2007058046A1 (en) * 2005-11-18 2007-05-24 Konica Minolta Holdings, Inc. Solid electrolyte and display element using the same
KR100850098B1 (en) * 2006-12-28 2008-08-04 동부일렉트로닉스 주식회사 Method for fabricating a semiconductor
CN115458604B (en) * 2022-10-24 2023-06-30 中芯越州集成电路制造(绍兴)有限公司 MOSFET device and manufacturing method thereof

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5714413A (en) * 1995-12-11 1998-02-03 Intel Corporation Method of making a transistor having a deposited dual-layer spacer structure
KR100220954B1 (en) * 1996-12-31 1999-09-15 김영환 Manufacturing method of semiconductor device having a triple well
US6198142B1 (en) * 1998-07-31 2001-03-06 Intel Corporation Transistor with minimal junction capacitance and method of fabrication
KR100294644B1 (en) * 1998-12-30 2001-11-02 박종섭 Triple Well Forming Method of Semiconductor Device_
US6297098B1 (en) * 1999-11-01 2001-10-02 Taiwan Semiconductor Manufacturing Company Tilt-angle ion implant to improve junction breakdown in flash memory application
KR100311217B1 (en) * 1999-12-22 2001-11-03 박종섭 Method for forming triple-well of semiconductor device using implantation of bf2 and multi-step annealing
KR20010087474A (en) * 1999-12-31 2001-09-21 황인길 Method for forming shallow junction of semiconductor device

Also Published As

Publication number Publication date
TWI254994B (en) 2006-05-11
JP4276057B2 (en) 2009-06-10
KR100524465B1 (en) 2005-10-26
KR20050002258A (en) 2005-01-07
US6927151B2 (en) 2005-08-09
US20040266149A1 (en) 2004-12-30
JP2005026652A (en) 2005-01-27

Similar Documents

Publication Publication Date Title
WO2007070321A3 (en) System and method for the manufacture of semiconductor devices by the implantation of carbon clusters
JP2011097093A5 (en)
TW200510179A (en) Formation of silicon-germanium-on-insulator (SGOI) by an integral high temperature SIMOX-Ge interdiffusion anneal
TW200634914A (en) Smart grading implant with diffusion retarding implant for making integrated circuit chips
WO2003096426A1 (en) Semiconductor substrate manufacturing method and semiconductor device manufacturing method, and semiconductor substrate and semiconductor device manufactured by the methods
SG142148A1 (en) Formation of silicided shallow junctions using implant through metal technology and laser annealing process
EP2092552A1 (en) Semiconductor device manufacturing method
TW200707590A (en) Shallow source/drain regions for CMOS transistors
US20080242066A1 (en) Method Of Manufacturing Semiconductor
TW200731361A (en) Semiconductor devices including impurity doped region and methods of forming the same
JP2007005575A5 (en)
CN102468163B (en) Method for manufacturing NMOS (N-channel metal oxide semiconductor) transistor
TW200641977A (en) Method for implanting ions to a wafer for manufacturing of semiconductor device and method of fabricating graded junction using the same
TW200715554A (en) Silicided regions for N metal oxide semiconductor and P metal oxide semiconductor devices and method for the same
TW200501276A (en) Method of manufacturing semiconductor device
EP1291905A3 (en) Method for fabricating semiconductor device
TW200603207A (en) Method for manufacturing semiconductor device (Ⅱ)
CN102446767B (en) Manufacturing method of NMOS (N-channel metal oxide semiconductor) transistor
US7060547B2 (en) Method for forming a junction region of a semiconductor device
JP2011049500A (en) Method of manufacturing semiconductor device
KR100624697B1 (en) Method for forming the dual poly gate of the recessed transistor
KR100728958B1 (en) Method of manufacturing semicondutor device
TW200512840A (en) Method for manufacturing semiconductor device
KR100521439B1 (en) Method for fabricating the p-channel MOS transistor
KR20100079139A (en) Method for manufacturing semiconductor device

Legal Events

Date Code Title Description
MK4A Expiration of patent term of an invention patent