KR100311217B1 - Method for forming triple-well of semiconductor device using implantation of bf2 and multi-step annealing - Google Patents
Method for forming triple-well of semiconductor device using implantation of bf2 and multi-step annealing Download PDFInfo
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- KR100311217B1 KR100311217B1 KR1019990060339A KR19990060339A KR100311217B1 KR 100311217 B1 KR100311217 B1 KR 100311217B1 KR 1019990060339 A KR1019990060339 A KR 1019990060339A KR 19990060339 A KR19990060339 A KR 19990060339A KR 100311217 B1 KR100311217 B1 KR 100311217B1
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- 238000000034 method Methods 0.000 title claims abstract description 36
- 238000000137 annealing Methods 0.000 title claims abstract description 33
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 238000002513 implantation Methods 0.000 title description 2
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 238000005468 ion implantation Methods 0.000 claims abstract description 24
- 229910052731 fluorine Inorganic materials 0.000 claims abstract description 23
- 239000011737 fluorine Substances 0.000 claims abstract description 23
- OKZIUSOJQLYFSE-UHFFFAOYSA-N difluoroboron Chemical compound F[B]F OKZIUSOJQLYFSE-UHFFFAOYSA-N 0.000 claims abstract description 12
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 9
- 239000012535 impurity Substances 0.000 claims abstract description 6
- 238000002955 isolation Methods 0.000 claims abstract description 6
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 claims abstract 5
- 238000010438 heat treatment Methods 0.000 claims description 9
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 5
- 229910052698 phosphorus Inorganic materials 0.000 claims description 5
- 239000011574 phosphorus Substances 0.000 claims description 5
- 239000012298 atmosphere Substances 0.000 claims description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims 1
- 229910001873 dinitrogen Inorganic materials 0.000 claims 1
- 238000007669 thermal treatment Methods 0.000 claims 1
- 239000002019 doping agent Substances 0.000 abstract description 12
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 18
- 229920002120 photoresistant polymer Polymers 0.000 description 11
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 6
- 229910052796 boron Inorganic materials 0.000 description 6
- 150000002500 ions Chemical class 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 230000006866 deterioration Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- -1 for example Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
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- H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub
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Abstract
본 발명은 이불화붕소(BF2)를 P-웰 형성용 도펀트로 사용하고, 그리고, 2단계에 걸친 어닐링으로 상기 P-웰 내에 존재하는 잔류 불소(F)를 제거하는 이불화붕소(BF2)의 이온주입과 다단계 어닐링을 이용한 반도체 소자의 삼중-웰 형성방법을 개시한다. 개시된 본 발명의 삼중-웰 형성방법은, 소자 영역을 한정하는 소자분리막들이 형성되고, 상기 소자 영역의 표면에는 스크린 산화막이 형성된 P형 기판을 제공하는 단계; 상기 P형 기판 상에 소자 영역을 노출시키는 제1이온주입 마스크를 형성하는 단계; 상기 노출된 P형 기판의 소자 영역 내에 N형 불순물을 이온주입한 후, 어닐링을 수행하여 N-웰을 형성하는 단계; 상기 제1이온주입 마스크를 제거하는 단계; 상기 N-웰이 형성된 상기 P형 기판 상에 상기 N-웰의 일부분을 노출시키는 제2이온주입 마스크를 형성하는 단계; 상기 노출된 N-웰 내에 이불화붕소(BF2)를 이온주입한 후, 어닐링을 수행하여 P-웰을 형성하는 단계; 상기 제2이온주입 마스크 및 상기 스크린 마스크를 제거하는 단계; 및 상기 P-웰 내에 존재하는 불소(F)가 제거되도록, 상기 결과물에 대한 1차 및 2차 어닐링을 연속적으로 수행하는 단계를 포함하여 이루어진다.The present invention uses boron difluoride (BF 2 ) as a dopant for forming P-well, and boron difluoride (BF 2 ) for removing residual fluorine (F) present in the P-well by annealing in two steps. Disclosed is a triple-well formation method of a semiconductor device using ion implantation and multistage annealing. The disclosed triple-well forming method includes providing a P-type substrate having device isolation films defining device regions and having a screen oxide formed on a surface of the device region; Forming a first ion implantation mask exposing a device region on the P-type substrate; Implanting an N-type impurity into the device region of the exposed P-type substrate, and then performing annealing to form an N-well; Removing the first ion implantation mask; Forming a second ion implantation mask exposing a portion of the N-well on the P-type substrate on which the N-well is formed; Ion implanting boron difluoride (BF 2 ) into the exposed N-well, followed by annealing to form a P-well; Removing the second ion implantation mask and the screen mask; And continuously performing primary and secondary annealing on the resultant to remove fluorine (F) present in the P-well.
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히, 이불화붕소의 이온주입과 다단계 어닐링을 이용한 반도체 소자의 삼중-웰 형성방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a triple-well formation method for a semiconductor device using ion implantation and multi-stage annealing of boron difluoride.
주지된 바와 같이, 셀 영역의 P-웰과 주변회로 영역의 P-웰을 전기적으로 절연시키기 위한 방법으로서, 삼중-웰 구조가 이용되고 있다. 상기 삼중-웰 구조는 N-웰 내에 P-웰을 형성시킴으로써, 상기 P-웰이 N-웰에 의해 감싸지도록 만든 구조를 일컫는다.As is well known, a triple-well structure is used as a method for electrically insulating the P-well in the cell region and the P-well in the peripheral circuit region. The triple-well structure refers to a structure in which the P-well is surrounded by the N-well by forming a P-well in the N-well.
종래 기술에 따른 삼중-웰의 형성방법을 설명하면 다음과 같다.Referring to the triple-well formation method according to the prior art as follows.
먼저, 소자분리막이 구비된 P형의 기판 상에 NMOS가 형성될 영역을 한정하는 제1감광막 패턴을 형성한다. 그런다음, 노출된 기판 부분에 N형 불순물, 예를들어, 인(P)을 이온주입한 후, 어닐링 공정을 수행하여 상기 P형 기판 내에 N-웰을 형성한다.First, a first photoresist layer pattern defining a region where an NMOS is to be formed is formed on a P-type substrate provided with an isolation layer. Then, an N-type impurity, for example, phosphorus (P) is ion implanted into the exposed substrate portion, followed by annealing to form an N-well in the P-type substrate.
이어서, 상기 제1감광막 패턴을 제거한 상태에서, 상기 N-웰이 형성된 기판 상에 상기 N-웰의 일부분만을 노출시키는 제2감광막 패턴을 재차 형성하고, 그런다음, 상기 제2감광막 패턴을 마스크로해서 노출된 N-웰 부분에 붕소(B)를 이온주입한 후, 연이어서, 어닐링 공정을 수행하여 상기 N-웰에 의해 감싸지는 형태로 상기 N-웰 내에 P-웰을 형성한다.Subsequently, in a state where the first photoresist pattern is removed, a second photoresist pattern is formed again on the substrate on which the N-well is formed to expose only a portion of the N-well, and then the second photoresist pattern is used as a mask. The boron (B) is ion-implanted in the exposed N-well portion, and subsequently, an annealing process is performed to form a P-well in the N-well in a form surrounded by the N-well.
그러나, 상기와 같은 종래 기술에 따른 삼중-웰 형성방법은 다음과 같은 문제점이 있다.However, the triple-well formation method according to the prior art as described above has the following problems.
전술한 바와 같이, P-웰은 N-웰 내에 P형 불순물, 예를들어, 붕소(B)를 이온주입하고, 그런다음, 어닐링을 수행하는 것에 의해 형성되며, 이후, 상기 P-웰은 후속 공정에서 여러번의 열 공정을 겪게 된다.As described above, the P-well is formed by ion implanting P-type impurities, such as boron (B) into the N-well, and then performing annealing, after which the P-well is subsequently The process undergoes several thermal processes.
그런데, 이 과정에서 P-웰의 도펀트인 붕소(B)와 상기 P-웰의 하부에 형성된 N-웰의 도펀트인 인(P) 사이에서 도펀트들간의 상쇄 효과(Compensation)가 일어나기 때문에, P-웰에서의 붕소(B) 농도의 감소 현상과 N-웰에서의 인(P) 농도의 감소 현상이 발생되어, 상기 P-웰의 상부에 형성되는 NMOS의 소오스 및 드레인 영역과, 상기 P-웰, 그리고, 상기 N-웰로 구성되는 NPN 바이폴라 접합 트랜지스터의 문턱 전압이 감소되는 결과가 초래되고, 아울러, 상기 P-웰과, 상기 N-웰, 그리고, P형 기판으로 구성되는 PNP 바이폴라 접합 트랜지스터의 문턱 전압이 감소되는 결과가 초래되어, 결과적으로는, 소자의 구동시에 누설 전류가 증가되는 현상이 초래된다.However, in this process, a compensation effect between the dopants occurs between boron (B), which is a dopant of P-well, and phosphorus (P), a dopant of N-well formed under the P-well. A decrease in the concentration of boron (B) in the well and a decrease in the concentration of phosphorus (P) in the N-well occur, so that the source and drain regions of the NMOS formed on the P-well, and the P-well In addition, the threshold voltage of the NPN bipolar junction transistor composed of the N-well is reduced, and the PNP bipolar junction transistor composed of the P-well, the N-well, and the P-type substrate is also obtained. The result is that the threshold voltage is reduced, resulting in an increase in leakage current when the element is driven.
한편, 누설 전류가 증가되는 현상을 억제시키기 위하여, 종래에는 P-웰 형성을 위한 도펀트로서 붕소(B) 대신에 상대적으로 이동도가 낮은 이불화붕소(BF2)를 이온주입하는 방법도 시도되고 있으나, 이 방법의 경우에는 이불화붕소(BF2)의 이온주입후, P-웰 내에 존재하는 잔류 불소(F)로 인하여 소자의 전기적 특성이 저하되는 또 다른 문제점이 발생된다.On the other hand, in order to suppress the phenomenon that the leakage current increases, a method of ion implanting a relatively low mobility boron difluoride (BF 2 ) instead of boron (B) as a dopant for forming a P-well is also attempted However, in this method, another problem that the electrical characteristics of the device is degraded due to residual fluorine (F) present in the P-well after implantation of boron difluoride (BF 2 ).
따라서, 상기와 같은 문제점을 해결하기 위하여 안출된 본 발명은, P-웰 형성을 위한 도펀트로서 이불화붕소(BF2)를 사용함으로써, 소자 구동시에 누설 전류가 증가되는 현상을 방지하며, 아울러, P-웰 내에 존재하는 잔류 불소(F)를 다단계 어닐링 공정을 통해 제거함으로서, 상기 잔류 뷸소(F)에 기인된 소자의 전기적 특성 저하를 방지할 수 있는 반도체 소자의 삼중-웰 형성방법을 제공하는 것이다.Therefore, the present invention devised to solve the above problems, by using the boron difluoride (BF 2 ) as a dopant for forming the P-well, to prevent the phenomenon that the leakage current increases during device driving, By removing residual fluorine (F) present in the P-well through a multi-stage annealing process, to provide a triple-well formation method of a semiconductor device that can prevent the degradation of the electrical characteristics of the device caused by the residual fluorine (F) will be.
도 1a 내지 도 1c는 본 발명의 실시예에 따른 삼중-웰 구조의 형성방법을 설명하기 위한 공정 단면도.1A to 1C are cross-sectional views illustrating a method of forming a triple-well structure according to an embodiment of the present invention.
도 2는 본 발명의 실시예에 따른 급속열처리시의 온도 상승 및 하강 속도를 설명하기 위한 도면.2 is a view for explaining the temperature rise and fall rate during rapid heat treatment according to an embodiment of the present invention.
(도면의 주요 부분에 대한 부호의 설명)(Explanation of symbols for the main parts of the drawing)
1 : P형 기판 2 : 소자분리막1: P-type substrate 2: device isolation film
3 : 스크린 산화막 4 : 제1감광막 패턴3: screen oxide film 4: first photosensitive film pattern
5 : N-웰 6 : 제2감광막 패턴5: N-well 6: second photosensitive film pattern
7 : P-웰 8 : P-N 접합 영역7: P-well 8: P-N junction region
상기와 같은 목적을 달성하기 위한 본 발명의 실시예에 따른 반도체 소자의 삼중-웰 형성방법은, 소자 영역을 한정하는 소자분리막들이 형성되고, 상기 소자 영역의 표면에는 스크린 산화막이 형성된 P형 기판을 제공하는 단계; 상기 P형 기판 상에 소자 영역을 노출시키는 제1이온주입 마스크를 형성하는 단계; 상기 노출된 P형 기판의 소자 영역 내에 N형 불순물을 이온주입한 후, 어닐링을 수행하여 N-웰을 형성하는 단계; 상기 제1이온주입 마스크를 제거하는 단계; 상기 N-웰이 형성된 상기 P형 기판 상에 상기 N-웰의 일부분을 노출시키는 제2이온주입 마스크를 형성하는 단계; 상기 노출된 N-웰 내에 이불화붕소(BF2)를 이온주입한 후, 어닐링을 수행하여 P-웰을 형성하는 단계; 상기 제2이온주입 마스크 및 상기 스크린 마스크를 제거하는 단계; 및 상기 P-웰 내에 존재하는 불소(F)가 제거되도록, 상기 결과물에 대한 1차 및 2차 어닐링을 연속적으로 수행하는 단계를 포함하여 이루어진다.In the method of forming a triple-well of a semiconductor device according to an embodiment of the present invention for achieving the above object, device isolation films defining a device region are formed, and a P-type substrate having a screen oxide film formed on the surface of the device region. Providing; Forming a first ion implantation mask exposing a device region on the P-type substrate; Implanting an N-type impurity into the device region of the exposed P-type substrate, and then performing annealing to form an N-well; Removing the first ion implantation mask; Forming a second ion implantation mask exposing a portion of the N-well on the P-type substrate on which the N-well is formed; Ion implanting boron difluoride (BF 2 ) into the exposed N-well, followed by annealing to form a P-well; Removing the second ion implantation mask and the screen mask; And continuously performing primary and secondary annealing on the resultant to remove fluorine (F) present in the P-well.
상기에서, 1차 어닐링은 450 내지 600℃의 저온에서 1 내지 2시간 동안 수행하며, 상기 2차 어닐링은 900 내지 1,200℃의 고온에서 10 내지 60초 동안 급속열처리로 수행한다.In the above, the first annealing is performed for 1 to 2 hours at a low temperature of 450 to 600 ℃, the second annealing is carried out by rapid heat treatment for 10 to 60 seconds at a high temperature of 900 to 1,200 ℃.
본 발명에 따르면, 삼중-웰 구조를 형성함에 있어서, P-웰의 도펀트로서 BF2를 사용하기 때문에 누설 전류가 초래되는 것을 방지할 수 있고, 또한, P-웰을 형성한 후에는 저온 어닐링 및 급속열처리를 통해 잔류 불소를 제거함으로써, 상기 잔류 불소에 기인된 소자의 전기적 특성 저하를 방지할 수 있다.According to the present invention, in forming the triple-well structure, since the use of BF 2 as the dopant of the P-well, leakage current can be prevented, and after forming the P-well, the low temperature annealing and By removing residual fluorine through rapid heat treatment, it is possible to prevent the deterioration of electrical characteristics of the device due to the residual fluorine.
이하, 첨부된 도면에 의거하여 본 발명의 바람직한 실시예를 보다 상세하게설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 1a 및 도 1c는 본 발명의 실시예에 따른 반도체 소자의 삼중-웰 형성방법을 설명하기 위한 공정 단면도이다.1A and 1C are cross-sectional views illustrating a method of forming a triple-well of a semiconductor device according to an embodiment of the present invention.
먼저, 도 1a에 도시된 바와 같이, P형 기판(1)의 일측 표면에 공지된 로코스 공정으로 소자 영역을 한정하는 소자분리막들(2)을 형성하고, 이어서, 후속의 이온주입시에 상기 기판(1)이 받게 되는 스트레스를 감소시키기 위하여, 상기 P형 기판(1)의 표면 상에 박막의 스크린 산화막(3)을 형성한다. 그런다음, 상기 P형 기판(1) 상에 NMOS가 형성될 영역을 한정하는 제1감광막 패턴(3)을 형성한다. 여기서, 상기 제1감광막 패턴(4)은 NMOS 영역을 한정할 뿐만 아니라, 후속의 이온주입 공정에서 이온주입 마스크로서의 기능을 한다. 계속해서, 상기 제1감광막 패턴(4)을 이온주입 마스크로해서, 노출된 P형 기판 부분에 N형 불순물, 예를들어, 인(P) 이온을 1.2∼2MeV의 에너지 및 1.0∼5.0×1013원자/㎠의 도우즈(dose)로 이온주입하고, 연이어서, 어닐링 공정을 수행하여 상기 노출된 P형 기판 부분 내에 N-웰(5)을 형성한다.First, as shown in FIG. 1A, device isolation films 2 defining device regions are formed on one surface of the P-type substrate 1 by a known LOCOS process, and then, during subsequent ion implantation. In order to reduce the stress that the substrate 1 is subjected to, a thin screen oxide film 3 is formed on the surface of the P-type substrate 1. Then, a first photoresist pattern 3 is formed on the P-type substrate 1 to define a region where an NMOS is to be formed. Here, the first photoresist layer pattern 4 not only defines an NMOS region, but also functions as an ion implantation mask in a subsequent ion implantation process. Subsequently, using the first photoresist pattern 4 as an ion implantation mask, N-type impurities, such as phosphorus (P) ions, were exposed to energy of 1.2 to 2MeV and 1.0 to 5.0 × 10 to the exposed P-type substrate. Ion implantation with a 13 atom / cm 2 dose, followed by an annealing process, forms an N-well 5 in the exposed P-type substrate portion.
다음으로, 상기 제1감광막 패턴을 제거한 상태에서, 도 1b에 도시된 바와 같이, P형 기판(1) 상에 N-웰(5)의 일부분을 노출시키는 제2감광막 패턴(6)을 형성한다. 그런다음, 상기 제2감광막 패턴(6)을 이온주입 마스크로해서, 노출된 N-웰(5) 내에 이불화붕소(BF2)를 450∼1,800KeV의 에너지 및 1.0∼5.0×103원자/㎠의 도우즈로 이온주입하고, 연이어서, 어닐링을 수행하여 상기 N-웰(5) 내에 P-웰(7)을 형성한다.Next, with the first photoresist pattern removed, a second photoresist pattern 6 is formed on the P-type substrate 1 to expose a portion of the N-well 5, as shown in FIG. 1B. . Then, using the second photoresist pattern 6 as an ion implantation mask, boron difluoride (BF 2 ) in the exposed N-well 5 is 450-1,800 KeV of energy and 1.0-5.0 × 10 3 atoms / Ion implantation with a cm 2 dose, followed by annealing, forms a P-well 7 in the N-well 5.
그 다음, 도 1c에 도시된 바와 같이, 이온주입 마스크로 사용된 제2감광막 패턴과 기판 보호용 스크린 산화막을 제거하고, 이어서, P-웰 내에 존재하는 잔류 불소(F)를 제거하기 위하여 2단계에 걸쳐 어닐링을 수행한다.Next, as shown in FIG. 1C, the second photoresist pattern and the substrate protection screen oxide film used as the ion implantation mask are removed, and then in step 2 to remove residual fluorine (F) present in the P-well. Annealing is carried out over.
여기서, 1단계 어닐링은 질소 분위기 및 450 내지 600℃의 저온에서 1∼12시간 동안 수행한다. 이때, 상기한 온도에서 어닐링을 수행하는 이유는 상기한 온도가 P-웰 내에 존재하는 잔류 불소(F)를 거동시키기 위한 최소한의 온도이기 때문이며, 특히, 기판(1)이 받게 되는 열을 최소화시킴으로써, P-웰(7)과 N-웰(5)의 도펀트들간의 상쇄 효과가 일어나는 것을 방지할 수 있기 때문이고, 상기한 1단계 어닐링의 결과, 상기 P-웰(7) 내에 존재하는 잔류 불소(F)의 대부분, 예를들어, 70% 이상은 제거된다.Here, the one-step annealing is performed for 1 to 12 hours in a nitrogen atmosphere and low temperature of 450 to 600 ℃. At this time, the annealing is performed at the above temperature because the above temperature is the minimum temperature for behavior of residual fluorine (F) present in the P-well, and in particular, by minimizing the heat This is because the offset effect between the dopants of the P-well 7 and the N-well 5 can be prevented from occurring, and as a result of the above-described one-step annealing, residual fluorine present in the P-well 7 can be prevented. Most of (F), for example, at least 70% is removed.
한편, 1단계 어닐링에 의한 잔류 불소(F)의 제거는 기판(1) 표면에 가까운 위치에서부터 이루어지기 때문에, 상기 기판(1) 표면으로부터 상대적으로 멀리 떨어져 존재하는 잔류 불소(F)는 제거되지 않으며, 특히, P-웰(7)과 N-웰(5)간의 경계 부분에 존재하는 잔류 불소(F)는 거의 제거되지 않는다.On the other hand, since the removal of residual fluorine (F) by the one-step annealing is made from a position close to the surface of the substrate 1, the residual fluorine (F) which is relatively far from the surface of the substrate 1 is not removed. In particular, residual fluorine (F) present at the boundary portion between the P-well 7 and the N-well 5 is hardly removed.
따라서, P-웰(7)과 N-웰(5)의 경계 부분에 존재하는 잔류 불소(F)를 제거하기 위하여, 본 발명의 실시예에서는 2단계 어닐링을 900 내지 1,200℃의 고온에서 10 내지 60초 동안 급속열처리(Rapid Thermal Process)로 수행한다. 또한, 상기 급속열처리는 잔류 불소(F)의 제거가 극대화되도록, 암모니아 가스 분위기에서 수행한다. 이때, 상기한 온도 및 시간 동안에는 P-웰(7) 및 N-웰(5)에서의 도펀트들의거동은 최소화되는 반면, 상기 P-웰(7)과 N-웰(5)의 경계부에 존재하는 잔류 불소(F)는 효과적으로 제거된다.Therefore, in order to remove residual fluorine (F) present at the boundary of the P-well 7 and the N-well 5, in the embodiment of the present invention, the two-stage annealing is performed at 10 to 10 at a high temperature of 900 to 1,200 ° C. It is performed by Rapid Thermal Process for 60 seconds. In addition, the rapid heat treatment is performed in an ammonia gas atmosphere to maximize the removal of residual fluorine (F). At this time, the behavior of the dopants in the P-well 7 and the N-well 5 is minimized during the above temperature and time, while being present at the boundary between the P-well 7 and the N-well 5. Residual fluorine (F) is effectively removed.
여기서, 상기 급속열처리시에는 도펀트들의 거동을 최소화시키기 위하여, 온도 상승(Lamping up) 및 온도 하강(Lamping down) 속도를 대략 50∼100℃/sec 정도로 한다.Here, in the rapid heat treatment, in order to minimize the behavior of the dopants, the temperature ramping up and ramping down rates are about 50-100 ° C./sec.
자세하게, 도 2는 상기 급속열처리시의 온도 상승 및 하강 속도를 설명하기 위한 도면으로서, 도시된 바와 같이, 800℃ 이하의 온도 상승 구간(A)에서는 도펀트들간의 상쇄 효과를 최소화시키기 위하여 온도 상승 속도를 100℃/sec 이내로 하고, 800℃ 이상의 구간(B)에서는 온도 상승 및 하강 속도를 50℃/sec 정도로 하며, 800℃ 이하의 온도 하강 구간(C)에서는 온도 하강 속도를 50∼100℃/sec 정도로 한다.In detail, Figure 2 is a view for explaining the temperature rise and fall rate during the rapid heat treatment, as shown, the temperature rise rate to minimize the offset effect between the dopants in the temperature rise section (A) of 800 ℃ or less Is within 100 ° C./sec, and the temperature rise and fall rate is about 50 ° C./sec in a section B of 800 ° C. or higher, and the temperature drop rate is 50 to 100 ° C./sec in a temperature drop section C of 800 ° C. or less. It is enough.
그러므로, 본 발명의 실시예에 따르면, 붕소(B)에 비해 상대적으로 이동도가 낮은 이불화붕소(BF2)가 P-웰 형성용 도펀트로 이용되므로, P-웰(7)과 N-웰(8)간의 P-N 접합 영역(8)에서의 웰 농도의 저하를 방지할 수 있게 되며, 이에 따라, 바이폴라 접합 트랜지스터의 문턱 전압 특성의 저하를 방지할 수 있게 된다. 또한, 1차 및 2차 어닐링을 통해 P-웰에 존재하는 잔류 불소(F)를 거의 모두 제거함으로써, 상기 잔류 불소(F)에 기인된 소자의 전기적 특성 저하를 방지할 수 있게 된다.Therefore, according to the embodiment of the present invention, since boron difluoride (BF 2 ) having a relatively low mobility compared to boron (B) is used as a dopant for forming P-wells, P-well 7 and N-wells. It is possible to prevent a decrease in the well concentration in the PN junction region 8 between (8), thereby preventing a decrease in the threshold voltage characteristic of the bipolar junction transistor. In addition, by removing almost all residual fluorine (F) present in the P-well through the primary and secondary annealing, it is possible to prevent the deterioration of the electrical characteristics of the device caused by the residual fluorine (F).
이상에서와 같이, 본 발명은 삼중-웰 구조를 형성함에 있어서, P-웰과 N-웰사이에 존재하는 P-N 접합 영역에서의 웰 농도 감소를 억제시킬 수 있기 때문에, 바이폴라 접합 트랜지스터의 문턱 전압 특성 저하를 방지할 수 있고, 그래서, 소자 구동시 누설 전류의 증가를 방지할 수 있다.As described above, the present invention can suppress the decrease in the well concentration in the PN junction region existing between the P-well and the N-well in forming the triple-well structure, and thus the threshold voltage characteristic of the bipolar junction transistor. The fall can be prevented, and therefore, an increase in leakage current when driving the element can be prevented.
또한, 2단계에 걸친 어닐링을 통해 P-웰 내에 존재하는 잔류 불소(F)를 거의 모두 제거할 수 있기 때문에, 소자의 전기적 특성 향상 및 그 신뢰성을 향상시킬 수 있다.In addition, since almost all residual fluorine (F) present in the P-well can be removed through the annealing in two steps, it is possible to improve the electrical characteristics of the device and its reliability.
한편, 여기에서는 본 발명의 특정 실시예에 대하여 설명하고 도시하였지만, 당업자에 의하여 이에 대한 수정과 변형을 할 수 있다. 따라서, 이하, 특허청구의 범위는 본 발명의 진정한 사상과 범위에 속하는 한 모든 수정과 변형을 포함하는 것으로 이해할 수 있다.Meanwhile, although specific embodiments of the present invention have been described and illustrated, modifications and variations can be made by those skilled in the art. Accordingly, the following claims are to be understood as including all modifications and variations as long as they fall within the true spirit and scope of the present invention.
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