KR100624697B1 - Method for forming the dual poly gate of the recessed transistor - Google Patents

Method for forming the dual poly gate of the recessed transistor Download PDF

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KR100624697B1
KR100624697B1 KR1020050056951A KR20050056951A KR100624697B1 KR 100624697 B1 KR100624697 B1 KR 100624697B1 KR 1020050056951 A KR1020050056951 A KR 1020050056951A KR 20050056951 A KR20050056951 A KR 20050056951A KR 100624697 B1 KR100624697 B1 KR 100624697B1
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ion implantation
manufacturing
semiconductor device
recess
gate polysilicon
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장세억
이래희
양홍선
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주식회사 하이닉스반도체
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    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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    • H01L29/1025—Channel region of field-effect devices
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location

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Abstract

본 발명은 게이트 폴리실리콘막에 균일한 농도의 이온주입을 하기 위한 반도체 소자의 제조방법을 제공하기 위한 것으로, 본 발명의 반도체 소자의 제조방법은 반도체 기판의 일부를 선택적으로 식각하여 리세스를 형성하는 단계, 상기 리세스가 형성된 기판 상에 게이트 폴리실리콘막을 형성하는 단계, 상기 리세스 영역의 내부에 매립된 상기 폴리실리콘막을 타겟으로 제1 이온주입하여 도핑하는 단계, 상기 기판 상부의 상기 폴리실리콘막을 타겟으로 제2 이온주입하여 도핑하는 단계, 및 상기 제1 및 제2 이온주입에 의한 도펀트들을 활성화 시키기 위한 어닐을 실시하는 단계를 포함하고, 본 발명은 반도체 소자의 수율 향상을 좋게하여 소자의 신뢰성을 확보하고, 소자 특성을 향상 시킬 수 있는 효과가 있다. The present invention is to provide a method for manufacturing a semiconductor device for implanting ions of uniform concentration into the gate polysilicon film, the method of manufacturing a semiconductor device of the present invention selectively etching a portion of the semiconductor substrate to form a recess Forming a gate polysilicon film on the recessed substrate, doping the polysilicon film embedded in the recess region with a first ion implanted into the target, and doping the polysilicon on the substrate. And implanting a film into the target with a second ion implantation, and performing annealing to activate the dopants by the first and second ion implantation. It is effective in ensuring reliability and improving device characteristics.

듀얼폴리게이트, 이온주입, 리세스게이트, 폴리실리콘, 어닐 Dual Polygate, Ion Implantation, Recess Gate, Polysilicon, Annealed

Description

리세스 트랜지스터의 듀얼폴리게이트 제조방법{METHOD FOR FORMING THE DUAL POLY GATE OF THE RECESSED TRANSISTOR}TECHNICAL FOR FORMING THE DUAL POLY GATE OF THE RECESSED TRANSISTOR}

도 1a 내지 도 1d는 종래기술에 따른 반도체 소자의 제조방법을 설명하기 위한 공정 단면도.1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

도 2a 내지 도 2d는 본 발명의 바람직한 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 공정 단면도.2A to 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a preferred embodiment of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

31 : 반도체기판 32 : 소자분리막31: semiconductor substrate 32: device isolation film

33 : 마스크 패턴 34 : 리세스33: mask pattern 34: recess

35 : 게이트 절연막 36 : 게이트 폴리실리콘막35 gate insulating film 36 gate polysilicon film

37 : 포토레지스트37: photoresist

본 발명은 반도체 제조 기술에 관한 것으로, 특히 리세스 트랜지스터의 듀얼 폴리 게이트를 갖는 반도체 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing techniques, and more particularly to a method of manufacturing a semiconductor device having dual poly gates of a recess transistor.

반도체 소자의 소형화, 직접화에 따라 트랜지스터의 채널길이(Channel length)가 짧아지고 있다. 이에 따라, 문턱전압(threshold voltage)이 급격히 낮아지는 숏채널효과(short channel effect)가 심해지는 문제점이 있다.As the semiconductor device becomes smaller and more direct, the channel length of the transistor is shortened. Accordingly, there is a problem in that a short channel effect in which a threshold voltage is sharply lowered becomes severe.

이러한 문제를 해결하기 위해 반도체 기판에 리세스를 형성하여 채널길이를 증가시키는 리세스 게이트 트랜지스터(Recessed Gate Transistor)가 제안되었다.In order to solve this problem, a recessed gate transistor has been proposed that increases the channel length by forming a recess in a semiconductor substrate.

한편, 반도체 소자의 싱글게이트에서 효율문제를 해결하고자 트랜지스터의 게이트전극을 nMOSFET 경우는 n형으로, pMOSFET 경우는 p형으로 도핑하는 듀얼게이트전극(Dual Gate Electrode)가 제안되었다. 상기 듀얼게이트전극은 게이트 폴리실리콘(Gate Polysilicon)에서 nMOSFET 경우는 n형 원소인 인(P)을, pMOSFET 경우는 p형 원소인 붕소(B)를 이온주입할 수 있다.On the other hand, in order to solve the efficiency problem in a single gate of a semiconductor device, a dual gate electrode is proposed in which a gate electrode of a transistor is doped with n-type nMOSFET and p-type pMOSFET. In the gate polysilicon, the dual gate electrode may ion-inject phosphorus (P), an n-type element in the case of nMOSFET, and boron (B), a p-type element in the case of pMOSFET.

이하, 종래기술에 따른 반도체 소자의 제조방법을 설명하기로 한다.Hereinafter, a method of manufacturing a semiconductor device according to the prior art will be described.

도 1a에 도시된 바와 같이, STI공정을 통해 반도체 기판(21)에 소자분리막(22)을 형성한다. 상기 소자분리막(22)을 포함한 반도체 기판(21)상에 마스크 패턴(23)을 형성한다.As shown in FIG. 1A, the device isolation layer 22 is formed on the semiconductor substrate 21 through an STI process. The mask pattern 23 is formed on the semiconductor substrate 21 including the device isolation layer 22.

도 1b에 도시된 바와 같이, 상기 마스크 패턴(23)으로 반도체 기판(21)을 식각하여 리세스(24)를 형성한다. 상기 형성된 리세스(24)를 포함한 반도체 기판(21)상에 게이트 절연막(25)를 형성한다.As illustrated in FIG. 1B, the semiconductor substrate 21 is etched using the mask pattern 23 to form a recess 24. A gate insulating film 25 is formed on the semiconductor substrate 21 including the recess 24 formed above.

도 1c에 도시된 바와 같이, 상기 리세스(24)가 형성된 기판 상에 게이트 폴 리실리콘막(26)을 형성한다. 이때, 상기 게이트 폴리실리콘막(26)은 도핑이 전혀 되지 않은 폴리실리콘(undoped polysilicon)이다.As shown in FIG. 1C, a gate polysilicon film 26 is formed on a substrate on which the recess 24 is formed. In this case, the gate polysilicon layer 26 is undoped polysilicon.

도 1d에 도시된 바와 같이, 상기 형성된 게이트 폴리실리콘막(26)에 이온주입을 실시한다. 이때, 이온주입의 깊이는 기판 상부의 폴리실리콘막(26a)에 위치하도록 에너지를 조절하고, nMOSFET의 경우는 n형 원소인 인(P)을, pMOSFET의 경우는 p형 원소인 붕소(B)를 각각 이온주입할 수 있다.As shown in FIG. 1D, ion implantation is performed to the formed gate polysilicon film 26. At this time, the depth of ion implantation is controlled so that the energy is located in the polysilicon film 26a on the upper substrate, n-type phosphorus (P) in the case of nMOSFET, and boron (B) -type element in the case of pMOSFET. Can be ion implanted respectively.

상기한 종래기술은 리세스내부의 폴리실리콘막에는 이온주입된 인(P) 또는 붕소(B)가 충분히 도달하지 못한다. 따라서, 이후에 활성화 어닐(Activation Anneal)공정을 실시하여도 리세스 트랜지스터의 게이트 폴리실리콘에는 예정된 이온주입을 할 수 없는 문제점이 있다.In the above-mentioned conventional technique, phosphorus (P) or boron (B) implanted with ions does not sufficiently reach the polysilicon film inside the recess. Therefore, there is a problem that a predetermined ion implantation cannot be performed on the gate polysilicon of the recess transistor even after the activation annealing process is performed later.

본 발명은 상기한 종래기술의 문제점을 해결하기 위해 제안된 것으로, 리세스 게이트 폴리실리콘막에 균일한 농도의 이온주입을 하기 위한 반도체 소자의 제조방법을 제공하는데 목적이 있다.The present invention has been proposed to solve the above problems of the prior art, and an object of the present invention is to provide a method of manufacturing a semiconductor device for ion implantation of uniform concentration in a recess gate polysilicon film.

상기 목적을 달성하기 위한 본 발명의 반도체 소자의 제조방법은 반도체 기판의 일부를 선택적으로 식각하여 리세스를 형성하는 단계, 상기 리세스가 형성된 기판 상에 게이트 폴리실리콘막을 형성하는 단계, 상기 리세스 영역의 내부에 매립 된 상기 폴리실리콘막을 타겟으로 제1 이온주입하여 도핑하는 단계, 상기 기판 상부의 상기 폴리실리콘막을 타겟으로 제2 이온주입하여 도핑하는 단계, 및 상기 제1 및 제2 이온주입에 의한 도펀트들을 활성화 시키기 위한 어닐을 실시하는 단계를 포함하는 것을 특징으로 한다.A method of manufacturing a semiconductor device of the present invention for achieving the above object comprises the steps of selectively etching a portion of the semiconductor substrate to form a recess, forming a gate polysilicon film on the recessed substrate, the recess Doping the polysilicon film embedded in the region by first ion implantation into a target, doping the polysilicon film on the substrate with a second ion implantation into a target, and doping the first and second ion implantation into the target And annealing to activate the dopants.

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

도 2a 내지 도 2d는 본 발명의 바람직한 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 공정 단면도이다.2A to 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a preferred embodiment of the present invention.

도 2a에 도시된 바와 같이, 소자분리공정(STI)을 통해 반도체 기판(31)에 소자분리막(32)를 형성한다. 상기 소자분리막(32)을 포함한 상기 반도체 기판(31)에 마스크 패턴(33)을 형성한다.As shown in FIG. 2A, the device isolation layer 32 is formed on the semiconductor substrate 31 through an element isolation process (STI). A mask pattern 33 is formed on the semiconductor substrate 31 including the device isolation layer 32.

도 2b에 도시된 바와 같이, 상기 노출된 반도체 기판(31)을 식각하여 리세스(34)를 형성한다. 이때, 리세스의 깊이는 1000~1800Å의 깊이로 할 수 있다. 상기 리세스(34)를 형성한 후, 마스크 패턴(33)을 제거하고 리세스(34)를 포함한 반도체 기판(31)상에 게이트 절연막(35)을 형성한다.As shown in FIG. 2B, the exposed semiconductor substrate 31 is etched to form a recess 34. At this time, the depth of the recess can be a depth of 1000 ~ 18001. After the recess 34 is formed, the mask pattern 33 is removed and the gate insulating layer 35 is formed on the semiconductor substrate 31 including the recess 34.

도 2c에 도시된 바와 같이, 상기 게이트 절연막(35)상에 게이트 폴리실리콘막(36)을 증착한다. 이때, 상기 폴리실리콘(36)은 도핑이 전혀 되지 않은 폴리실리콘으로, 증착 두께는 800~1500Å으로 할 수 있다. 상기 형성된 게이트 폴리실리콘막(26)상에 리세스(34)부분의 폴리실리콘막(26)이 오픈되도록 포토레지스트패턴 (38)을 형성한다.As shown in FIG. 2C, a gate polysilicon film 36 is deposited on the gate insulating film 35. At this time, the polysilicon 36 is polysilicon which is not doped at all, and the deposition thickness may be 800 to 1500 kPa. A photoresist pattern 38 is formed on the formed gate polysilicon layer 26 so that the polysilicon layer 26 of the recess 34 is opened.

상기 리세스(34)영역의 내부에 매립된 상기 폴리실리콘막(36a)을 타겟으로 제1 이온주입을 실시한다. 이때, 상기 제1 이온주입은 리세스의 중간부분이 되도록 이온주입 에너지를 선택하지만, 경우에 따라서는 위 또는 아래로 이온주입 조건을 조절 할 수 있다. 또한, 상기 제1 이온주입은 상기 리세스가 끝나는 부분 즉, 반도체 기판의 높이 이하로 제한한다. First ion implantation is performed using the polysilicon film 36a embedded in the recess 34 region as a target. At this time, the first ion implantation selects the ion implantation energy to be the middle portion of the recess, but in some cases, the ion implantation conditions can be adjusted up or down. In addition, the first ion implantation is limited to a portion where the recess ends, that is, the height of the semiconductor substrate.

상기 제1 이온주입은 nMOSFET의 경우 n형 원소인 인(P)를 5×1015∼1×1016ions/㎠의 농도로 55∼65keV 에너지로 실시하고, pMOSFET의 경우 p형 원소인 붕소(B)를 5×1015∼1×1016ions/㎠의 농도로 15∼25keV 에너지로 실시할 수 있다. 상기 제1 이온주입은 리세스 내부까지 되어야 하므로 상대적으로 많은 에너지를 가한다.The first ion implantation is performed with phosphorus (P), an n-type element, at a concentration of 5 × 10 15 to 1 × 10 16 ions / cm 2 for an nMOSFET at 55-65 keV energy, and boron (p-type element) for a pMOSFET. B) can be carried out at 15 to 25 keV energy at a concentration of 5 × 10 15 to 1 × 10 16 ions / cm 2. Since the first ion implantation has to be inside the recess, relatively high energy is applied.

도 2d에 도시된 바와 같이, 상기 제1 이온주입이 끝난 후, 포토레지스트(37)를 제거하고, 상기 기판 상부의 상기 폴리실리콘막의 상부(36b)를 타겟으로 제2 이온주입을 실시한다. 이때, 상기 제2 이온주입은 nMOSFET의 경우 n형 원소인 인(P)를 5×1015∼1×1016ions/㎠의 농도로 13∼17keV 에너지로 실시하고, pMOSFET의 경우 p형 원소인 붕소(B)를 5×1015∼1×1016ions/㎠의 농도로 3∼6keV 에너지로 실시할 수 있다.As shown in FIG. 2D, after the first ion implantation is finished, the photoresist 37 is removed, and a second ion implantation is performed on the upper portion 36b of the polysilicon film on the substrate. In this case, the second ion implantation is carried out with phosphorus (P), which is an n-type element in the case of nMOSFET, at a concentration of 13 to 17 keV energy at a concentration of 5 × 10 15 to 1 × 10 16 ions / cm 2, and is a p-type element in the case of pMOSFET. Boron (B) may be carried out at 3-6 keV energy at a concentration of 5 × 10 15 to 1 × 10 16 ions / cm 2.

상기 제1 및 제2 이온주입 실시 후, 활성화어닐(Activation Anneal)을 실시 하여 이온주입된 도펀트(Dopant)를 활성화시킨다. 이때, 상기 활성화어닐은 950∼1000℃의 온도에서 10∼60초 동안 실시할 수 있다.After the first and second ion implantation, activation annealing is performed to activate the ion implanted dopant. At this time, the activation annealing may be carried out for 10 to 60 seconds at a temperature of 950 ~ 1000 ℃.

상술한 바와 같이, 제1 및 제2 이온주입된 게이트 폴리실리콘막은 리세스내폴리실리콘에 이온주입을 예정된 농도로 도핑할 수 없는 문제점을 해결할 수 있다.As described above, the first and second ion implanted gate polysilicon films can solve the problem of not being able to dope the implanted polysilicon in the recess at a predetermined concentration.

본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

상술한 본 발명에 의한 반도체 소자의 제조방법은 소자의 수율 향상을 좋게하여 소자의 신뢰성을 확보하고, 소자 특성을 향상 시킬 수 있는 효과가 있다.The method of manufacturing a semiconductor device according to the present invention as described above has the effect of improving the yield of the device to ensure the reliability of the device, and improve the device characteristics.

Claims (10)

반도체 기판의 일부를 선택적으로 식각하여 리세스를 형성하는 단계;Selectively etching a portion of the semiconductor substrate to form a recess; 상기 리세스가 형성된 기판 상에 게이트 폴리실리콘막을 형성하는 단계;Forming a gate polysilicon film on the recessed substrate; 상기 리세스 영역의 내부에 매립된 상기 폴리실리콘막을 타겟으로 제1 이온주입하여 도핑하는 단계;Doping the polysilicon layer buried in the recess region with a first ion implanted into a target; 상기 기판 상부의 폴리실리콘막을 타겟으로 제2 이온주입하여 도핑하는 단계; 및Doping the polysilicon layer on the substrate with a second ion implantation into a target; And 상기 제1 및 제2 이온주입에 의한 도펀트들을 활성화 시키기 위한 어닐을 실시하는 단계Performing an anneal to activate the dopants by the first and second ion implantations. 를 포함한 반도체 소자의 제조방법.Method of manufacturing a semiconductor device comprising a. 제 1항에 있어서,The method of claim 1, 상기 제1 이온주입은 상기 리세스 영역의 상부가 노출된 마스크 패턴을 사용하여 실시하는 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 1, wherein the first ion implantation is performed using a mask pattern in which an upper portion of the recess region is exposed. 제 1항에 있어서,The method of claim 1, 상기 리세스는 1000∼1800Å의 깊이로 하는 것을 특징으로 하는 반도체 소자 의 제조방법.The recess is a manufacturing method of a semiconductor device, characterized in that the depth of 1000 ~ 1800Å. 제 1항에 있어서,The method of claim 1, 상기 게이트 폴리실리콘막은 800∼1500Å의 두께로 형성 하는 것을 특징으로 하는 반도체 소자의 제조방법.The gate polysilicon film is a manufacturing method of a semiconductor device, characterized in that formed to a thickness of 800 ~ 1500Å. 제 1항에 있어서,The method of claim 1, 상기 제1 이온주입은 상기 리세스의 중간깊이를 타겟으로 이온 주입 에너지를 선택하는 것을 특징으로 하는 반도체 소자의 제조방법.The first ion implantation method of manufacturing a semiconductor device, characterized in that for selecting the ion implantation energy to target the depth of the recess. 제 1항에 있어서,The method of claim 1, 상기 게이트 폴리실리콘은 nMOSFET의 게이트 폴리실리콘이며, 상기 제1 이온주입은 인의 이온주입 조건을 5×1015∼1×1016ions/㎠의 주입량으로 55∼65keV에너지로 하는 것을 특징으로 하는 반도체 소자의 제조방법.The gate polysilicon is a gate polysilicon of an nMOSFET, and the first ion implantation is a semiconductor device characterized in that the ion implantation condition of phosphorus is 55 to 65 keV energy at an implantation amount of 5 × 10 15 to 1 × 10 16 ions / cm 2. Manufacturing method. 제 1항에 있어서,The method of claim 1, 상기 게이트 폴리실리콘은 pMOSFET의 게이트 폴리실리콘이며, 상기 제1 이온주입은 붕소의 이온주입 조건을 5×1015∼1×1016ions/㎠의 주입량으로 15∼25keV에너지로 하는 것을 특징으로 하는 반도체 소자의 제조방법.The gate polysilicon is a gate polysilicon of a pMOSFET, and the first ion implantation is a semiconductor, wherein the ion implantation condition of boron is 15 to 25 keV energy at an implantation amount of 5 × 10 15 to 1 × 10 16 ions / cm 2. Method of manufacturing the device. 제 1항에 있어서,The method of claim 1, 상기 게이트 폴리실리콘은 nMOSFET의 게이트 폴리실리콘이며, 상기 제2 이온주입은 인의 이온주입 조건을 5×1015∼1×1016ions/㎠의 주입량으로 13∼17keV에너지로 하는 것을 특징으로 하는 반도체 소자의 제조방법.The gate polysilicon is a gate polysilicon of an nMOSFET, and the second ion implantation is a semiconductor device characterized in that the ion implantation condition of phosphorus is 13 to 17 keV energy at an implantation amount of 5 × 10 15 to 1 × 10 16 ions / cm 2. Manufacturing method. 제 1항에 있어서,The method of claim 1, 상기 게이트 폴리실리콘은 pMOSFET의 게이트 폴리실리콘이며, 상기 제2 이온주입은 인의 이온주입 조건을 5×1015∼1×1016ions/㎠의 주입량으로 3∼6keV에너지로 하는 것을 특징으로 하는 반도체 소자의 제조방법.The gate polysilicon is a gate polysilicon of a pMOSFET, and the second ion implantation is a semiconductor device, wherein the ion implantation conditions of phosphorus are 3 to 6 keV energy at an implantation amount of 5 × 10 15 to 1 × 10 16 ions / cm 2. Manufacturing method. 제 1항에 있어서,The method of claim 1, 상기 어닐은 950∼1000℃에서 10∼60초 동안 실시함을 특징으로 하는 반도체 소자의 제조방법.The annealing is performed for 10 to 60 seconds at 950 to 1000 ℃ manufacturing method of a semiconductor device.
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KR101096250B1 (en) * 2009-06-15 2011-12-22 주식회사 하이닉스반도체 Doping method for p-type poly-gate for preventing seam moving and method of fabricating the poly-gate using the same
CN112530810A (en) * 2020-11-24 2021-03-19 北海惠科光电技术有限公司 Preparation method of switch element, preparation method of array substrate and display panel

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KR20020002808A (en) * 2000-06-30 2002-01-10 박종섭 Method of manufacturing poly-silicon layer in semiconductor device

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020002808A (en) * 2000-06-30 2002-01-10 박종섭 Method of manufacturing poly-silicon layer in semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101096250B1 (en) * 2009-06-15 2011-12-22 주식회사 하이닉스반도체 Doping method for p-type poly-gate for preventing seam moving and method of fabricating the poly-gate using the same
CN112530810A (en) * 2020-11-24 2021-03-19 北海惠科光电技术有限公司 Preparation method of switch element, preparation method of array substrate and display panel
CN112530810B (en) * 2020-11-24 2023-06-16 北海惠科光电技术有限公司 Preparation method of switching element, preparation method of array substrate and display panel

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