TW200428538A - Method of fabricating vertical integrated circuits - Google Patents

Method of fabricating vertical integrated circuits Download PDF

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Publication number
TW200428538A
TW200428538A TW092132601A TW92132601A TW200428538A TW 200428538 A TW200428538 A TW 200428538A TW 092132601 A TW092132601 A TW 092132601A TW 92132601 A TW92132601 A TW 92132601A TW 200428538 A TW200428538 A TW 200428538A
Authority
TW
Taiwan
Prior art keywords
layer
semiconductor layer
layers
bonded
substrate
Prior art date
Application number
TW092132601A
Other languages
English (en)
Chinese (zh)
Inventor
Sadeg M Faris
Original Assignee
Reveo Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Reveo Inc filed Critical Reveo Inc
Publication of TW200428538A publication Critical patent/TW200428538A/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C99/00—Subject matter not provided for in other groups of this subclass
    • B81C99/0035—Testing
    • B81C99/0045—End test of the packaged device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Micromachines (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)
TW092132601A 2002-11-20 2003-11-20 Method of fabricating vertical integrated circuits TW200428538A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US42812502P 2002-11-20 2002-11-20

Publications (1)

Publication Number Publication Date
TW200428538A true TW200428538A (en) 2004-12-16

Family

ID=33551213

Family Applications (3)

Application Number Title Priority Date Filing Date
TW092132601A TW200428538A (en) 2002-11-20 2003-11-20 Method of fabricating vertical integrated circuits
TW092132599A TW200423261A (en) 2002-11-20 2003-11-20 Method of fabricating multi-layer devices on buried oxide layer substrates
TW092132597A TW200421497A (en) 2002-11-20 2003-11-20 Method and system for increasing yield of vertically integrated devices

Family Applications After (2)

Application Number Title Priority Date Filing Date
TW092132599A TW200423261A (en) 2002-11-20 2003-11-20 Method of fabricating multi-layer devices on buried oxide layer substrates
TW092132597A TW200421497A (en) 2002-11-20 2003-11-20 Method and system for increasing yield of vertically integrated devices

Country Status (8)

Country Link
US (1) US7056751B2 (enExample)
EP (1) EP1573788A3 (enExample)
JP (1) JP2006520089A (enExample)
KR (1) KR20050083935A (enExample)
CN (1) CN1742358A (enExample)
AU (1) AU2003304218A1 (enExample)
TW (3) TW200428538A (enExample)
WO (1) WO2004112089A2 (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI728778B (zh) * 2020-02-20 2021-05-21 大陸商長江存儲科技有限責任公司 具有xtacking架構的動態隨機存取儲存器（dram）記憶體元件
TWI880532B (zh) * 2023-04-26 2025-04-11 大陸商上海易卜半導體有限公司 晶片堆疊及製備方法

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FR2839505B1 (fr) * 2002-05-07 2005-07-15 Univ Claude Bernard Lyon Procede pour modifier les proprietes d'une couche mince et substrat faisant application du procede
US7659631B2 (en) * 2006-10-12 2010-02-09 Hewlett-Packard Development Company, L.P. Interconnection between different circuit types
US20090026524A1 (en) * 2007-07-27 2009-01-29 Franz Kreupl Stacked Circuits
CN102844176A (zh) * 2009-09-30 2012-12-26 微型实验室诊断股份有限公司 微流体装置中选择性的粘结性降低
KR101348655B1 (ko) * 2010-03-24 2014-01-08 한국전자통신연구원 미세유체 제어 장치 및 그 제조 방법
US8829329B2 (en) * 2010-08-18 2014-09-09 International Business Machines Corporation Solar cell and battery 3D integration
DE102010041763A1 (de) 2010-09-30 2012-04-05 Siemens Aktiengesellschaft Mikromechanisches Substrat
US10543662B2 (en) 2012-02-08 2020-01-28 Corning Incorporated Device modified substrate article and methods for making
TWI617437B (zh) 2012-12-13 2018-03-11 康寧公司 促進控制薄片與載體間接合之處理
US9340443B2 (en) 2012-12-13 2016-05-17 Corning Incorporated Bulk annealing of glass sheets
US10014177B2 (en) 2012-12-13 2018-07-03 Corning Incorporated Methods for processing electronic devices
US10086584B2 (en) 2012-12-13 2018-10-02 Corning Incorporated Glass articles and methods for controlled bonding of glass sheets with carriers
US10510576B2 (en) 2013-10-14 2019-12-17 Corning Incorporated Carrier-bonding methods and articles for semiconductor and interposer processing
JP6770432B2 (ja) 2014-01-27 2020-10-14 コーニング インコーポレイテッド 薄いシートの担体との制御された結合のための物品および方法
KR20160145062A (ko) 2014-04-09 2016-12-19 코닝 인코포레이티드 디바이스 변경된 기판 물품 및 제조 방법
JP2018524201A (ja) 2015-05-19 2018-08-30 コーニング インコーポレイテッド シートをキャリアと結合するための物品および方法
KR102524620B1 (ko) 2015-06-26 2023-04-21 코닝 인코포레이티드 시트 및 캐리어를 포함하는 방법들 및 물품들
US20170186730A1 (en) * 2015-12-26 2017-06-29 Invensas Corporation System and method for providing 3d wafer assembly with known-good-dies
JP7309364B2 (ja) 2016-06-01 2023-07-18 クアンタム－エスアイ インコーポレイテッド 分子を検出し分析するための集積デバイス
TWI892429B (zh) 2016-08-30 2025-08-01 美商康寧公司 用於片材接合的矽氧烷電漿聚合物
TWI810161B (zh) 2016-08-31 2023-08-01 美商康寧公司 具以可控制式黏結的薄片之製品及製作其之方法
KR102659516B1 (ko) 2017-08-18 2024-04-23 코닝 인코포레이티드 유리 적층체
WO2019118660A1 (en) 2017-12-15 2019-06-20 Corning Incorporated Method for treating a substrate and method for making articles comprising bonded sheets
US11315789B2 (en) * 2019-04-24 2022-04-26 Tokyo Electron Limited Method and structure for low density silicon oxide for fusion bonding and debonding
US11829077B2 (en) * 2020-12-11 2023-11-28 Kla Corporation System and method for determining post bonding overlay
US11782411B2 (en) 2021-07-28 2023-10-10 Kla Corporation System and method for mitigating overlay distortion patterns caused by a wafer bonding tool
CN114035030B (zh) * 2021-11-05 2023-10-24 爱迪特（秦皇岛）科技股份有限公司 一种测试组件
CN119275214B (zh) * 2024-12-10 2025-02-25 电子科技大学 一种用于腐蚀工艺监控的表征器件

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JPS63155731A (ja) * 1986-12-19 1988-06-28 Agency Of Ind Science & Technol 半導体装置
US5094697A (en) * 1989-06-16 1992-03-10 Canon Kabushiki Kaisha Photovoltaic device and method for producing the same
JP3214631B2 (ja) * 1992-01-31 2001-10-02 キヤノン株式会社 半導体基体及びその作製方法
JP4126747B2 (ja) * 1998-02-27 2008-07-30 セイコーエプソン株式会社 ３次元デバイスの製造方法
US6133582A (en) * 1998-05-14 2000-10-17 Lightspeed Semiconductor Corporation Methods and apparatuses for binning partially completed integrated circuits based upon test results
JP5121103B2 (ja) * 2000-09-14 2013-01-16 株式会社半導体エネルギー研究所 半導体装置、半導体装置の作製方法及び電気器具
US6965895B2 (en) * 2001-07-16 2005-11-15 Applied Materials, Inc. Method and apparatus for analyzing manufacturing data

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI728778B (zh) * 2020-02-20 2021-05-21 大陸商長江存儲科技有限責任公司 具有xtacking架構的動態隨機存取儲存器（dram）記憶體元件
TWI880532B (zh) * 2023-04-26 2025-04-11 大陸商上海易卜半導體有限公司 晶片堆疊及製備方法

Also Published As

Publication number Publication date
AU2003304218A1 (en) 2005-01-04
US7056751B2 (en) 2006-06-06
EP1573788A3 (en) 2005-11-02
US20040241888A1 (en) 2004-12-02
TW200421497A (en) 2004-10-16
AU2003304218A8 (en) 2005-01-04
TW200423261A (en) 2004-11-01
WO2004112089A2 (en) 2004-12-23
EP1573788A2 (en) 2005-09-14
CN1742358A (zh) 2006-03-01
WO2004112089A3 (en) 2005-09-15
KR20050083935A (ko) 2005-08-26
JP2006520089A (ja) 2006-08-31

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