TW200405184A - Characterization and reduction of variation for integrated circuits - Google Patents

Abstract

A method and system are described to reduce process variation as a result of the semiconductor processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to modify the design and manufacture of integrated circuits.

Description

200405184

Technical field to which the invention belongs ... The present invention relates to the analysis of characteristics of various integrated circuits. In the manufacture of integrated circuits, variations in layout patterns (such as material density: low. Chu different width, and line spacing) will affect the thickness of the interconnect layer, line fishing (dishing), and erosion (eroso). )And other issues. The disk surface usually affects subsequent process capabilities and process integration. The structure position on the table of the present invention affects the characteristics of the device by the variation of capacitance and resistance. Previous technology: For several categories

Xin's film thickness can be distinguished in chemical mechanical polishing (CMP): lot-to-lot, wafer-to-wafer, wafer-level to wafer-level to die_level) 〇CMp caused the main reason for the change of the user f comes from the difference in layout patterns on the wafer. Often the most obvious is the composition of the pattern or grain level. In general, the oxide layer does not begin to grind until all areas on the wafer have been flattened. However, even if the oxide layer can be planarized regionally, the subsequent CMP oxide layer thickness of the underlying metal pattern. U said ~

For the abrasive oxide layer, the density of the grain pattern is the main variation 3. The ratio of the rising area of the oxide layer in the entire area is defined as the pattern density. This area may be, for example, a flattened area. The flattening length is usually determined by process parameters, such as the type of grinding mill, CMP tools, and chemical composition of the slurry. Using filter (f i i ter) the designed layout density can calculate an effective pattern for each area on the die

200405184 V. Description of the invention (2) Density, generally use various two-dimensional density filters to analyze the area to be analyzed. For the CMP metal polishing process of the trench structure (damascene), there are still other physical layout effects, such as line width and line spacing. Both dishing and erosion effects occur during the CMP of metal trench structures. The difference in metal thickness between the edge of the wire and the center can be measured to measure the dishing phenomenon. The difference in the thickness of the oxide layer above the metal wire is defined as the phenomenon of erosion, especially in measurement-type wires adjacent to unpatterned areas. Figure 2A shows the trench process with copper features 1, 2 and corresponding wafer surface 3 in the oxidized area 4. Figure 2B shows the effect of the layout pattern on the thickness change of the metal layer during the CMP process. The expected wafer surface 5 does not match the actual wafer surface 6. Figure 2B shows the effects of dishing 7 and erosion 8 formed by copper CMP in a fine pitch line array. This figure shows that in addition to the pattern density in the trench process, it is necessary to predict the variation of other physical layout parameters. Adding a dummy fill structure can improve the flatness of the process. Since the density of a metal pattern is defined as the ratio of the metal in the area, increasing the dummy filling structure of the metal can increase the density of the pattern. Conversely, adding a dummy oxide layer can remove a part of the copper wire, and j has a low pattern density. This filling operation can also change other parameters such as line width and line door. If a dummy metal layer is placed between two parallel wires:: The line spacing between the two wires. If the structure adjustment is filled with additional dummy, the physical parameters, such as pattern density, line width, and sub-cloth, are changed. Due to the uneven spacing of the uneven metal or oxide layer formed by CMP, the physical parameters will change, regardless of the metal ratio added or removed, and S will increase the layout.

1057-5667-PF (Nl) .ptd

Coffee plus elephant cut} Wang Fuxing. Therefore, according to f), the metal bite 4 / μ is obtained ^ ^ ^ ^ 3. The process model of filling the pallidization layer is: The existing dummy filling structure to reduce the uneven thickness of the film is used to improve the film user * μ ^ " Add or remove the existing structure in the integrated circuit. / Inch thief: / yo! Uniform secret filling method of dummy oxide layer. The following two figures show the metal and structure. Figure 2C is frequency dry ^ #Figure 2 shows that the metal is filled into the knot in the center. The central area can be =-surrounded by a sequence of metal wires 10. A uniform pattern of dense sound is achieved everywhere, =. One purpose of the dummy filling is to make the film thickness. Such areas; can be :: accumulation and grinding processes can lead to flatness, especially such areas and electrical properties = taken as a dummy fill. The influence of special people on the capacitance value. In the 2Dm :, and the dummy filling can be reduced and placed in the oxidized area 13 to be used, the metal dummy filling structure 14 is still filled and surrounded by the structure: = This metal dummy is shown in Figure 3. Up to maintain electrical isolation. In the diagram, the metal area: imaginary two fills in the structure. In Fig. 3B, the oxygen layer is shown as a metal slot in dummy) 18 is added to the metal area 17: The grinding uniformity of this area can also be marked (reducing the thickness of the film: change the thickness of the filled area ^ means adding a dummy filling The area of the structure, and the "virtual structure" is the target embedded in this area. The structure of the seat is filled with the virtual $ and the structure can be filled. The pattern of the filled structure can be used. Figure 4A shows a symmetrical fill-in ^ ^ Often

200405184

V. Description of the invention (4) Use in placing dummy oxide layer in metal. Figures 4β and 40 show an asymmetric pattern, which is usually used to place a dummy metal layer (that is, a conductive material) in an insulating material (such as an oxide layer). The asymmetric pattern suppresses the induced valley effect between adjacent signal lines. This force is better than the symmetrical pattern and reduces cross-talk noise. Circuit designers expect that the addition of dummy fill structures will not alter the expected electrical performance. However, the addition of the dummy structure can inadvertently affect the electrical properties and reduce the performance of the chip. There are many important factors that must be considered for effective dummy fill processing. These factors include process impact, electrical impact, and impact of placement.

The electrical performance of the ® circuit can be limited by f, the capacitance value, which can be one of the interconnection design. Circuit performance f, such as signal delay, time should be the internal connection of the anode is the wiring resistance, metal layer. The capacitance value of the interconnects, the line spacing, and the routing between the wiring. Note that the interconnector fills in the structure or trench or the trench, etc., which will also be determined by the characteristics of the », and the interconnect is usually To be effective, such electrical parameters include the function of the interconnect resistance value and the circuit performance metrics clock skew, the crosstalk effect, and the capacitance value. Function of the resistance value of the interconnect, the length of the interconnect, and the line width as a function of the thickness of the metal layer, the length of the interconnect, the line width, and the dielectric constant of the body (oxide layer). g structure affects electrical properties. Therefore, if it is false, how does it change, such as placing a dummy to fill in the measurement of structural performance. Placing a dummy filling structure may cause unexpected electrical effects. Entering a dummy structure will change the effective pattern density and line spacing. And shifting ^ 钤 ^ (oxidized filling structure) will change the effective pattern density and line spacing. ^ Into

200405184 V. Description of the invention (5) The influence of "" depends on the interconnect structure of the adjacent filling structure (for the metal dummy structure) or the interconnect structure itself (for the oxide dummy structure). Adding metal to fill the structure will change the coupling capacitance (C) of the adjacent interconnects. Adding an oxidized dummy structure will change the value of the coupling capacitance (C) and the interconnect, and the resistance (R). The corresponding effect depends on the size of the interconnect structure. The degree of variation in R and C determines how the circuit is affected. Establish a design rule (Design Ruie) to make the internal connection "variation 2 error to an acceptable level. In addition, the design rule allows circuit performance to be measured, such as signal delay, clock shift, or crosstalk effects. ^ 雠 One error range. This performance measurement parameter is generally a function of the interconnected RC. The overall interconnected capacitance value is almost completely determined by the adjacent structure. This is a standard setting, and the object or object level can be controlled by process variation. $: Convergent settings (such as line width, line spacing, or density) are judged separately before they are normalized. Therefore, in addition to the flatness of the process related to such features, the sex effect will be affected by the strategy of dummy filling. Figures 5 and 6 show the completion of the trench process using ECD and CMP ... Figure q5A shows step 1 'Using lithography and etching on the oxide layer' and:

The f-slot 19 is used as an interconnect structure. Figure 5B shows the step J read. The trench 23 in the field oxide layer 20 is filled by electroplating, which reads: 'Plating layer 21 to time T2 forms an electrical display. Surface 2 ... Step 2 is filled by plating No. A Oxygen diagram: Two time T f groove 27. Figure 6B shows how to use cmp g n and field oxide layer 29. Use CMP to remove copper and planarize the trenches. 28 Due to the copper deposition, all ㈣4 above this area need to be removed.

1057-5667-PF (Nl) .ptd Page 8 200405184 V. Description of the Invention (6) In the semiconductor process, CMP is the mainstream method for removing copper and flattening. I J I Japanese white film, due to different structures and peripherals will lead to different polishing rates. Proof = there will be no short circuit between the wires, over-polishing is needed: the copper above the oxide layer is completely removed. This will cause variations in the thickness of the metal layer. (See Figure 4). Another type of dummy filling structure :: Used to adjust the interconnect structure and surroundings to reduce variation. This can be achieved by filling metal interconnects with dummy structures or removing existing interconnects. Adding extra patterns (metal dummy fills) or removing existing pattern areas (grooves with oxide dummy fills) will change the original design of the layout. Although it can improve the planarization of the process, it affects the electrical properties of the chip. Therefore, retaining the function of the original design circuit and reducing the variability of the process is an important purpose of filling in the layout. In the manufacture of integrated circuits, the interconnection structure is different due to changes in layout patterns (such as material density, line width, and line spacing). The non-flattened south will raise the issue of subsequent process capability and process integration. The independence of the pattern is due to the change in capacitance and resistance caused by the structural position on 70 pieces, which will affect the characteristics of the plastic part. "The fabrication and formation of the lithographic mask is performed on the film with a preset focus to produce projections. However, the second process of IC manufacturing and pattern formation is: pattern dependency usually occurs on the surface of the process film. Significant thickness variations result in variations in the structural dimensions (such as line widths) of integrated circuits (ICs) using patterns of such masks. When non-planar material layers are continuously deposited and ground, the above variation will More serious. This type of change is caused by the interconnection and high-level wires load the power to the chip.

200405184 V. Description of the invention (7) The difference will increase the sheet resistance, which will affect the power efficiency of the chip. The characteristics of variation in thickness and width of the structure due to pattern attachment in the deposition, etching, planarization, and grinding processes can be used to generate a full two-dimensional space model of the circuit structure of each layer in the component. This model can help predict the electrical properties of the interconnect layer. Variations in the thickness and width of the interconnect structure will affect the timing, propagation delay, and power characteristics of the circuit. One of the means to reduce the transmission delay is to use an intermediate buffer (so-called repeater terpe) in a long interconnect wiring. However, because it is difficult to estimate the number and size of buffers required, designers often overuse buffers and increase power consumption. One of the ways to reduce the variation of manufacturing wafers is to perform physical measurement on the original design element, and to use this physical measurement result to adjust the search method 2: How to reduce the variation ☆ Include a verdict and confirm An optical error correction (0pc) method for subwavelength distort 10ns caused by a patterned structure is presented. The characterization of the manufacturing wafer, the variable segment. Measurement refers to Shi Xijing. =: Method of hand-for-transmission measurement: On-line operation is ι method, for example, the three operations of stomach in-si tu) operation is // wafer volume between steps In the same room, wafer measurement is performed to remove the wafer f; and in offline operation, the dimensions are measured in parallel. Means of reducing integrated circuit junction. Measurement is also an important operation when i = material, process and structure can be modified. Process and process can be an important method of yield on the production line. Measure /, the variation of birth to do a better characterization, 1057-5667-PF (Nl) .ptd Page 10, 200405184 V. Description of the invention (8) Further shorten the time to market and reduce production costs During the manufacturing process, whether the process will generate the integrated circuit to be preset. 1 mile or process Physical measurement on wafers, and refers to-Ke refers to the strategy of measuring in products. The measurement strategy includes the needle placement group, the specific pattern on the wafer, or the specific position measurement in the wafer. The measurement between the process steps can be separated from the specific steps and structures of the two-line measurement problem, and then try to diagnose the cause of the problem as soon as possible.忒 At the 20 or 30 process steps, it is necessary to determine the number of steps for selecting a crystal cube from a plurality of crystal cubes on a specific wafer or crystal cube amount. How many steps is required? How to measure from the wafer will delay the subsequent wafer processing, so directly ^ parameters. Excessive rate. Excessive measurement will also make the process engineer: output and process good too much data. The system must be instantaneously divided as shown in Figure 101A. Sometimes the test structure is: In the area outside the wafer circuit on the wafer, it is set to 1 6025 to form ^ 6023. The execution of the measurement is often set in the ^ cutting path or The tangent-insulated test structure 1 6025 is not stubborn to a 75-type structure or device. • 02? 'By avoiding inaccurate commitment ;: Variation = delete the structure of 4 if there are pattern attachments, such as Zong Xu, causing electrical variation, so you must measure the edge = = meeting, such as analogy, logic, I / 0 And ^^ 2 are gathered on a single chip: chip (SGC) 16G24, the above consideration = the mixed system of pieces ~ the more important the Qiaoli will be.

200405184 V. Description of the invention (9) Integrated circuits are manufactured to be physically derived from circuits that are not out of the circuit. Therefore, the use of electrons for the layers is provided on the wafer circuit. Proceeds set the process and design specifications. In addition, it will affect the number of process equipments in each step of this cycle. As for the completion of such experiments in the equipment, the specific experiment equipment «suitable for designing ICs for repeated operations due to multiple process methods is reliable and expensive and expensive Time. The manufacturability and electricity have been set to ten. If the page is completed, the plan can be automatically formed. This device is used until the establishment of the new equipment manufacturing department. It will be trial-produced (and subsequent timing). The manufacturing steps, the chip out basically follow the cycle of design and manufacturing, and the device you want to design. Most of the circuits can be manufactured, and it is not the same as the design or simulation. To build a circuit, you must perform a repetitive process. , EDA software, lithography with lithography technology, and a series of responsible manufacturing steps. After measurement, the electrical classification device that finally characterizes this circuit usually requires several cycles to adjust the design device. The efficiency reaches an acceptable range, and it does not reach the time limit for the calculation-manufacturing cycle that requires expensive labor to place the product on the market. It usually requires experimental design and recipe for each process. Usually experimental design is used to select specific IC devices. Special tool characterization (typically tape-out) and process optimization after performing the aforementioned process steps. Therefore, when measuring the physical and electrical characteristics of the wafer, select the process settings. This will be at some point of each step of the process. Process variation usually leads to no process setting to determine the goal, so no. The possibility of deciding that the manufacturing capacity of a known design will be more manufactured is not purely inferred after the fact. Guides in design rules

l〇57-5667-PF (Nl) .ptd Page 12, 200405184 V. Description of the invention (10) New Sil t ΐ: t jing: and knowledge to prevent such situations in production and manufacturing Jf 1 # ^ = in " However, the new type of device still needs to repeat the design and manufacturing experience gained .... = It is often based on the conventional device and technology to evaluate the follow-up to the complete process flow. C Comprehensive consideration of the step-by-step evaluation method will Organizational or non-linear optimization methods, such as the influence of variation on the number of soldiers, soil, t, and less, are characterized. However, the problem is also beneficial to the problem of nrt! Design, which is based on / adequately accompany the original design rules. The stage frequently estimates the possibility of its production. The process is to achieve reasonable quality; the new ΑΟΤΡ Λ M tz has to be introduced to shorten the crazy field. Advanced circuit design (such as the body circuit (1C) knot: Ϊ 3 :::: ground f cost, 5 new products to maintain the scheduling project to shorten cycle-time ',' However, IC process design will sincerely improve the cycle time and reduce non-recurring Reduce the cost of non-process integration. Process integration is based on the process parts to determine all process flow and individual The process structure of the second office adopts a known or known device structure (⑽tom), or it is different due to the new device using the two models to obtain the process flow and prescription.% 16β〇2 ^ · Ν · It is not a display chart that is ranked from top to bottom, ^ system 16 6 0 2 is designed as a step display, τ inheritance Πββ〇4- ^ ηβ need to describe the lower operating layer in detail). Designers need to let the high-level operation frequency "low-level two people operate one &. Tricky and simulation tools do not require conversion,

200405184 V. Description of Invention (11) (translate) specifications, it is necessary to manage constraints and conflicts in order to comprehensively solve the problem of manufacturing process. In this context, the manufacturing process can be defined as three grinding steps: bulk grinding (bu 丨 k p〇 丨 ish), endpoint testing (pointer), and barrier barrier removal (barrierremval). The process flow can also include all of the etching, lithography, deposition, and polishing steps during IC manufacturing. In this method, synthesis is used to transform the specification from a high-level operation to the next-level operation that meets this specification.

Contents of the Invention: According to an object of the present invention, the present invention provides a method including the following steps: According to an electrical impact analysis of a chemical mechanical polishing process and a pattern attachment model, a dummy filling configuration is generated in the chemical mechanical polishing process. A table strategy; and the use of the pattern attachment model and the electrical impact analysis to evaluate the expected results of placing the dummy fill; the use of the model and the electrical impact analysis is included in the In strategy.

According to another object of the present invention, the present invention provides a method and a method, which include: generating a dummy filling into the stomach with the chemical mechanical polishing process according to an electrical impact analysis and a subsidiary model of the chemical mechanical polishing process; A strategy; and using the pattern attachment model and the electrical impact analysis to evaluate the expected results of placing the dummy fill; the manufacturing process to which the generated strategy is applicable includes manufacturing processes other than a chemical mechanical polishing process. According to another object of the present invention, the present invention provides a method, including

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1057-5667-PF (Nl) .ptd Page 14 200405184 Operation of a servo ′ and a) Develop the virtual machine located at the ambassador can be remotely controlled • Analyze the design should be adjusted; adjust the design parameters. Include two sets of segments included in the single fifth, the description of the invention (12) brackets. According to the strategy of the pattern attached model to generate in a chemical-mechanical mechanical grinding process Applicable according to the present invention: according to a chemical-mechanical mechanical grinding process The pattern attached to the pattern is applicable to the generated strategy. • One of them can be removed, which also includes: a function of a virtual reality, a client (client, where the server is used, which is used, and also included; according to the analysis Adjust and confirm according to the physical and electrical properties that have been set. Among the two steps, one of the two-step mechanical grinding process generates a dummy fill configuration. Evaluate the manufacturing process of putting the dummy fill into another purpose. A diagram of one of the invention's mechanical grinding processes generates a dummy filling configuration to evaluate the manufacturing process of placing the dummy filling into the materials included in the case. A subsidiary model of the project, a strategy in the transformation; and the expected results of the utilization; the institute or more Provides a method, including the subsidiary mold, a strategy for the transformation; and the expected results of the utilization; The flattening process provides a strategy for a semiconductor design. The user can fill in the configuration through a web browser. Near the user. Make the server. Use one of the dummy filling strategies to repeat the analysis. And the adjustment step; manufacturing one integrated circuit conforms to plural or more sets of processes. In a process, there are two or more sets of steps, wherein the two steps and &, .. > Facies deposition. Among them, the strategy of %% generation includes the rules of generating complex arrays of dummy filling.

Page 15 200405184 V. Description of Invention (13). It also includes: defining a group of multiple hierarchical cell placements for dummy filling; and using these hierarchical unit configurations to add dummy filling to reduce the size of an electronic layout file. Among them, a user is A web browser and a web server perform the dummy fill generation operation. The server is located near the user. The user can remotely control the server. ^ The process includes a trench process (damascene process, where the strategy of configuring dummy filling includes determining the size and configuration of the dummy filling. Among them, the manufacturing process includes forming a dielectric interlayer with a low dielectric value ( interlayer) 〇 Wherein, the manufacturing process includes chemical vapor deposition or spin-on dielectric materials with a low dielectric value. The generation of the dummy filling strategy includes dividing a semiconductor design into a plurality of cells. (Grids). Wherein, the generation of the dummy filling strategy includes capturing the density of the area patterns in each of the cells of a semiconductor design. Wherein, the generation of the dummy filling strategy includes capturing each of the semiconductor devices. The line width of the area in the grid. Among them, the generation of the dummy filling strategy includes capturing a semiconductor chip.

1057-5667-PF (Nl) .ptd Page 16 200405184 V. Description of the invention (14) The line spacing in each of the divisions. Among them, the generation of the dummy filling strategy includes calculating an effective pattern density of each cell. Among them, ′ also includes a semiconductor design that uses a complex model to generate a dummy filling strategy, and calculates the non-uniformity of the film thickness. Among them, it also includes calculating the variation in film thickness. It also includes getting the coordinates of all the objects in each grid.

It also includes generating at least one set of line width, pitch, length, and bounding box for each of these objects. Among them, the dummy filling strategy includes dummy filling in the plural empty areas of each of the cells. Wherein, the dummy filling includes a plurality of slots in a plurality of objects, which includes recalculating a region density after adding the dummy filling. Among them, it also includes recalculating a valid pattern density in each grid after adding dummy filling. The dummy filling strategy is based on at least one type of electrical f-parameter variation tolerance in the following rules: capacitance value and resistance value, film I resistance value, output delay, skew, voltage drop, and drive current loss. : Power dissipation, dielectric constant, or crosstalk noise. The effective pattern density is calculated according to a flattening length of a grinding process. Where is based on the elliptical weighting window (e 1 1 i p t i c a 1 1 y

1057-5667-PF (Nl) .ptd Page 17 200405184 V. Description of the invention (15) f wind ° w) or other filters to calculate the effective pattern density, which is' dynamically based on electronic design guidelines% or complex design parameters The rule of generating a complex number of imaginary 5s and filling them varies with technology. Where of which which belong to. Where density. The '-effective pattern density is dynamically flattened with a process. The manufacturing process includes a lithography process. The manufacturing process includes electrochemical deposition. The manufacturing process includes copper chemical mechanical grinding. It also includes extracting multiple patterns from a semiconductor layout with line width, or lines. These layouts include the corresponding line spacing, which also includes: using a patterned conductor device, corresponding to-pre-selection and circle or test plural half. One of the system procedures of the Han Dynasty is very explosive. The strategy is to configure a dummy entry in the prisoner rape process. The accumulation of auxiliary branches to production also includes: the use of a calibrated feature and features: ^ r ^ model to compare the map 、 thickness, film thickness variation, dish: number parameters' such as the final thin Number, such as film resistance value, resistance value, electrical = post-digit electrical parameters. It also includes: according to the pattern, the pattern attached to the pattern generated in the production process, hanging number, and according to 苴 由 介 A k. 丨 ... Name ^ 夏 虚 6 Then fill in the strategy. Configuration virtual in the auxiliary model generation process

1057-5667-PF (Nl) .ptd Page 18 200405184 V. Description of the Invention (16) This strategy is provided; and) is used to evaluate the impact of the process and adjustment at the wafer stage. It also includes a strategy based on the configuration of dummy filling in the combination process. The effect of dummy filling on the process variation. It also includes a strategy of configuring a dummy filling in the combination process. Electrical parameters. φ It also includes the configuration of generating a plurality of dummy filling rules based on the predicted data. These dummy entry rules include these dummy entry rules and management. It also includes: providing multiple access strategies; and using these features to GDS electronic layout files. It also includes: · a plurality of dummy fill-in adjustments for a layout file of a semiconductor device in a network; return to the client as a file. It also includes: · The servo function of a cost function (variation of electrical parameters and the implementation of dummy filling of multiple sets of pattern sub-models generated from one system), and the prediction of the set of pattern sub-models generated according to the strategy. The wafer stage and the simulated wafer stage and electrical parameters are optimized in a process and used in a semiconductor manufacturing process to include dimensions of dummy filling. Configuration including dummy filling. Including dummy filling The formation of the dummy unit of the grading unit is used to generate the dummy unit that automatically adjusts a complex server of a semiconductor device and receives it from a client; the server generates the layout slot and fills the adjusted dummy unit. A service is provided on the server to enable a user

200405184 V. Description of the invention (17) Interactive configuration can be performed with a dummy filling application executed on the server; and the user can use the dummy filling application to generate dummy filling information. It also includes: a user can confirm the dummy input information corresponding to half of the conductor design and a manufacturing process on a network. Among them, the confirmed dummy filling information includes at least one of a dummy filling pattern, a dummy filling strategy, or a dummy filling performance. Among them, the confirmed dummy filling information is a separate interconnect layer corresponding to the semiconductor design. • I Among them, the confirmed filled-in information is a plurality of separate interconnect layers corresponding to the semiconductor design. Among them, it also includes comparing the dimensions of a plurality of dummy fill-in targets, and a dummy or fill-in pattern of one of the targets is generated for a single or multiple interconnect layer of the semiconductor design. The dummy filling information includes a plurality of dummy filling rules. Among them, the pattern includes plural oxidation or metal dummy filling in the target. Among them, the target systems of the dummy fill patterns are configured to minimize variations in the thickness of the whole wafer film. Among them, the target system configuration of the dummy filling pattern is to minimize the variation of the full electric power parameter in the complex electrical parameters. Among them, the electrical parameters include at least one of a thin film resistance value, an electrical threshold value, a capacitance value, crosstalk noise, a voltage drop, a driving current loss, a dielectric constant, and an effective dielectric constant. The GDS file is adjusted to improve the level of the semiconductor device.

1057-5667-PF (Nl) .ptd Page 20 200405184 V. Description of the invention (18) Frankness and electrical performance. The manufacturing process includes a trench manufacturing process. It also includes: a user can use a network application with a plurality of network services on a network to confirm the dummy filling information corresponding to a semiconductor design and a manufacturing process. Among them, the dummy filling configuration strategy includes using a plurality of dummy filling targets to improve the structural integrity of a low-dielectric constant dielectric structure. Among them, the dummy filling configuration strategy includes using a plurality of dummy filling standards to maintain or improve the dielectric constant of a dielectric structure having a low dielectric constant. The effective dielectric constant is maintained in all steps of a trench process flow. The dummy filling configuration strategy includes using a plurality of dummy filling targets in a trench manufacturing process to facilitate the integration of a plurality of low-k dielectric materials. It also includes maintaining a database of semiconductor dummy filling information (1 ibrary); linking the database to generate multiple dummy filling configuration specifications; and changing dummy filling information to update the database. It also includes: storing calibration information based on at least one of the following: multiple $ process tools, multiple recipes, and multiple processes; and updating the calibration information to reflect changes in the process tools, the recipes, or the processes. It also includes using the calibration information to generate a dummy filling strategy. The middle tT includes selecting a plurality of process tools, a plurality of formulas, and a plurality of processes from a calibration database of a plurality of dummy filling characteristics. ,

Page 21, 200405184 V. Description of the invention (19) It also includes ... The user can use a single user interface through a user interface to use: single click operation to gain a reward: one of the dummy required for the conductor design is filled in Strategy. Yu Niu also includes: a user can get in the network service-what is needed for semiconductor materials-a dummy filling strategy人 一一 ^^ ^ / 包 包 枯 或 chemical deposition or electrochemical "True strategy, to compensate for the number of patterns attached to a power according to the present invention ~ a μ ^ ^ 附属 The number of steps attached: List-according to-electrochemical ”F: provides a method, including electrical impact analysis and ~ ^; t t mechanical mechanical deposition manufacturing process-strategy; μ use this picture Feng Erli ,: belong to the type to generate a configuration dummy fill in: configuration of The history of false words is filled with 属 and the electrical scene is too loud, evaluate the omitted part according to the present invention, and the electrical impact is divided into C-phase results; and the pattern is attached to the outline part Eight uses the following steps to generate the dummy fill configuration: the invention provides a method of electrical impact analysis and a method of dry deposition or electrochemical mechanical deposition based on a method according to the present invention; and Utilize :, pattern attached models to generate configuration dummy fills Disposing a dummy speech is filled t h subsidiary model pattern with the influence of the electrical analysis' according to the present invention such expected date = ί of the results. 々 抟 The following steps: According to the purpose of the present invention, the present invention provides a method, an electrical impact analysis and manufacturing strategy, chemical deposition or electrochemical mechanical deposition manufacturing, and a strategy; and the use of a pattern attached model to generate a dummy configuration for evaluation. 4 Pattern attached model and the electrical impact analysis', 1057-5667-PF (Nl) .ptd Page 22, 200405184 V. Description of the invention (20) Estimate the expected results that are configured by the dummy filling. It also includes: operating a server to provide a function for generating a dummy fill for a semiconductor design; and a user can develop a strategy for the dummy fill configuration on a client (c 1 ient) via a network browser. . The server is located near the user. The user can remotely control the server. It also includes: analyzing a design to which the dummy filling strategy has been applied; adjusting the design according to the analysis; repeating the analysis and the adjustment steps; and confirming that a integrated circuit manufactured according to the adjusted design conforms to a plurality of preset physics And electrical parameters. The two phases include two or more processes. Among them, the two phases include two or more sets of steps in a single process. The two phases include deposition and chemical vapor deposition. Among them, the generation of this strategy includes the rules of generating complex arrays of dummy filling. 0 sets of plural hierarchical units and you use the big-and-so word server of these great bureau files. It also includes: the definition of dummy filling A configuration (hierarchical cell placements) «Eight-level cell configuration adds dummy filling to reduce one electron. Among them, a user executes the dummy filling generation operation through a web browser. ° Where the server is located in the user's extension. The user can remotely control the server

1057-5667-PF (Nl) .ptd Page 23 200405184 V. Description of the Invention (21) The process includes an electrochemical mechanical deposition process. . Among them, the strategy for the configuration of the dummy filling includes determining the size and configuration of the dummy filling. The manufacturing process includes forming a dielectric interlayer with a low dielectric value. Among them, the manufacturing process includes chemical vapor deposition or spin-on a dielectric material with a low dielectric value. The generation of the dummy filling strategy includes dividing a semiconductor design into a plurality of grids. ^ > φ wherein the generation of the dummy filling strategy includes capturing the density of the area pattern in each of the cells of a semiconductor design. Wherein, the generation of the dummy filling strategy includes capturing a line width of a region in each grid of a semiconductor design. Wherein, the generation of the dummy filling strategy includes retrieving an area line distance in each grid of a semiconductor device. The generation of the dummy filling strategy includes calculating an effective pattern density of each cell. It also includes one of the methods of generating dummy filling using the plural model correspondingly.

2 conductor design, calculate the non-uniformity of the thickness of the film. It also includes calculations of variations in film thickness. It also includes getting the coordinates of all the objects in each grid. It also includes generating at least one set of line width, line spacing, length, and bounding box for each such object.

1057-5667-PF (Nl) .ptd Page 24 200405184 V. Description of the Invention (22) Wherein, the dummy filling strategy includes adding dummy filling to the plural empty areas of each grid. Wherein, the dummy fills a plurality of slots included in the plurality of objects. This includes recalculating a region density after adding a dummy fill. Among them, it also includes recalculating a valid pattern density in each grid after adding dummy filling. Among them, the dummy filling strategy is based on at least one type of electrical parameter variation tolerance in the following rules: capacitance value and resistance value, film surface P resistance value, output delay, skew, voltage drop, drive Current loss, dielectric constant, or crosstalk noise. The effective pattern density is calculated according to a flattening length of a grinding process. Among them, the effective pattern density is calculated according to an elliptical weighted window (e 1 1 i p t i c a 1 1 y we i ght ed w indow) or other wavelet. Among them, the plural dummy filling rules according to the electronic design policy are generated sadly with the technical or plural design parameters. Among them, an effective pattern density changes dynamically with the flattening length of a process. The manufacturing process includes a lithography process. The manufacturing process includes electrochemical deposition. The manufacturing process includes copper chemical mechanical polishing. It also includes extracting a plurality of pattern attachments from a semiconductor layout.

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Among them, these layout attachments include corresponding line spacing, line width, or line density. It also includes: using a patterned test wafer or testing a plurality of semiconductor devices, corresponding to a preselected tool or process recipe to calibrate a pattern auxiliary model; and generating dummy fills in the production process according to a pattern auxiliary model of a semiconductor process Into the strategy. It also includes: using a calibrated pattern accessory model to compare pattern accessory features (f e a t u r e s) with multiple wafer stage parameters, such as final film thickness, film thickness variation, dishing, erosion, and multiple electrical parameters

Such as film resistance value, resistance value, capacitance value, crosstalk noise, voltage drop, driving current loss, dielectric constant, and effective dielectric constant; and the strategy of dummy filling in the production process according to the attached model of the pattern. It also includes the strategy of placing dummy fills in the production process based on the attached model of the pattern; and the use of a cost function to evaluate process and electrical parameter variations at the wafer stage and perform dummy fill adjustments Influence.

It also includes: a strategy for configuring a dummy fill to be generated in a process based on a combination of multiple patterns of auxiliary models; and predicting the impact of the dummy fill generated on the strategy on process variation. • It also includes a strategy of arranging dummy filling in a process based on combining multiple sets of pattern auxiliary models to optimize the wafer stage and electrical parameters of the overall wafer. It also includes generating dummy filling rules based on predicted or simulated wafer stages and electrical parameters, and used in a semiconductor manufacturing process.

1057-5667-PF (Nl) .ptd Page 26 200405184 V. Description of the invention (24) The configuration of dummy filling. Among them, these dummy filling rules include the size of dummy filling. Among them, the 4 dummy filling rules include the configuration of dummy filling. Among them, these dummy filling rules include the formation and management of dummy filling grade units. 'It also includes: providing a plurality of dummy filling functions to generate the dummy filling strategy; and using these functions to automatically adjust a plurality of GDS electronic layout files of a semiconductor device. It also includes: receiving a layout file transmitted from a client to a private semiconductor device on a network server; generating a plurality of dummy filling of the layout file in the server; and filling the adjusted dummy filling The imported layout file is returned to the client. It also includes: providing a service on the server so that a user can perform a vertical configuration with a dummy fill application running on the server; and the user can use the dummy fill The input application generates dummy filling information. The server includes a network server. The user is located at a location remotely controlling the web server. It also includes: a user can confirm the dummy entry information corresponding to half of the design and a manufacturing process on a network. Among them, the confirmed dummy filling information includes at least one of a dummy filling pattern, a dummy filling strategy, or a dummy filling performance. Among them, the confirmed dummy filling information is a separate interconnect layer corresponding to the semiconductor design.

1057-5667-PF (Nl) .ptd Page 27 200405184 V. Description of the Invention (25) Among them, the confirmed dummy filling information is a plurality of separate interconnect layers corresponding to the semiconductor design. _ It also includes comparing the size of a plurality of dummy fill-in targets' and generating a dummy fill pattern for one or more of the targets for a single or multiple interconnect layer designed for the semiconductor. The dummy filling information includes a plurality of dummy filling rules. Among them, the pattern includes plural oxidation or metal dummy filling in the target. Among them, the target systems of the dummy fill patterns are configured to minimize variations in the thickness of the whole wafer film.

φ Among them, the target system configuration of the dummy filling pattern is to minimize the variation of the whole chip in complex electrical parameters. The electrical parameters include at least one of a thin film resistance value, a resistance value, a capacitance value, crosstalk noise, a voltage drop, a driving current loss, a dielectric constant, and an effective dielectric constant. The GDS file is adjusted to improve the flatness and electrical performance of the semiconductor device. Among them, the process includes a trench process.

It also includes: a user can use a network with multiple network services 4 :: net application to confirm the correspondence-semiconductor design and-manufacturing process% self-filled information. Where ‘the network is an internal network, an external network, or the Internet

1057-5667-PF (Nl) .ptd Page 28, 200405184 V. Description of the invention (26) (structure integrity) ° Wherein, the dummy filling configuration strategy includes using a plurality of dummy filling to maintain or improve the dielectric with a low dielectric constant. The dielectric constant of the electrical structure is only 5%, and the dielectric constant is maintained at all steps in a trench manufacturing process. To another, the dummy fill configuration strategy includes the use of a dummy dummy fill in the target to facilitate the complex low dielectric constant dielectric. "Integrity. It also includes: maintaining a semiconductor dummy fill 1 ibrary); linking the database and using it to generate multiple dummy filling configuration specifications; and changing the dummy filling information to update the database. It also includes storing according to at least one of the following: Calibration information: copy process tools, multiple recipes, and multiple processes; and update the calibration message to reflect the process tools ^ the recipes, or changes to the processes ^ including the use of the calibration information to generate a dummy fill Strategies. ° It also includes the selection of multiple process tools, multiple recipes, and multiple households in the calibration database based on the desired number of dummy fill-in characteristics; the bucket also includes user-accessible- No. — I user interface, obtained with a single click operation — a dummy filling strategy required for gastric body design. According to another object of the present invention The present invention provides a method including the following steps: generating a dummy fill-in strategy in the process according to an electrical analysis of a manufacturing process flow including one or more steps and a pattern attachment model; and using the Pattern attachment model and the electrical impact analysis

1057-5667-PF (Nl) .ptd Page 29, 200405184 V. Description of the Invention (27)-Estimate the expected result of putting the dummy fill in; estimate the use of the model and the electrical impact analysis are included in generating the dummy Fill in the configured policy. According to another object of the present invention, the present invention provides a method, which includes: = 1 step. According to the electric shadow of the manufacturing process flow including one or more steps, the auxiliary model of the pattern is generated in the manufacturing process. The dummy filling configuration 1 is omitted, and the expected result filled in by the manufacturing facility using the pattern auxiliary model and the electrical impact analysis is filled in; the process of the produced 4 strategy includes manufacturing other than the chemical mechanical polishing process Another object of the present invention is to provide a method for forming a package: a pattern auxiliary mold in a 1C manufacturing process, a pattern auxiliary mold === 1% true = of-strategy; and using a basket of health Set the expected result filled in by Haixu; the produced package has a manufacturing stage. Model, in the "manufacturing process of the manufacturing process-the pattern attached mold model to evaluate the dummy filling: two :; and = sheng zhi luo suo nan tian" also Μ 〈top results, the wu dance Removable-a material that includes a grinding or planarization process 'inside M. The virtual operation of a server' provides a client for semiconductor design (c), and a user can ^^^ through a web browser to develop the strategy of the dummy filling configuration. The server is located near the user. 1057-5667-PF (Nl) .ptd Page 30 200405184 V. Description of the invention ( 28) Among them, the user can remotely control the server. It also includes: analyzing that one of the dummy filling strategies has been applied μ ^ · adjusting the design based on the analysis; repeating the analysis and the adjustment steps to confirm the basis The physical and t-parameters of the integrated circuit manufactured by the adjusted design are included. The complex number is preset, and the two stages include two or more processes. Among them, the two stages include the Two or more groups + steps in a single process. Among them, the two stages include deposition and chemical vapor deposition. Then the allocation of small instructions, the production of the long-distance strategy includes generating complex arrays of dummy filling rules, which also includes complex division of virtual addresses for dummy filling. cell placements); and dummy cell configuration to add dummy filling to reduce the number of electronic layout rights = temple 0 where,-the user generates the dummy filling operation through a web browser and the service. ° ° Where, The server is located near the user. _ Where & where the size and configuration (interlayer «the user can remotely control the server. The process includes an electrochemical mechanical deposition process ... the configuration is filled in by default Strategies include determining the dummy fill rule. The manufacturing process includes forming a dielectric interlayer with a low dielectric value.

200405184 V. Description of the invention (29) Wherein, the manufacturing process includes chemical vapor deposition or spin-on dielectric material with low dielectric value. Wherein, the generation of the dummy filling strategy includes dividing a semiconductor design into a plurality of cells (g r i d s). Among them, the generation of the dummy filling strategy includes capturing the density of the area pattern in each of the cells of a semiconductor design. Wherein, the generation of the dummy filling strategy includes capturing a line width of a region in each grid of a semiconductor design. Wherein, the generation of the dummy filling strategy includes extracting a region line spacing in each grid of a semiconductor design. Among them, the generation of the dummy filling strategy includes calculating the effective pattern density of each grid. The degree of the dummy filling strategy also includes the use of a complex model to generate a semiconductor design and calculate the non-uniform thickness of the film thickness. This also includes calculating the variation in film thickness.

Box) 〇 Multiple empty spaces of the grids This also includes obtaining the coordinates of all objects in each grid. It also includes generating at least a set of line width, line spacing, length, and bounding for each of these objects. The dummy filling strategy includes adding dummy filling to each (empty areas). Among them, the dummy Filling the plurality of slots included in the plurality of objects 0, which includes recalculating a region density after adding dummy filling.

1057-5667-PF (Nl) .ptd Page 32 200405184 V. Description of the Invention (30) It also includes recalculating a valid pattern density in each grid after adding dummy filling. Among them, the dummy filling strategy is based on at least one type of electrical parameter variation tolerance (t ο 1 erance) in the following rules: • capacitance value and resistance value, film resistance value, output delay, skew, voltage drop, Drive current loss, dielectric constant, or crosstalk noise. The effective pattern density is calculated according to a flattening length of a grinding process. Among them, the effective pattern density is calculated according to an elliptically plane ighted window or other filters. 々 少 ί ^ According to the electronic design guidelines, the plural dummy filling rules are dynamically generated according to the technology or the number of parameters. = Medium The effective pattern density changes dynamically with the flattening length of a process. The manufacturing process includes a lithography process. ίΐ ′: The manufacturing process of Hai includes electrochemical deposition. The manufacturing process includes copper chemical mechanical grinding. make. ', Also includes extracting a plurality of patterns from a semiconductor layout including' these layout attachments include corresponding line spacing, 'line width, or lines using a patterned test wafer or test plural half corresponding to a pre-selected tool or process recipe To calibrate a picture

It also includes methods of conducting devices

200405184 V. Description of the invention (31) Affiliated model; and the strategy of configuring dummy filling in the production process according to a pattern auxiliary model of a semiconductor process. It also includes: using a calibrated pattern satellite model to compare pattern features with multiple wafer stage parameters, such as final film thickness, film thickness variation, dishing, erosion, and multiple electrical parameters, such as film Resistance value, resistance value, capacitance value, crosstalk noise, voltage drop, drive current loss, dielectric constant, and effective dielectric constant; and the strategy of generating dummy filling in the manufacturing process according to the attached model of the pattern. It also includes: the strategy of generating dummy and filling in the process according to the pattern auxiliary model generation; and using a cost function (cost functi ο η) to evaluate the process and electrical parameter variation at the wafer stage and perform dummy filling adjustment The impact. It also includes: a strategy for configuring a dummy fill to be generated in a process based on a combination of multiple patterns of auxiliary models; and predicting the impact of the dummy fill generated on the strategy on process variation. It also includes a strategy of arranging dummy fills in a process based on combining multiple sets of pattern attachment models to optimize the wafer stage and electrical parameters of the overall wafer. This also includes generating dummy fill rules based on predicted or simulated wafer stages and electrical parameters, and used in a dummy fill configuration in a semiconductor manufacturing process. Among them, these dummy filling rules include the size of dummy filling. Among them, these dummy filling rules include the configuration of dummy filling. Among them, these dummy filling rules include the form of dummy filling in the classification unit.

1057-5667-PF (Nl) .ptd Page 34 200405184 V. Description of Invention (32) Formation and Management. -This also includes providing a plurality of dummy fill-in strategies; and using these functions & a to generate the dummy fill-in GDS electronic layout file. Local adjustment of a semiconductor device also includes: a layout file of a semiconductor device in an Internet feed; two dummy input filling adjustments received from a client to the case; and; the server generates the layout file The file is returned to the client. μ Adjusting the layout of dummy filling 2: It also includes: providing on the server to enable a user interface to interact with a dummy filling application running on the server for configure (configure); and the use of The person can use the dummy filling application to generate dummy filling information. It also includes: a user can confirm the dummy input information corresponding to half of the conductor design and a manufacturing process on a network. Among them, the confirmed dummy filling information includes at least one of a dummy filling pattern, a dummy filling strategy, or a dummy filling performance. Among them, the confirmed filled-in information is a separate interconnect layer corresponding to the design of the rate conductor. Among them, the confirmed filled-in information is a separate interconnect layer corresponding to the number of semiconductor designs. ，， 本本 It also includes comparing the size of a plurality of dummy fill-in targets 'to a single or multiple interconnected layer of a 2 semiconductor design to generate one of these targets' dummy fill-in patterns. Among them, the dummy filling information includes plural dummy filling rules °

I side

1057-5667-PF (Nl) .ptd Page 35 200405184 V. Description of the Invention (33) Wherein the 戎 pattern includes complex oxidation or metal dummy filling structure. Among them, the variation of the thickness of the configured full wafer film of the dummy fill pattern. Ning, Peili Among them, the target system configuration of the dummy filling pattern is to minimize the variation of the whole chip in complex electrical parameters. Among them, the electrical parameters include at least one of a thin-m value, a capacitance value, a crosstalk noise, a voltage drop, a driving current loss, a constant, a wide, and an effective dielectric constant. # Where ‘the GDS slot is adjusted for m-level and electrical performance. Thousands of guide bottles 'where' the network is an internal network, an external network, or η where the process includes the trench process flow Internet users also includes: providing a server on the server Using 々 can interact with < perform a dummy fill application ^ configure on the temple server, and the user can apply to generate dummy fill information. Use 4 virtual. I also fill in the change I I: :: The configuration strategy includes the use of a plurality of dummy filling standards, and the structural integrity of the structure is included, and the maintenance or improvement of the configuration strategy is low. Dielectric constant; of; =: =; Fill in the standard, all the hanging numbers in the -trench process. Electrical constant. To maintain the effective medium

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Among them, the dummy filling configuration strategy includes using a plurality of dummy filling targets in a trench process to facilitate the integration of complex low dielectric constant dielectric edges. What's in it is to set the specifications; it also uses the process tools and information to reflect the ^ which is also selected from the library, which is also the user interface conductor design institute, and also the strategy to obtain half life. Based on this column Steps: The auxiliary model of the dielectric interlayer case is based on the following steps: Including: maintaining a semiconductor dummy fill information; linking the database and generating multiple dummy fills and changing dummy fill information to update the database- It includes: storing calibration information according to at least one of the following; multiple recipes and multiple processes; and updating process tools such as the school ^, these recipes, or changes to these processes, including using the calibration information to generate a dummy filling strategy … Including calibration tools, plural recipes, and plural processes based on the desired number of dummy fill-in characteristics: 'Dagger: A user can use a user interface device — two uses and one click (si ng 1 ecii ck) operation to obtain a dummy fill strategy required by the bucket. H: a user can use on the network Network Services :: a dummy filling strategy required for the design; and the manufacturing process used for the production includes one or more manufacturing stages. Another purpose of f 'is that the present invention provides a method, including a drawer? Prediction is used when mechanically or chemically vapor-depositing a low dielectric constant, or when coating a low dielectric constant between dielectric layers. :: Another aspect, the present invention provides a method that includes a chemical mechanical polishing process Electrical impact analysis and first

200405184 V. Description of the invention (35) A pattern auxiliary model, a strategy for generating a dummy filling configuration in a semiconductor manufacturing process, and the use of a tritium pattern auxiliary model and the electrical impact analysis to evaluate the expected result of placing the dummy filling The use of the model and the electrical impact analysis is included in the strategy of generating dummy fill configurations. According to another object of the present invention, the present invention provides a method including the following steps: according to the electrical influence of a chemical mechanical polishing process, dividing a pattern auxiliary model, and generating a strategy for a dummy match in a semiconductor manufacturing process, And the use of the auxiliary model of the pattern and the electric shadowing 沬 估 I estimate the expected result of the dummy filling; the resulting strategy: the manufacturing process includes the oxidation chemical mechanical polishing process, and & Use. According to another object of the present invention, the present invention provides a method, the following steps: according to a pattern attached to a chemical mechanical polishing process, including a strategy to generate a dummy filling configuration in a semiconductor manufacturing process. The pattern auxiliary model is used to evaluate the placement of the dummy-filled box such as 'and the manufacturing process applicable to the generated strategy includes one or more results'. Table k Stages, where each stage includes a process recipe. Among them, each stage includes a process type. Among them, each stage includes a process flow. According to another object of the present invention, the present invention provides a method according to one of the following steps: a pattern attached according to a chemical mechanical polishing process is included in a semiconductor manufacturing process to generate a dummy filling configuration, a flute fruit type; and%; and

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200405184 V. Description of the invention (36) Use the attached model of the pattern to apply the generated strategy. Among them, one of the following steps can be removed, which also includes a plurality of electricity. According to the invention, the following other steps: operate a servo dummy fill in A web browser, its lithography, its roots, the following steps, the design of the design, the steps of the design are in accordance with it, which, the middle, the one: electrochemistry, the middle, the data according to the present Steps: use a benefit; root; and several presets, the middle, the function; in order to use the server, the user can specifically set up $ Chemical machine 娀 deposition, use the default setting 嗔 netting to specify other ~ Fill in the material in the manufacturing process based on the analysis and confirmation of the physical and two-stage package and two-stage package based on the analysis with a drawing. Sex analysis. The purpose of the device is to provide a grinding or periodical result that a user can fill in the dummy; a flattened netting dummy is filled in at the remote end of the user to control the configuration function of deposition, chemistry and chemical machinery In-configuration function In-configuration function purpose, the attached model of the hair distribution strategy; analysis and adjustment of the strategy should be adjusted electrical parameters. Including two groups or more in a single specification provides a method that includes counting the number of operations by a user. The server uses vapour precipitation. The application is provided by the application of the analysis of a product has been applied, repeat the calculation of at least the product, coating the following process layout process, isolation in shallow trenches. For oxidizing the dielectric layer. A method includes the design of a body circuit; the dummy filling strategy is analyzed and adjusted to reproduce one integrated circuit in multiple sets of processes. Two or more steps in the process

200405184 V. Description of the invention (37) Wherein, the two stages include two or more steps in a single process type, where the two stages include two or more steps in a process flow, where the two stages include In the deposition and transformation, the generation of the strategy includes another purpose of generation. The present invention uses a dummy fill to cel 1 placements to reduce the amount of electricity generated by a user through a network. The server is located at the user. The user can remotely control the generation of the filling system. The strategy includes a pad of a chemical machine. Once the execution is performed, the dummy is filled in, the server is served, and the service is provided. Among them, the system Among them, the allocation configuration. Among them, the interlayer system is a meteorological deposit. The specification of dummy array filling provides a method, including grouping multiple hierarchical unit configurations; and using the size of these hierarchical sub-layout files. The drama browser and an online temple are nearby. server. A web deposition process provided on a server. Including determining the dummy fill rule. The manufacturing process includes forming a dielectric interlayer with a low dielectric value. ‘The manufacturing process includes chemical vapor deposition or spin-on a dielectric material with a low dielectric value.

1057-5667-PF (Nl) .ptd Page 40 200405184 V. Description of the Invention (38) Wherein, the generation of the dummy filling strategy includes dividing a semiconductor design into a plurality of cells (gr i ds). Among them, the generation of the dummy filling strategy includes capturing the density of the area pattern in each of the cells of a semiconductor design. Wherein, the generation of the dummy filling strategy includes capturing a line width of a region in each grid of a semiconductor design. Wherein, the generation of the dummy filling strategy includes extracting a region line spacing in each grid of a semiconductor design. Wherein, the generation of the dummy filling strategy includes calculating a pattern density of g in each grid. It also includes the use of a complex model to generate one of the dummy filling strategies for semiconductor design, and calculate the non-uniformity of the film thickness. Non-uniformity of the film thickness is also calculated. This also includes calculating the variation in film thickness. It also includes getting the coordinates of all the objects in each grid. It also includes generating at least a set of line widths, line spacings, lengths, and bounding boxes for objects such as a mother and a child. The dummy fill strategy includes adding dummy fills to a plurality of empty areas in each grid. ® Wherein, the dummy filling includes a plurality of slots in a plurality of objects. This includes recalculating a region density after adding the dummy filling. It also includes recalculating a valid pattern density in each of these cells after adding dummy fills.

1057-5667-PF (Nl) .ptd Page 41 200405184 V. Description of the invention (39) Wherein, the dummy filling strategy is based on at least one type of electrical parameter variation tolerance in the following rules: capacitance value and resistance value , Film resistance, output delay, skew, voltage drop, drive current loss, dielectric constant, or crosstalk noise. The effective pattern density is calculated according to a flattening length of a grinding process. Wherein, the effective pattern density is calculated according to an elliptically weighted window or other filters. 0

The non-flatness of a film thickness is determined according to the physical parameters of the pole number. Among them, these physical parameters include density, line width, and / or line spacing of 0. This also includes using the dummy filling strategy to reduce the variation of electroplated copper deposition before or after chemical machinery. Wherein, the dummy filling strategy is completed automatically. The two dummy filling rules according to the electronic design policy are dynamically generated with the technical or plural digimeter parameters. _ Among them, the effective pattern and degree are dynamically changed with the flattening length of a process. Furthermore, 'the manufacturing process includes a lithography process. Among them, the manufacturing process includes electrochemical deposition. The manufacturing process includes chemical mechanical grinding of steel. The manufacturing process includes electrochemical mechanical deposition.

1〇57-5667-PF (N1) * Ptd Page 42 200405184 Description of the Invention (40) The manufacturing process includes a dielectric material with a low dielectric constant. The manufacturing process includes a low-k dielectric material process. It also includes extracting a plurality of pattern attachments from a semiconductor layout. Among them, these layout accessories include corresponding line spacing, line width, or line density. According to another object of the present invention, the present invention provides a method comprising the steps of: using a patterned test wafer or a method of testing a plurality of semiconductor devices, corresponding to a pre-selected tool or process recipe to calibrate a pattern accessory model; and The strategy for generating dummy fills in the process is generated according to a pattern auxiliary model of a semiconductor process. ^ According to another object of the present invention, the present invention provides a method including the following steps: using at least one of the following processes to generate a plurality of auxiliary wafer pattern auxiliary models: electrochemical deposition, electrochemical mechanical deposition, copper chemical mechanical polishing, lithography, Shallow trench insulation chemical mechanical polishing, chemical vapor deposition of a low dielectric constant dielectric layer, and spin-coating of a low dielectric constant dielectric layer; and the strategy of configuring dummy filling in the production process according to the attached model of the pattern. According to another object of the present invention, the present invention provides a method including the following steps: using a calibrated pattern accessory model to compare pattern features with multiple wafer stage parameters, such as final film thickness ^, film thickness Variation, dishing, erosion, and complex electrical parameters such as gastric membrane resistance, resistance, capacitance, crosstalk noise, voltage drop, drive current loss, dielectric constant, and effective dielectric constant; and according to the pattern The strategy is configured by filling in dummy models in the auxiliary model generation process. According to another object of the present invention, the present invention provides a method including the following steps: according to the pattern auxiliary model generating process, a dummy filling is configured in the manufacturing process.

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5. The strategy of the invention description (41); and the use of a cost function to evaluate the impact of the dummy filling adjustments on the variation of the process and electrical parameters at the wafer stage. According to another object of the present invention, the present invention provides a method comprising the steps of: configuring a strategy of dummy filling in a process according to a combination of a plurality of pattern sub-models generated; and predicting the virtual $ generated according to the strategy. Fill in the impact on process variation. According to another object of the present invention, the present invention provides a method including the following steps: optimizing the wafer stage of the overall wafer according to a strategy of generating and filling in a process according to a combination of multiple sets of pattern attachment models generated in a process And electrical 丨 _ parameters. According to another object of the present invention, the present invention provides a method including the following steps: According to predicted or simulated wafer stages and electrical parameters, a plurality of dummy filling rules are generated and used for a dummy filling in a semiconductor manufacturing process. Its configuration. , Where 'these dummy filling rules include the dimensions of the dummy filling. Among them, these dummy filling rules include the configuration of dummy filling. Among them, these dummy filling rules include the management and management of filling dummy units. '

According to another object of the present invention, the present invention provides a method including: a set of steps and steps: providing a plurality of dummy filling functions to generate the dummy filling policy, and automatically adjusting the complex number of a semiconductor device by using these functions GDS electronic layout file. According to another object of the present invention, the present invention provides a method, including

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V. Description of the invention (42) The following steps: Receive a layout file from ^ ^ ^, one of the conductor devices on a network server; fill in half of the layout slots generated by the server with dummy settings; Adjusted the dummy filled cloths and slots $ Back to the client 〃 The server and the client are connected via the Internet. The server and the client are connected via an external network. Yun

The server and the client are connected using an internal network. Among them, the server and the client are connected using a virtual private network (VPN). Wherein, the server and the client use a secure she 11 (SSH) security communication protocol. ^ The server and the client use a secure socket layer (SSL) security protocol. The server and the client use a virtual private network (vpn) security communication protocol. According to another object of the present invention, the present invention provides a method, the following steps: providing a service on the server, so that a user can:

^ A dummy fill application running on the server is used for interactive setup "" configure); and the user can benefit

Fill in the information. Dan Ba applied J f: The user is located in accordance with another object of the present invention, the present invention provides a method Step: A user can confirm at ^ 7 A including the following

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V. Description of the invention (43) The dummy filling information of the manufacturing process. Accompanied by filling in, the confirmed dummy filling information includes at least ^. Among the patterns, a dummy filling strategy, or a dummy filling performance representing its minus clock, among them, the confirmed dummy filling information corresponds to a semi-V body to form a separate interconnecting layer. Among them, the confirmed dummy filling information is a plurality of separate interconnect layers corresponding to the semiconductor design. It also includes comparing the dimensions of a plurality of dummy filling in the target, and generating a dummy filling of one of the targets for a single or multiple interconnecting layer designed for the semiconductor.

| Pattern. The dummy filling information includes a plurality of dummy filling rules. Among them, the pattern includes plural oxidation or metal dummy filling in the target. Among them, the target system of the dummy filling pattern is configured to optimize the variation of the thickness of the whole wafer film. Mi Among these, the target system configuration of the dummy filling pattern is the variation of the chip in a plurality of electrical parameters. Lai: Xiaohuayu Among them, these electrical parameters include at least one of the thin film resistance “capacitance value, crosstalk noise, voltage drop, drive current loss, eight resistance value, and effective dielectric constant.

_ Among them, the GDS file is adjusted to improve the natural and electrical performance. The name of the body is the same as that of the low-dielectric constant improvement of the stringent process including the trench process: = dummy fill in the standard

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200405184 V. Description of the invention (44) (structure integrity) 〇 The dummy filling configuration strategy includes using a plurality of dummy filling targets to maintain or improve the dielectric constant of a dielectric structure with a low dielectric constant. The effective dielectric constant is maintained in all steps of a trench process flow. The dummy filling configuration strategy includes using a plurality of dummy filling targets in a trench manufacturing process to facilitate the integration of a plurality of low-k dielectric materials.

According to another object of the present invention, the present invention provides a medium that can load an I message and configure a device so that a user can search for and obtain a plurality of dummy size information included in a dummy semiconductor device design included in a plurality of semiconductor device designs. According to another object of the present invention, the present invention provides a medium capable of loading information, and a device is set up so that a user can search and obtain plural database information contained in plural dummy filling targets or patterns. According to another object of the present invention, the present invention provides a medium that can load > and set a device so that a user can search for a brother and obtain plural database information contained in plural dummy filling rules. .

According to another object of the present invention, the present invention provides a method comprising two rows of steps: maintaining a database of semiconductor dummy filling information, 1 ibrary); linking the database and generating a plurality of dummy filling configuration specifications; and changing Fill in the information to update the database. According to another object of the present invention, the present invention provides a method comprising the steps of: storing calibration information according to at least one of the following: a plurality of process tools, a plurality of recipes, and a plurality of processes; and updating the calibration information to reflect

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ZUU4UM84 V. Description of the invention (45) It should wait for the process tools, which also includes brakes or squares, or changes in these processes. It also includes j: the? The quasi-information generates a dummy filling strategy. According to the present invention, ‘two = tools, multiple formulas, and multiple processes are selected from the library. The following steps: a method using the present invention, the present invention provides a method, including an interface, using-click °. Through ~ a user interface device one of the user's device needs a dummy fill into the click) operation to obtain a semiconductor device which , 5 Hai process includes ditch Zen. It also includes: a Mascene process to obtain a semiconductor design can = use a plurality of network services on the network according to another of the present invention :; a dummy filling strategy. The following steps: Characterize the 1-body circuit and provide a method 'including a process in the integrated circuit = a variation in the dimensions of the element, one of the topographical (t0p〇graphical) variations produced by Genbei Ping. Among them, the topological pattern variation is produced. Chemical mechanical grinding. M, N or L include electroplated copper deposition or or where the process includes a lithography or etching process. P_ The electrical pattern variation affects each other to produce a complex number: "The process and the extension. 'The etching process includes a plasma etching process According to another object of the present invention, the present invention follows the following steps: A method using topology pattern change, including an attached model of the complex element size change of an integrated circuit, to predict ... the complex electrical characteristics, The integration

1057-5667-PF (Nl) .ptd P.48 200405184 The components of topological variable presetting are different ~ Topological patterns for the purpose · Multiple components & Components containing lithographic or etch presets Features such as deep grooves, deep grooves, and the like include the manufacturing process including the electrical process including the manufacturing process. The features include equal features, phase changes, the forecast changes, the forecast changes, and the forecasts. Designed to be manufactured; features to fit the design. A method is provided, which includes a pattern attachment model, predicting a number of electrical characteristics, and one of the products is designed and manufactured; the characteristics are in accordance with the design; and the sexual characteristics. These features include sidewall angles. Sign. «Body circuit. Within the body circuit. Variable component width. Change the topological mutation. Variation due to changes in size and width V. Description of the invention (46) The circuit is based on the production and the following steps are changed according to this issue: the circuit of the Liyi integrated circuit is based on the package and the special features are changed, including the _ | Trench width, among which, among which, among which, among them, change the complex physical and electrical parameters. Among them, the prediction is based on the response from a network (response), which is based on a network service or a different process size or The electrical characteristics of the present invention are one inch variation or one process size or electrical inch or multiple plasma remaining moments. Multiple element rule, multiple electrical characteristics, copper plating deposition. Mechanical grinding element width. About all products About all products Features include changes and also features include changes to receive or respond to a request electrically. To provide the forecast or the change.

1057-5667-PF (Nl) .ptd Page 49 200405184 V. Description of the Invention (47) One of the variations of the pattern attached model, which predicts the steps of variation or complex electrical characteristics. Including plural process recipes. Including different tool settings for a tool. Including multiple power settings. Including plural etching times. Including multiple grinding times. Including plural deposition times. Include plural pressures. Include plural tools. Among them, which are mentioned by different vendors, among which among which among which «Among them, the size of a plurality of components using a topological pattern of an integrated circuit includes according to at least two different manufacturing processes. Among them, the manufacturing characteristics include Other process recipes, process recipes, process recipes, 5 process recipes, special process recipes, process feature packages, and tools are made up of two consumables. Multiple photoresistor or multiple photomask types. Measured in these process characteristics. As a service in a network. The external network, an external network, or a network, among which the process feature package includes the consumables, which also includes according to the pre-characterization, the characterization step is in which the network includes an internal, g Network 'and the characterization is provided according to a plurality of user's requests ^ 2') also includes an electronic design automation combined with the characterization step According to another object of the present invention, the present invention provides a method, including: Step: Use the -pattern attached model to predict the size variation of an integrated circuit. The integrated circuit is based on the

〇57-5667-PF (Nl) .ptd Page 50 200405184 V. Description of the invention (48) Topological change of the body circuit _ production process is one of the processes and is designed and manufactured. The process includes electroplated copper deposition (ECD). The process includes chemical mechanical polishing (CMP). The predicted variation of these models in the element size of Bazhong is due to the interaction between this process step and a lithography or etching process (int ^ actioon). The characterization step is a service in a network. The network includes an internal network, an external network, or an Internet 'and the characterization is provided according to a plurality of user requests. ^ It also includes an electronic design automation (EDA) in combination with this characterization step. According to another object of the present invention, the present invention provides a method, which includes the following; / The use of a pattern attachment model to predict the dimensional characteristics of a plurality of integrated circuits of a one-level integrated circuit, the integrated circuit is made based on design And make sure that these predicted component dimensional characteristics meet the requirements of the design. It also includes adding a circuit element after predicting the size characteristics of the components, the = Ya, and, after adding the component to the design, confirming that the preset component size characteristics meet the design specifications. Among these features include component width. Among them, the prediction and confirmation are provided by a network service. The " Hai network includes an internal network, an external network, or an Internet, and the prediction and confirmation are provided based on a plurality of user requests. It also includes an electronic design combined with this prediction and confirmation step Ιϋ ^ ΙΙ Μιpage 51 1057-5667-PF (Nl) .ptd 200405184 V. Description of the invention (49)

Automation (EDA According to the date and month of this issue _ the following steps: Lee: j: ", the present invention provides a method, including: _ Ji_ $ a pattern attached model predicts one of the topological changes of a complex circuit of an integrated circuit 4 Based on (a) one of the processes of lmpart, sine product, or etching process, and (b) —a design of one of the micro-punch x spears; it is cut to the present month The characteristics of the Rong Box system meet the plural specifications of the design. ^ 'And the following are indeed the predictions of the 5 Haizhuan prediction: 2 books: Another purpose of the invention, the present invention provides a method, including β, two miscellaneous Φ: The pattern attachment model predicts the complex and special changes of an integrated circuit-one of the production processes: to): (= product = = one of the etching processes, and a stand-by, 4 ^ (b) series of lithography or Μ Μ ί ^ ^ «Γ 〇 was made 4 and confirmed that the characteristics of the predictions resulting from the process known by the lithography or etch ^ conform to the plural specification of the design m 3 Another object of the present invention, the present invention Provide a method, including ^ • performing a lithography or etching process on a test wafer; The complex generated by the lithography or ㈣ process: the feature information is used in the auxiliary model of case j. D. One of the clothing manufacturers According to another object of the present invention, the present invention provides a method: using a pattern auxiliary model to predict a Integrated circuit = the relative change in the number of parts & the integrated circuit is ㈣ = ^ lithography or etching tools or consumables of multiple processes-designed and manufactured " & 'and the selection of these processes Manufacturing based on these relative prediction variants

200405184 V. Description of the invention (50) The integrated circuit. Where 'is the prediction provided by a web service. Wherein the network includes an internal network, an external network, or an Internet, and the characterization is provided according to a plurality of user requests. It also includes an electronic design automation (EDA) in combination with this characterization step.

Among them, the lithography process includes MV (deep ultraii〇let), EUV (extremely short UV), or ion projection lithography process (IPL). Among them, the measurement of the size of these components is performed using a scanning electron microscope SM (scanning electron microscopy), scattering measurement and eye-catching seedling probe microscope, Hne edge roughness, or three-dimensional space measurement technology. According to another object of the present invention, the present invention provides a method, It includes the following steps: using a pattern attached model to confirm that a plurality of chip-level components of one of the integrated circuits 1 ^ can be concentrated on a plurality of lithographic tools ^ ° ten to manufacture. Fj plus network services to provide the confirmation which is' system From this, the network includes an internal network, an external network, and a network, and the characterization is provided according to a plurality of user requests. The network also includes one combined with the confirmation step. Electronic external device (EDA) ... 丨 Motion according to another object of the present invention, the present invention provides a method, the following steps: using a pattern attached model to predict a integrated power Road-including

200405184 V. Description of Invention (51) Whether one of the designs can be imaged lithographically based on the design; if not, design or plural process parameters to achieve imaging. ° Among them, the adjustment step includes selecting a plurality of optimal tool settings of a lithography tool, wherein ′ the adjustment step includes selecting a plurality of optimal photoresist materials. The adjusting step includes selecting a plurality of optimal photoresist deposition recipes. The adjusting step includes adjusting a plurality of settings of a tool. Among them, the adjustment step includes adjusting a plurality of power settings. Among them, the adjusting step includes adjusting a plurality of etching times.

% Among them, this adjustment step includes adjusting the multiple grinding time. Among them, the adjusting step includes adjusting a plurality of deposition times. Among them, the adjustment step includes adjusting a plurality of pressures. According to the following steps of this issue: Another application of Li Ming is a pattern sign. The integrated circuit is designed for lithography or surname engraving JiF according to a design change in one of the processes of a production process. The production process is manufactured in accordance with the following steps of the present invention: · When the degree (degree) is manufactured; the micro-prediction feature adjusts the interaction of another lithographer to fail to produce the purpose, the present invention provides a method, the package is attached The model predicts a complex number 4 of an integrated circuit, including (a) the topology of the integrated circuit, and (b)-lithography or post-etching using a photomask produced by the design for speech or etching processes. And the production process] are different from the design; and corresponding to the model's mask, to reduce the effect of the lithography or etching process |. For the purpose, the present invention provides a method for producing a tool without adjusting one of the tools during production.

V. Description of the invention (52) The model predicts the focus limit of a multi-purpose belt. The location of a circuit is in accordance with the mask, so that the material is changed or at least inch obtained from the design. The office tool can generate a suitable component ruler at these positions, where the focus limit includes the depth of focus. The tool includes a lithography stepper. It also includes using an electronic design automation (EDA) tool to combine at least one of the prediction or the decision. I. where ′ is a pattern accessory model that receives at least one of the following as input:

f. The layout or design specifications of the integrated circuit, the lithography tool: the number of complex parameters and the setting of the lithography tool, and the data of the test wafer produced by the lithography tool. Among them, the step of using the pattern auxiliary model includes determining whether an integrated circuit can be manufactured according to the design using the lithography tool. Among them, changing the design or the photomask also produces a suitable electrical property. Among them, the location is in one of the areas of the design, and the lithography tool was not adjusted during production. The design includes a plurality of other integrated circuits, and the lithography tool is adjusted between the plurality of integrated circuits during production to meet the focus limit. However, the design or reticle is changed so that the lithographic tool can produce a suitable component size at these locations. The component size includes a line size, and the component size includes a line pitch. Among them, the size of the element includes

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Page 55 200405184 V. Description of the invention (53) Among them, among the modified components, among them, 〇 Among them, the Internet, and the design size according to the invention. A network or a mask includes changing the design or providing services in the mask to provide the prediction or the change, wherein the network includes the prediction or the modification of a port, a, an internet, an external network, and a variation based on a plural The user requests to mention the second network. The present invention provides a method for performing a position in the package domain—a pattern attached model prediction of a lithography tool with the _light virtual adjustment 'limit of the focal point in the area of the wafer. Does not have a suitable component size. Limitations include a depth-of-field including: a distance from the lithographer and the lithography tool physically in a region of a wafer to meet the focus limit ^. A plurality of portions of an original mask layout are changed to produce the layout as a single integrated circuit. The area of the wafer has less than one of a predetermined size. The distance from the tool is physically adjusted according to a mark on the wafer. Including: perform another step on other plural positions in the area of the wafer. • The photomicrographer can focus on one of the virtual tunes from one wafer away. ^ The layout is due to the fact that it has its own imaging. . Its its inch. The activities in its area are also included in the adjustment, including the middle, and in the middle, the lithography also includes the adjustment. Purpose A whole area, execute one of the pair according to the hood

1057-5667-PF (Nl) .ptd Page 56 200405184 Outside of this area of the wafer, other plural positions are included, including line dimensions. Include line spacing. Including linear density. Purpose, the present invention provides a method, including an auxiliary model predicting a complex topological variation, which can accelerate a predetermined lithographic process step; providing the prediction or the change within the service by using the complex design of the complex reticle in the private step. Network, an external network, or variants depending on the purpose, or Yu Hai | J patterning case attached plural include each including multi-size size a default network V. invention description (54) one which also includes: in the line Virtual adjustment. Wherein, the component size is the component size, the component size is according to another following step of the present invention: using a pattern to occur in a integrated circuit, and adjusting and using it in the lithography βHai topology topology change. . Wherein, it is a network. Wherein, the network includes the Internet, and the prediction or modification is based on another following step of the present invention: utilization-test-wafer; root; Figure g is produced by the shadow or etching process, where the photomask design includes the photomask design and other photomasks including various lines and spaces, and the process includes the last name engraving formula. Provided upon request from multiple users The present invention provides a method including a process of generating a mask design to pattern the wafer to characterize the process; and a root model predicting the complex integrated circuit due to the feature. Class line and spacing dimensions. Multi-level multiple masks, each of these 0 lithography or afterglow tools, or lithography or

IM

〇57-5667-PF (Nl) .ptd Page 57 200405184 V. Description of the invention (55) Among them, among which, among which, among them, the processes are the processes the processes are the processes Including at least one of the steps includes a plurality of preset power settings, a plurality of preset etching times, a plurality of preset grinding times, a plurality of preset deposition times, and a plurality of preset pressures. Generation step, the characterization step, and the prediction step

A combination of electronic design automation (EDA, where the Internet has multiple dimensions of the following steps to the product, and the number of steps is changed into the product by the following steps. In this step, the 'and Among the users, this step is based on: mutation, physical circuit manufacturing; according to this step: the difference, this circuit < the generation step provides a network packet generation step request and is specifically formulated for another use A picture of the product and its impact. Clearly use another picture of the product, a production step, a network step, an internal step, and a supply. The auxiliary circuit is included in the project to determine the product characterization process. The steps and the prediction step are at least a service on the road. The external network, an external network $, or a network characterization step and the prediction; the steps are based on a preset photoresistor. The present invention provides a method comprising: The complex elements of the body voltage, and (a) distributes topological changes, t (b), a lithography or etched body circuit, and the dimensions of these components vary: for the purpose, the present invention provides a method, including = accessory model Advance - Extension of the complex process of integrated circuits, and (b) changes to flutter J etching process or simulated Movies

1057-5667-PF (Nl) .ptd Page 58 200405184 V. Description of the Invention (56) was manufactured; and it determines the influence of one of the electrical properties. It also includes prediction, and determines that the integrated electric-μ θ points are mutated in the complex rule circuit of Cailing Integrated Circuit. The complex rule size of the complex circuit is 1T ^ J. The complex element of the integrated circuit is two One of the effects is the integration of the medium, (the timing of φ, the process of the complex circuit, and the internal circuit of the internal circuit. The% slot structure includes the number of electrons and the number of electrons, and the distribution of these electrical power sources, closure) Also included are changes based on the number of photomasks. It also includes corresponding process capabilities. Corresponding circuit performance is also included. 'Performs the prediction based on the multiple levels of the integrated circuit. The impact of this decision is to determine the dummy fill or plural ^ ^ dynamic current, # including thin film resistor, valley, drive, closed, and considering multiple levels of interconnect analysis ° The design meets the preset specifications. *-List the impact adjustment of the decision for the lithography 5 * The impact of the decision adjust the design to improve the J product, and advance the product ^ The impact of the decision adjust the setting is performed at the interconnect level of one of the circuits The pre-order is based on the configuration. ′ Is based on the impact of the decision to determine the configuration of the replicas in the integrated circuit. ′ Is based on the decision of the influence to determine the loop (routing) of the complex interconnected area between the complexes in the integrated circuit.

200405184 V. Description of the invention (57) Wherein, the integrated circuit includes a system-on-chip (SoC), and the method also includes determining a plurality of internally-connected circuits in the SOC device. . Among them, 'is the geometric structure of the plurality of electronic components, the plurality of interconnections, or the plugs (v i a) in the integrated circuit according to the decision of the influence. It also includes an electronic design (EDA) in combination with this prediction and validation step. . It is called Riel, where at least one of the decision step and the prediction step is provided as a service on the Internet. The steps are%, wherein the network includes an internal network, an external network, or an Internet, and the prediction step or the decision step is provided according to a plurality of user demands. According to another object of the present invention, the present invention provides a formula: a two-pattern attached model predicts a complex topology of an integrated circuit. The integrated circuit is based on one of the integrated circuits including (a) a distribution topology. Production system, αr κ ^, crossover to production, and (b) are produced by a shadow or etching process7, which determines the topological change of the integrated circuit-the impact; and The use of an RC operation (extractor: = g-type and the impact of the decision.… 5. According to another object of the present invention, the present invention provides a method, the following steps: using a pattern attached model to predict an integrated circuit Complex if = different and complex variation of the size of the complex element, the integrated electric = according to U) the topological change of the integrated circuit to one of the integrated circuits. The production system is based on X and (b) secret or surname engraving process. Manufacture; determine the integrated circuit

I Page 60 1057-5667-PF (Nl) .ptd 200405184 V. The topological variation of the description of the invention (58) is determined. Among them, it depends on the width of the shadow element, the integration of the dish, which is provided in one, the degree, etching, or copper consumption, and the distribution of the electric power. The decision is made on the network, the network and the prediction are among them. Internet, on demand. According to the following steps of the present invention: generating a prediction of the number of model attached models and production topological data based on the design, 'the generation (the complex of optical variations which is approximately corrected to one of the complex electrical effects; and An RC capture tool is used to combine the use of the remote model with multiple secondary regions of the affected circuit. The use step size includes at least one of the following: micro-trench width, etched trench depth, etched sidewall angle. The total power consumption includes thin film resistors, capacitors, drive currents, signals, and timing closure steps and at least one of the prediction steps is a service. It includes an internal network, an external network, The step of one net or the step of determination is based on the request of a plurality of users for another purpose. The present invention provides a method, which includes an electronic design of an integrated circuit, and the integrated circuit uses a component size change introduced into the integrated circuit. Granted-In the manufacturing process, the generation step includes the topology of the root and the size adjustment of the topology-related components of the electronic design. A plurality of optical interference effects using an optical 1 proximity correction) to adjust the set

(jh I 200405184 V. Description of invention (59). Among them, the electrical design of the electronic package includes thin film resistors, capacitors, drive currents, signal integration, power distribution, and timing closure analysis The variation of these device sizes includes at least one of the following: lithographic device width, etched trench width, etched trench depth, etched sidewall angle, dishing, or total copper consumption.

It also includes generating the electronic design using a configuration and loop tool. It also includes the use of a resistor and capacitor (Rc) dimming tool to adjust the code. It also includes the use of an electronic design automatic simulation tool to generate the electronic design. It also includes the use of physical confirmation of differences to confirm the electronic design. It also includes the use of an optical approximate school history (0PC) tool to adjust the electronic design. It also includes the use of signal integration to verify the electronic design. It also includes guaranteeing the manufacturing capability of the electronic design. It also includes improving the electrical performance of the integrated circuit. It also includes improving the electrical performance of an electronic device layout of the integrated circuit. It also includes adjusting a formatted file according to the adjustment of the electronic design, the file format conforming to an EDA file format. The file format includes a graphic data stream (GDS,

1057-5667-PF (Nl) .ptd Page 62 200405184 V. Description of the invention (60) Graphical data stream format. The step of adjusting the electronic design includes improving the manufacturing capability of the integrated circuit. The step of adjusting the electronic design includes adjusting the design to improve circuit performance. Wherein, generating the electronic design step includes predicting a complex topological variation corresponding to an interconnect level. Among them, generating the electronic design step includes predicting multiple topological variants corresponding to multiple interconnecting levels, electronically characterizing or simulating multiple interconnecting levels. This includes the decision based on that influence to determine the configuration of the dummy fill or multiple trench structures. This includes determining the configuration of the plurality of electronic components in the integrated circuit. This includes determining the routing of the complex internal wiring area between the complex electronic components in the integrated circuit. The integrated circuit includes a system-on-chip (SoC), and the method also includes determining a plurality of interconnected circuits in the SoC device. This includes determining the geometry of the complex electronic component, complex interconnect, or plug (v i a) in the integrated circuit. It also includes an electronic design automation (EDA) in conjunction with this prediction and validation step. Among them, at least one of the determining step and the predicting step is provided on a network as a service.

1057-5667-PF (Nl) .ptd Page 63 200405184 V. Description of the Invention (61) ~ The netizen invites among them, the Internet, the Internet, the Internet, and the Internet t — provided by mouth 1, 'same path, request. Plural use According to another object of the present invention, the present invention provides the following steps: generating an electronic design of an integrated circuit, the 鞅 ′ includes producing according to the design, and using the elementary and half circuit system introduced into the integrated circuit A different process of topological distribution is performed; in which, the generation = l = inch variation data, a pattern attached to the topological expression of the pattern attached model and the topological expression of related component sizes, and multiple predictions of the root variation, adjust the electronic design; You can use a R c button to generate and adjust the electronic design. According to another object of the present invention, the present invention provides a method including the steps of: generating an electronic design of an integrated circuit, the integrated circuit being produced according to the design, and using components introduced into the integrated circuit Dimensional variation is a process of topological distribution, wherein the generating step includes adjusting the electronic design based on a complex prediction of the topological expression of a pattern attached model and the complex variation of the topologically related component sizes; and using an RC Take tools to generate and adjust the electronic design. Wherein, the use step is performed on a plurality of secondary regions of the circuit, wherein the element sizes include at least one of the following: lithographic element width, etched trench width, etched trench depth, etched sidewall angle, Total sinking or copper consumption. Among them, these electrical properties include thin film resistors, capacitors, drive currents, signal integration, power distribution, and timing closure (t i m i ng c 1 osur e)

1057-5667-PF (Nl) .ptd Page 64 200405184 V. Explanation of Invention (62). Among them, the decision step and the prediction step to k are provided on a network as a service. / 、 One step where ‘the network includes _ the Internet, and the prediction step is either provided by — or an external network. The decision step is based on a plurality of users = a step system or a network user, please include the circuit system to the product ^ topology. According to another object of the present invention, the following steps: generate-product; = Production, and the use of sub-division of a complex two-body circuit system of the current road m Du Cheng 'where' use-pattern attached 4: j number characteristics, the integrated circuit is based on the production process including = to one of the integrated circuit, And (b) are manufactured by the engraving process. According to another aspect of the present invention, the present invention provides one of the following steps: Utilization—pattern accessory mold: 'include sign' The integrated circuit is based on one of a process The design is based on the complex features of the road to determine the complex number and basis of the integrated circuit. 〈Multiple configuration belongs to the eighth. The configuration attributes include the design in a configuration, and determines the plural interconnecting plugs and plural wires. It is a complex feature that meets the road. It is a complex attribute between the number of buffer areas and Λ where 'the predicted characteristics include width variation or the = attribute includes the electronic active components of the λ t' predicted characteristic packages. Width variation or flutter formula unitary variation hexyl set position and variant forms FIG.

ZUU4U ^ 184 V. Description of the Invention (63) These configuration attributes include cross-circuit circuits. % Of the interconnected components of the integrated circuit. Among them, the predictions are configured. , J breaks include geometry i 2 of dummy filling or plural groove structure. These prediction features include dummy filling or a complex trench structure. 丨 = Ben: Another purpose of the present invention is to provide a method, which includes ^ ^ predicting a plurality of electronic components of an integrated circuit using a pattern attached model. The structure, the integrated circuit is designed according to one of the manufacturing processes, and the prediction of the geometric structure of the electronic components such as H 4 is based on the variation in the width of the unitary number or the complex topological variation. This includes adjusting the design to improve the circuit performance of these electronic components. This includes adjusting the design to improve the complex junction or reliability characteristics of these electronic components. According to another object of the present invention, the present invention provides a method including the following steps: According to one or more steps of one of the production processes, an electrical shadow analysis and a pattern attached model, a strategy is generated for connecting in complex numbers , ^

Ig a plurality of buffers or repeaters to determine the size of the stomach; and use the electrical impact analysis and the pattern attached model to evaluate; the expected results of ancient buffers or repeaters; among them, The use of the analogue effect analysis is integrated into the buffer or the second part. τ, the generation of seat states is slightly generated. According to another object of the present invention, the present invention provides a method including

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200405184 V. Description of the invention (64) The following steps: re-analysis with a pattern attached model according to one or more sessions; generation, number of flow or repeaters; and confrontation and use of electricity The evaluation model of the sex shadow plastic model is configured with these buffer tests. The model and the electricity are generated by the following analysis: The model is generated by the expected repeater strategy of the relay—: & lt The use system is integrated into another object according to the present invention, and the present invention provides an I :: „„ according to one or more steps-the plural production delay of the production process. &Amp; This electrical influence impacts the strategy of the puncher or repeater; in the use of the installation system, a part of the Ci Yi T to reduce the number of complex transmissions ^ "Wu /, the electrical influence analysis is the design According to another purpose of the present invention, the present invention provides a following step: a step. According to the analysis of one or more steps and a pattern attachment, the energy consumption of the private level is produced. Type, prediction or simulation of single- or multi-rate i Ξ: ^ ΐ ΐ? Type and the analysis of the electrical impact include the straight-line and 1 strategy produced-part to reduce the energy Second:… model and the electrical impact The analysis is to design an electrical effect on the pattern of a plurality of buffers and the auxiliary results of the pattern; the buffer or method 'includes an electrical effect to integrate the interconnect layer into the slow delay. A part of the process includes an electrical influence on the interconnect layer and the cost of the integrated system. Changing the energy and timing of the process > includes the model and part of the analysis process. Tun 1 King ~ ring analysis as one

1057-5667-PF (Nl) .ptd Page 67 200405184 V. Description of Invention (65) It also includes the model and the electrical impact analysis using energy, signal integration, and timing analysis tools. . It also includes the model and the electrical impact analysis using a design rule checker (DRC) or the layout verification schematic (LVS). This also includes the model and the electrical impact analysis. Use resistance and capacitance manipulation tools. Among them, the process flow includes CMP. + Wherein, the process flow includes plasma etching, lithography, or deposition. According to another object of the present invention, the present invention provides a method including T-row steps: one of the production processes according to one or more steps Impact analysis and a pattern attached model to predict the width and thickness of the component of the complex interconnected geometry ^ one level. Wherein, these device dimensions include at least one of the following: lithographic device width, etched trench width, etched trench depth, etched sidewall angle, dishing, or total copper consumption. A method, including an electrical impact process, configures a dummy property model to evaluate the expected effect

According to another object of the present invention, the present invention provides ~ j steps: according to one or more steps of one or more steps of the production process analysis and-pattern attached model, generating a strategy to fill in the system; and using the electrical impact analysis and The pattern is filled with a dummy filled in the size and configuration of the buffer; among them, the model and the electrical impact analysis use the punch strategy to generate a part of the size and configuration strategy.

1057-5667-PF (Nl) .ptd Page 68 200405184 V. Description of the Invention (66) According to the present invention, the following steps occur: the level of the complex buffer difference occurs in the structure. Among them, it is provided in a network and the Internet. The following steps are analyzed and rooted. The following steps are analyzed and rooted. The steps are analyzed and the pattern is attached to the display. Another object of the present invention is to provide a method for predicting a complex variation in a predetermined integrated circuit using a pattern attachment model; and performing size adjustment and configuration processing on the interconnector to comply with the adjustment steps and The prediction step is at least one of them as a service. v The network includes an internal network, an external network, a prediction step or the decision step based on a plurality of operations, the 'and the supply. According to another object of the present invention, the steps include connecting according to one or more steps, and the steps of a network are required to include an influence device. Include impact road. Step. Including the influence and the type, the present invention provides a physical circuit element of the production process, provides a physical circuit arrangement and circuit provision of the production process—a pattern attached model of one of the electrical images of the production process, and determines a complex product based on this step: In the root pattern, you can follow this step: in the model of the root pattern, another purpose of the Ming, according to one or more steps attached to the model, the decision to feedback (feedback another purpose, according to the one or more steps attached to the model) , Determine the result of comparing multiple complex numbers, etc. The results are based on the complex product of one of the present invention) to one of the present invention: utilization method, a method of matching electrical parts, a method of thinning step of electrical wires, and electrical response analysis All or part of the crystal y I person 1 knife image, these results are based on a complex statistical bar graph

1057-5667-PF (Nl) .ptd Page 69 200405184 V. Description of the Invention (67) In other words: 2 and other images include thickness, total copper consumption, film resistance, disk, U, and erosion information. Resistance, ί: equal bar graphs include thickness, total copper consumption, thin-film electricity, and erosion information. Where 'is a comparison between two or more sets of designs. Progressive; 1 is compared to two or more sets of process recipes or tool settings of the same design = :, compared between two process steps of the same design. The results of Turtle II are displayed through a web browser or including an intranet 1 " Kushiro and an internet. i: Ben :: · Wait for the result to choose a design for manufacturing. Another purpose of χ month is that the present invention provides a method for recording the ancient and the following steps: in the step χ month length seeding method, including the use of at least-production process and ji 稷 1: measurement, the device is an attached model Select the place. '^ ,,,,, according to one of the processes, the pattern according to another aspect of the present invention: The following steps: select a complex method on the device, including manufacturing using at least-production process, wherein the two devices are selected by analysis Such locations. One of the electrical processes of the μ I process is selected from the electrical impact analysis, which also includes according to the position. The process includes chemical mechanical polishing. Among them, these bits are selected according to a measurement strategy. Among them, the selected positions are part of a measurement recipe. 1057-5667-PF (Nl) .ptd Page 70

200405184 V. Description of Invention (68) Among them, the selected positions correspond to a measurement strategy. Among them, the process includes electrochemical deposition. Among them, the process includes two or more stages. Among them, the process includes two or more processes. The process includes two or more steps in a single process. These two phases include deposition and chemical mechanical polishing. Among these, the selected positions include positions in a plurality of crystal cubes and a plurality of wafers (crystal cubes to crystal cubes). Among them, one of these two stages includes lithography. % Among them, one of these two stages includes plasma etching. It also includes the use of a patterned test wafer or a plurality of test semiconductor devices to generate the pattern auxiliary mold according to a pre-selected tool or process recipe, wherein the pattern auxiliary model corresponds to a plurality of wafers produced by the plurality of pattern auxiliary features. State parameters include at least one of the following: final film thickness, film thickness variation, dishing, or money intrusion. Among them, the pattern attached model corresponding to the plurality of pattern attached features produces at least one of the following parameters: film resistance value, resistance, crosstalk noise, voltage drop, driving current loss, dielectric a effective dielectric constant. $ It also includes: using a cost function to determine the complex position of the measurement. Among them, the position is selected based on more than one pattern auxiliary model. < selection which also includes: using a cost function to select the plural positions to

Complex electrical properties 4, capacitance value, and

200405184

V. Description of the invention (69) The effect of filling in. It also includes: receiving from a client on a web server, a layout file of a semiconductor device and multiple design specifications; selecting those locations on the server; and confirming the selected location information The client is returned from the server. It also includes that a messenger located on a network can use a service that allows the user to select a location based on a semiconductor design, a manufacturing process, and a device. Among them, these locations are selected based on a single interconnect level of the device. The measurement plan is generated based on a plurality of interconnected levels of the device. The device includes at least a semiconductor wafer or a semiconductor wafer on a wafer. Among them, the step of selecting the position includes using a dummy number to fill in the target to improve the structural integrity of a complex low dielectric constant element. Among them, the step of selecting the position includes filling an effective dielectric constant of one of the improved low-dielectric-constant elements of the target by using a plurality of dummy fills. The effective dielectric constant is maintained in all steps of a trench process. Wherein, the effective dielectric constant is maintained in all steps of a trench manufacturing process, wherein the step of selecting the position includes filling a target with a plurality of dummy holes to form a plurality of low dielectric constant material structures in the trench manufacturing process.

l〇57-5667-PF (Nl) .ptd Page 72, 200405184 V. Description of the Invention (70) It also includes: maintaining a database of plural positions; this database can be linked with the strategy of generating complex quantities; and according to New or improved tools to update the database. It also includes: storing measurement information according to at least one of the following: a plurality of process tools, a plurality of recipes, and a plurality of processes; and updating the measurement information according to changes in those process tools, recipes, or processes. It also includes: a user can select multiple digits for a device via a single click of a user interface device with a user interface ^ which also includes: a user can obtain a The selected location of the device. Plural network on the Internet Φ It also includes: a user can confirm the multiple location via one of the networks according to the device and a production process or process. Among them, these positions are chosen to characterize the changes in the complex electrical parameters, where the electrical parameters include at least one of the following values, resistance value, capacitance value, crosstalk noise, voltage drop, drive loss ^ and dielectric Constant, and effective dielectric constant. Complaints, including the interpretation of the device |. ....... η ^ a And, a plurality of patterns are extracted in a layout, among which the patterns include corresponding line spacing, line width 〇

Density This also includes the use of the selected position control system or a recipe synthesis. Line process

200405184 V. Description of the invention (71) Among them, these positions are selected for a semiconductor crystal. These positions are selected for one or more sets of semiconductor crystals in a wafer. These locations are selected for one or more groups of wafers. These locations are selected for one or more batches of wafers produced by a product. Among them, a tool is used to select these locations. Among them, these positions are selected using a process control or advanced process control system. Among them, these selected locations are via an external network,

• I, the Internet, or a virtual private network is connected electronically or optically to a process or tool. Among them, the selected positions are based on the tolerance of at least one type of electrical parameter in the following rules: capacitance and resistance, film resistance, output delay, skew, voltage drop, and drive current loss , Dielectric constant, or crosstalk noise. , Where ’the selected positions are based on at least one of the following rules: circle parameter variation tolerance: film thickness, dish depression, and intrusion to class V

According to another object of the present invention, the present invention provides a method so far—selecting a plurality of measurement positions for the entire semiconductor wafer, and driving the positions according to a pattern attached to a single interconnect level of the wafer. For another purpose of January, the present invention provides a method. ^ :: Positive- + conductor chip selects a plurality of measurement positions, and 5 of these positions is based on one of the multiple interconnection levels of the chip. . According to another object of the present invention, the present invention provides a method for sending 200405184

V. Description of the Invention (72) One of the attached models of the pattern, 'Changing the plurality of wafer-like parameters, the plural has predicted the following steps: at the time of production, measuring a device in accordance with one of the productions; The predicted variation of the complex number in the parameter. This also includes variations that change multiple electrical properties during production. According to another object of the present invention, the following steps are performed: a chemical-mechanical-measurement meter is used to measure a device; the chemical-mechanical grinding still has the following steps that are not according to another object of the present invention: Testing a semiconductor device to identify plural features; and using the quantity process control system. ‘The present invention provides a method comprising grinding a pattern accessory model of a process and identifying a plurality of regions of the device to completely remove material. The present invention provides a method, which includes measuring one of the auxiliary models of the pattern and measuring the residual copper on the device after the manufacturing process.

According to another object of the present invention, the present invention provides the following steps: measuring a semiconductor device according to one of the production models; identifying a semiconductor device after the manufacturing process; and using the measured plural number The results are used as a process for feedback to the azimuth synthesis. Find the measurement formula where of which

Among them, the selected positions are a measurement book of the equipment, or an automatically generated part of the same plan. Once the equipment includes optical equipment. The device includes a portrayal device. The device includes an electronic probe device. 200405184 V. Description of the invention (73) Among them, ‘the device is red.’ Including the same room (ln_situ) or online (in) · 丄, in-ilne which: also includes the control of the feedback process. According to another invention of the present invention, the use of plural test structure and plural: test J ::? Two methods, including Links the measurement of cutting lines with the characteristics of complex crystals ...., hard number diagrams. The attached model is measured with 'these positions are at least one of online and in the same room. Or offline state where' the process includes part of the groove Process flow. • Among them, the process includes the introduction of a plurality of low-dielectric process flows. Hanging a number of materials into a trench. The process includes the introduction of a plurality of low-dielectric (ILD) materials to a trench process. * Several interlayer dielectric layers. Among them, the process includes using dummy filling to improve the structural properties of the interlayer dielectric layer (ILD). ^ 丨 Swinging several layers where 'The electrical impact analysis includes evaluating the effective dielectric constant. Among them, these locations are selected Characterized by a plasma rhyme and a plural pattern attached. ^ Where 'the positions are selected to characterize a lithography or a tool's complex C pattern attached. Where' the 4 positions are selected to characterize a chemistry machine A plurality of tools or grinding process subsidiary IC pattern in which 'the spot position of the train is selected so as to form a plurality of IC features within a plurality of subsidiary wiring pattern of the structure.

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V. Description of the Invention (74) According to another object of the present invention, the present invention provides a method including the following steps: selecting a plurality of positions to measure a semiconductor device that has been produced; Measurements show that the device does not meet a requirement, remove the device; select other plural locations to measure the semiconductor device; measure these other locations; and if the measurements at these other locations do not meet the requirement Remove the device. It also includes repeating these selection, measurement and removal steps. Among them, the measurement is performed online corresponding to a process step. / 、 The test system of ‘60’1 is implemented in the same room corresponding to a process step.

_ Among them, the measurement is performed offline corresponding to a process step. Wherein, the selection is performed by using a software of a tool. In a, the selection is based on a pattern corresponding to one of the processes of the device attached to which the data has been carried out, which is based on the multiple production process and quality, where according to the process, the 'the mold' and the modulus are measured, The position of the present invention is based on the production process regardless of the drawing process. The model position is selected. The position is selected on another device. The process is except for the case that the auxiliary mold includes grinding. It is measured by a specific tool. Into the variation of the process, and the selection system is taken at a crystal level. Taken at a wafer level, the present invention provides a method that includes measuring. The device uses at least a lifetime including removing material from a surface of the device to fall within an acceptable tolerance, and selecting the root type. These locations are tested. And the acceptable tolerance includes not over-grinding

ZUU4UM84 — > —, V. Removal treatment of invention description (75) It also includes control, in which the tool includes an optical reflection current with a corresponding tool, sound range or thirst current. It also includes the use of yield.

The selection. Device, CD, and other measurements to characterize the overall design of the wafer. Mechanical grinder, where ′ is based on -p ^, n ^ may damage the device or be extremely small. It also includes feedback to adjust a chemical or formulation parameter. It also includes feedback to adjust the flow rate of an electron-containing electro-chemical mechanical deposition tool. It also includes feedback to adjust a chemical pressure. It also includes feedback to adjust a process. It also includes feedback to adjust a process number. It also includes comparison and selection from the best known plural. It also includes feedback to adjust a plurality of processes of a plasma plasma etching process tool. According to another object of the present invention, the present invention uses a measurement plan to measure a plurality of chemical mechanical sinking processes of a semiconductor device. Contour tools or wafer-level specifications have a large number of complex integrators or packaged or formulated parameters in the complex process of the multiple differential steps of the mechanical grinding head. Synthetic recipe parameters Process method and multiple consumables Etching process tools may include a setting or recipe, and the measurement plan is based on a parameter. Method, including

200405184 V. Description of the invention (76) Plasma etching pattern attached (CD). Among them, the state of the plurality of wafers in the figure), the thickness of the film, which also includes a plurality of processes, which also includes a number of control bands. • This also includes which also includes and devices. A tool for measuring a control element according to the present invention

1057-5667-PF (Nl) .ptd belongs to the model to confirm the complex critical dimension of the complex I c element. The attached model corresponds to the features of the plural pattern. At least one of the following parameters is included: critical dimension (CD aspect ratio, or groove). Width, or groove depth. Feedback to adjust a lithography tool or include a lithography tool setting or recipe parameter. Adjust multiple design rules, multiple design specifications, or multiple designs of the test structure or device. Combine with multiple wafer parameters With another object of the existing plural test structure, the present invention provides a device including a parameter of a semiconductor device, the measuring tool includes a plurality of positions, and the measurement is performed according to a process corresponding to a process of the device. F Another object, The invention provides a method, which includes a t-type to determine a manufacturing process of an integrated circuit (IC), a device setting, a manufacturing formula, and a f-state parameter or electrical manufacturing process for introducing these devices into a variation. The state parameters include at least one of the overall production, c, and test wafers to characterize the integrated circuit injury. The pattern is used in the model on page 79, 200405184. V. Invention Description (77) and other patterns are attached to it, among which, among which, among which, among them, a plurality of wafers in which 0, the array height, and the coupling current, the pitch, line width, Among them are different predictions, and among them, they are also set by jt. Among them, they can be set, which can be a combination of gradients, modal programs, line processes, part processes, part processes, part processes, part processes, and part pattern variations. The parameters of the state parameters include the sub-included sub-included sub-included sub-included sub-characteristics including the thin-film electrical sub-characteristics including the efficiency density. Use the model to generate the parameter. Use a cost function to prepare the production, the production, the production, and the The model and parameters of the production state are the crystallinity and capacity. The graphs include the use of the cost function to include the use of the cost function to include the use of complex optimization methods to minimize the state of the multiple wafers or electricity. Optimization methods include the following annealing (annealing) program, and the approximately linear process electroplating process. Oxidative deposition. Chemical mechanical polishing. Plasma etching. Lithography. At least one of the following examples corresponding to the process introduction: film thickness resistance, capacitance, crosstalk noise, at least one of the following: multiple wafer changes in wafer state between lines Measure the comparison of the plural knots of these predictions-the variation of the group formula or plural set formula and the plural parameters. The column at least-item: single, last name dynamic formula, approximate move

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:, Also includes the use of the quadratic cost function (quadra t i c) to Gan Convergence of these optimization methods (convergence). This includes a single process step. This includes more than one process step or process flow. It also includes transmitting one or more sets of manufacturing recipes and multiple equipment settings to a user via a graphical user interface. It also includes the direct transfer of at least one manufacturing recipe to a process tool or a production automation system. This also includes directly transmitting at least one manufacturing recipe to a crystal.

• I carrier or memory device assigned to one of a specific batch of wafers. ^ It also includes the use of the pattern attached model to predict or simulate electrical or complex electrical parameters as a result of a single process step. It also includes using the auxiliary model of the pattern to predict or simulate electrical or complex electrical parameters as a result of multiple process steps or a process flow. It also includes the use of multiple actual product wafers to develop the model. The model will make the auxiliary features of the multiple patterns correspond to variations in multiple state parameters or multiple electrical parameters caused by at least one process. Among these, the auxiliary features of the patterns include at least one of the following stomach, line width, W, and effective density. Between lines

Among them, the wafer state parameters include at least one of the following examples: film thickness, array height, and step height. Among them, the wafer state parameters include at least one of the following examples: a thin film resistor valley, crosstalk noise, and a face-on capacitor.

Page 81 200405184 V. Description of the invention (79)-This also includes ensuring the manufacturing capability of the IC design before placing an order (tape otto) and manufacturing before the photomask. This also includes the ability to place orders (tape out) and simulate the IC design before manufacturing. This also includes determining a process flow in a plurality of pre-selected items designed by IC. This also includes changing the plural recipe parameters in a 1C manufacturing process to characterize the plural pattern attachment.

This also includes applying the party to characterize the process drift at multiple points in the life cycle of the process. Among them, the process tends to include a CMP pad placed or built on the walls of a plasma reactor. — Make it available to a user, which is implemented by software on a medium. This also includes providing a patterned user interface result. The middle system is used for process synthesis and is implemented on a web server. Medium system is used for process optimization and implemented on a web server. Medium system is implemented on a web server.

It also includes the zero-customization network service for different users. It also includes one process step or four process steps in a process. Spatially confirm post-manufactured faults across a crystal cube. This also includes receiving through a web server using a specific process or

1057-5667-PF (Nl) .ptd Page 82 200405184 V. Description of the invention (80) Prediction of the 1C complex manufacturing capability of the tool ^ It also includes the use of an online feeding tool or the addition of multiple process tools or steps, automatically Provide a process schedule. Renzhong has selected recipes or multiple settings which also provide a user to get an optimization from one mouthful. The word server corresponds to one click and it also provides a user to obtain an optimization from one. The server corresponds to one-click, and it also includes more than a plurality of process hours or Xin Cheng trend and switch (sh i f t). The characterization of YI YUN YEN includes maintenance and repair work of multiple tools for scheduling. This also includes selecting multiple consumable groups. The consumables group includes a plurality of polishing pads, a plurality of polishing liquids, or a gas composition. # w 挺 According to another object of the present invention, the present invention provides the following steps: according to one or more steps of the manufacturing process flow, electrical J-variation analysis and -pattern attachment model, generating a strategy to compare plural eliminations: two Or the equipment / and the use of electrical impact analysis and the pattern attached model make the selected integrated circuit of the consumable group or equipment set the expected results. Among them, these consumable groups include multiple polishing pads, multiple liquids, or multiple gases. Among them, the equipment includes CMP, ECD, plasma etching, lithography, and deposition equipment. ^ 5

1057-5667-PF (Nl) .ptd Page 83 200405184 V. Description of the invention (81) According to the present invention, the following steps: based on analysis and a pattern with a consumable group or equipment; evaluation of the expected use of a selected design Among these liquids, or multiple gases, the equipment is provided. Another object of the present invention is to provide a method, which includes one or more steps of an electrical influence model of a manufacturing process, generating a strategy for analyzing or diagnosing a plurality of eliminations, and using electrical influence analysis to obtain the pattern attached model. Complex integrated circuit results for such consumable groups or equipment. The consumable set includes a plurality of polishing pads, a plurality of types of polishing, and includes CMP, ECD, plasma etching, lithography, or deposition. According to the following steps of the present invention: According to another object, the present invention provides a method including one or more steps. An electrical impact analysis of a manufacturing process and a pattern attachment model produce a prediction of the geometry of a plurality of isolation trenches. The process flow includes CMP. The process includes the plasma # 刻. Characterize the plural specific aspect ratio of one of the tools for plural diagnosis or control. Build a database for analysis. Compile aggregate statistics on tools or consumption behaviors Establish plural standards for tools or designs. Provide information via a network. Prediction of an active device area and an isolation trench interval, among which, the system, which includes a plurality of patterns attached, which also includes, which also includes materials, which also includes, which also includes, which also includes

1057-5667-PF (Nl) .ptd Page 84 200405184 V. Description of the invention (82) The groove rounding of the interface. It also includes predicting a threshold voltage of an interface between an active device region and an isolation trench. It also includes predicting a leakage current at an interface between an active device region and an isolation trench region. It also includes a polysilicon stringer that predicts an interface between an active device region and an isolation trench region. It also includes a plurality of process steps or processes for forming a plurality of trench isolation structures.

% This also includes selecting a specific shallow trench isolation design. It also includes selecting a design or multiple process features to affect the fillet condition of the trench edge (Conner). 'The process analysis including the process and the period is included in the more clear'. In accordance with another object of the present invention, the present invention provides a method with the following steps: manufacturing electrical properties by trench isolation according to one or more steps Impact analysis and-pattern auxiliary model, generating-strategy to configure a plurality of dummy filling in the oxidation area; and using the electrical property to affect the map, the auxiliary model evaluates the pre-fruits using the dummy filling configuration " The impact analysis and the use of the pattern attachment model are part of the generation of the filling strategy. Let the above and other objects, features, and advantages of the present invention "," Yiyi ", and" II ", a preferred embodiment be exemplified below, and described in detail below with reference to the accompanying drawings.

200405184

V. Description of the invention (83) Institute < Figure 1 A The green system uses electronic design automation or (EDA) tools :: integrated circuit to allow the designer to set the block τ °°. Use-computer tools to configure components and set up connections and plugs. In the design of the chip: the endogenous-electronic archives that need to cross multiple levels must be formatted in the following format: ---; temples, using EDA tools to produce orders using this archive (tape-ouJ = description device, 10102. circuit characteristics) Lithographic mask, 101) 04 union. Produced for use during the production process; processes can include deposition, lithography, radon, electricity mining, and

(CMP) step 'and select each tool setting (such as gas, grinding mill, grinding fluid, etc.). A wafer utilizing the physical and electrical characteristics of this process, I. ·. Generates measurements made across this ... 10108. -Amount of jealousy, 10'ΐη using this recipe ’纟 includes how and where to measure this; If this chip or device meets the specific performance and yield rate chip! Test this setting on: Ten and the process, then use and produce this crystal performance fish ^ Also calculate the area of φ error, 101 丨 6. This kind of shadow

Changes in width or thickness in the Ciiifrn road geometry. Isolation plugs, dummy fills and trench sizes, and shallow trench isolation configurations and trenches. And Cheng / 苒 倌 Chengtu No. = ΐ ϊ ϋ 利 ”case is attached to improve the design process of the design process, and the surplus is determined by the layout of the generality, the disc sigh (such as material negative slack, line width, line

200405184 HMli ----- V. Description of the invention (84) Spacing) Variation. Non-planar surfaces often lead to problems with integration. This kind of # 羑, and other process capabilities and enlightenment, such as the effect of the structure on the device will vary. Generate electric valley value and resistance value in this way. “Designer's structure, 10 ″, generate electronic file in GDSII format. The geometry knot of the road interacts with the system, 10 i 44. Field, or direct case geometry The structure corresponds to each-manufacturing process using the model 'the thickness and width of the components of the chip in the design diagram. The whole chip or the impact after the process steps, such as timing, clarity, and methods can be used to characterize electrical changes in functionality. Yield and other issues, 1014Y. And the influence of power characteristics' or other parameters and differences. The method can also be used to predict the characteristics required for yield changes: good Test; regulation: pass, this design will go-not meet (below an acceptable t Y mask manufacturer to make lithographic masks. If count, 1 0 1 50, such as this square 7 standard), this method can be used Adjust the setting or groove structure to change the size of the flat load / distinguishable size, and configure the dummy filling mole standard) m also; use; J: if it does not match lower than an acceptable one • Circuit components meet can be connected ',, the geometric knot on the mask, so that the map ic map The method can be used to characterize the use of flow / manufacturing rights to manufacture Chinese circuits. The pattern between this structure is attached. This == process steps of the design and manufacturing geometric structure corresponding to each process or I use the model to design the pattern Geometry, whole or part of the wafer after the steps of the bathing process 1057-5667-PF (Nl) .Ptd p. 87200405184

V. Description of the invention (85) The thickness and width of the component, 1 0 1 7 2 Similarly, this method can also develop models that utilize specially designed tests or characterize wafers to characterize the range of circuit geometry (such as variation pattern cost, line width, line thickness, line spacing line, and the angle of the trench sidewalls). And aspect ratio).

This method can also be used to select process recipes and tool settings, and select consumables (such as polishing liquid and polishing pads) for each step, 1074. The process flow can include deposition, lithography, electrical keying, and chemical mechanical polishing (CMP) steps. Select the tool settings and consumables (such as gas, polishing pad, polishing liquid, etc.) for each step. Use this process to manufacture a chip with physical and electrical characteristics of the total software design _ ^ 1 0 1 7 6. Generate a measurement recipe to measure the position across the device being manufactured 'and generate measurement tool parameters (such as depicting measurement parameters). 1 0 78 ° A measurement tool uses this recipe to physically Manufacture the set of wafers, or array wafers or cubes on the wafer, 10180 〇 If the wafer or device meets + specific performance and yield specifications, then the wafer is manufactured, 010 90 ° If the wafer or device does not meet the specific Performance and yield specifications, adjust the process recipe or consumables to correct the wrong area, 1 0 1 84. If the chip or device does not meet specific performance and yield specifications, adjust the design (eg, using dummy fills or trenches) to correct the wrong area, 1 0 1 86. When the adjustment setting =, this process can feedback the adjustment layout, 1 0 1 4 0, Fig. 1B. When the shoulder is not timed, this process can be returned to the person who chooses the process recipe and consumables ^, 1074. As shown in Figures 1A, 1B, and 1c, this method can be used to characterize pattern attachment variations, and specify methods to modify and measure circuit geometry and components, including

1057-5667-PF (Nl) .ptd Page 88 200405184 V. Description of the Invention (86) --- Variations in the interconnecting degree and width of single or multiple interconnecting levels including the King 3D special imitation. This method can be used for a single process step, such as thick mechanical grinding (CMP), or a multi-step full process flow, such as copper to machine. Each process type and specific tool type and setting of the individual object slot have different pattern attachments, so it will change the influence of the width, thickness and thickness of the crystal, wafer and toilet. The following description of the batch level will describe the process variation of adding dummy filling to reduce the electrochemical deposition of the structure of the semiconductor device and the subsequent special connection in the chemical mechanical polishing. Variations in wafer quality (such as thin-film thickness variation discs from W, I variations, such as dish sinking and erosion) and electrical parameters (resistance, electrical = surface extension) can be used for semi-physical process models. Step-by-Step Procedure—Measures one or more types and simulations of a specific process in a step. Configure the dummy filling structure in the layout; when maintaining electrical = modular = setting or design value, improve the thickness and surface of the wafer. 4th can be configured according to the following methods: gastric design cloth. Such as effective pattern dense Tang, county; π Dou, Dan, 丨 丨 Haiku parameters, improve the lower layer dielectric insulation> (1 into the width and spacing between Α structure; 丨 # +1 r, marginal layer (such as low dielectric The constant) of the structure. * And minimize or limit the impact on electrical performance. "I, and most

In order to provide more effective data storage "... ce ") The database is duplicated on the chip equipped with dummy padding. This unit needs to be filled in every time. The parameter can be stored in the redundant information about the dummy structure. : Can reduce the storage of the same size units to fill in a specific area. You can also choose from the library to not use the manufacturing process models or molds, and other types of units. And the electrical performance of the virtual 4 person method

200405184 V. Description of the invention (87) The model or simulation is embedded in a dummy simulation system, which can minimize the influence of process variation and subsequent electrical performance. The better method is to form a feedback system to determine the appropriate size and configuration of the dummy filling, to minimize the impact of process variation and subsequent electrical properties. 31 > 33

Fig. 7 shows an embodiment of the present invention. The sub-blocks in Figure 7 (--1, 34, 35) will be enlarged and described in blocks b to f. 1C designs usually electronically display database files (eg, in GDS format) to define the structure and location of each level of the integrated circuit, 30%. Such files are generally very large, although components related to process variation can be more efficiently expanded. Layout extraction, 3 1, is related to a dense combination of the discrete grid in the integrated IC design. Its parameters include line width, line spacing, and density layout characteristics of each grid. 3 3 To wafer: mouth quality, such as film thickness, or electrical parameters, such as film resistance or capacitance. This information can be used for a single process model (such as CMP) or a set of process models = with nine-step fruit CMP process, or more complex process flow to predict or model = f &,., 0, and corresponding Variation, 33 — i. This becomes ‘such as an optical measurement of film thickness, or wafer surface texture, high depression or step height, and invasion of money or arrays.

4 Sub-ground 1 to measure such variations, such as film resistance or electrical L and may need to use the original 1C design, 39. Calculated parameters from $ 33-2 hurt A person B u to

The date is too much, and it is the integration of the king chip, and it is also applicable to the crystal cube or multi crystal cube that spans H, 3 3-3. Pavilion Yinri W combined with the process model rabbit ^ -ΤΙ JA ^ · | μ 々 々 々 々 问 问 问 问 问 问 问 问 Xing electronic fork is expected to predict the performance of IC design, face-to-face wafer quality mine from 4t bimonthly b, and Compare, Yidian | ± parameters with design rules

200405184

From a scientific point of view, such comparisons can be viewed as functions), 35, A series of root / two functions (in cost, if can be one to two or two, Kang can reduce process variation while maintaining electrical performance, and can perform仃 Comprehensive dummy filling strategy. If the design fails to meet a specific category # -X —, distortion requirements' dummy filling (copper or emulsion) can be added to adjust the layout. Zhao ^ ^ ^ ^ > number (such as density) The layout and post-processing parameters of 70 features will be taken, 38, and design rules, 37, and the size and configuration algorithm will be substituted, 34, and the target and target maps will be filled in in this design, and The position or configuration of this structure. The size and configuration of this dummy fill include two main components: rule generation,

% -1, and size comparison and classification configuration, 34_2. Rule generation is a transformation of this design rule and is qualified to conform to the guidelines of a dummy entry. Each dummy fill can be configured as an independent target in the chip design, but this method will greatly increase the size of the layout. Taxonomic units or meta-objects (meta_objects) are generated based on structural characteristics, such as line spacing and line width. This type of unit represents the file size and memory requirements that will be used more efficiently when sorting in the design file. This system outputs design files in a graphics computer-assisted design format (such as GDS). The complete system can add each IC component in real time or after all I c components are added to the I c design layout.

=. Repeat this method until it is determined to meet the desired process specifications and electrical performance. This design will confirm that it can be manufactured, 3 of 6. b The following sections describe the manufacturing methods of the examples. Section a describes the use of embodiments to reduce variations in the electroplated copper deposition (ECD) process. Section b describes the process of extracting layout parameters related to process variation and transforming large design files into manageable feature sets. Although it is not necessary to perform layout capture, it is better

1057-5667-PF (Nl) .ptd 200405184 V. Description of the invention (89) Still needed. Section c describes the use of process and electronic models to characterize the effects of electrical process variation. Section d describes the use of a cost function to estimate the impact of dummy fill adjustments (or no adjustments), and how to use this function to achieve the desired wafer quality and electrical performance specifications. Section e interpolates the dummy filling rules—the generation and management, the size of the dummy filling, and the configuration of the dummy filling. Section ί describes the classification unit allocation algorithm and the benefits of memory. Article ^

Section describes the application of the dummy filling system to the trench process flow, electrochemical deposition (ECD) and electrochemical mechanical deposition (ecmd), and the integration of low dielectric constant dielectric materials into the trench process flow. Section h describes the structure and calculation organization using the dummy filling β method, and the operation and user methods of the dummy filling system. Section 1 describes the results of the dummy filling method and screen images of the user interface. 〃 a • Using dummy filling to reduce the related variation of ECD In the copper trench process, a line structure is used. The purpose is to fill in completely and without holes when the minimum surface topology (usually referred to as the height of the trench region. The variation and minimization of the thickness of the copper deposited by the electroplated copper deposition (ECD)).

^ Beam time (time to fill the groove completely, marked with) depends on the depth of the groove. For large trenches, the copper sinker # on the sidewall is smaller than the trench width. Therefore, such trenches tend to be filled from the bottom. This area has the same deposition rate. This trench is filled with 1 = copper thickness in this region, which will leave large step structures, or so-called step heights, on the surface of the vast trench structure. In contrast, sidewall deposition of small trenches

200405184 V. Description of the invention (90) Quickly reduce the groove width. This increases the coagulation of the catalytic medium and precipitates in the solution, resulting in a faster deposition rate at the bottom of the trench. The copper fill in the trench will stay in the same area until the trench is filled. Residual catalyst in the copper of the small trench allows the copper deposition to continue to cover this trench, resulting in the formation of copper bumps or inverted step heights. The combination of the huge variation in the width of the trench on the wafer will result in a large amount of variation in copper thickness and step height. Dummy filling or dummy trenches can be used to reduce the variation in the thickness of copper deposits and surface topography. Adding dummy fills to the surface topology significantly reduces variability. Reducing variation can obviously achieve the purpose of flat grinding, so it can reduce the need for dummy I filling and dummy trenches to reduce CMP variation.

For example, when dummy trenches are used to fill oxide structures or trenches are used to fill such trenches, variations in thickness and step height due to electroplated copper deposition can be reduced. Section 8® shows the use of oxidative dummy filling in EcD. Figure μ shows the difference between the deposited copper thickness 40 on the narrow line width 41 and the deposited copper thickness 45 on the wide line width or trench 43. The line in FIG. 8B shows how the oxide dummy pillar 44 is added to the trench 45 so that the deposition thickness at the narrow line width 48 is equal to the thick production 47. The role of the oxidized dummy pillar 44 is to reduce the effective width of the trench. Oxygen: = ΐ is the same as the case where the metal is removed and added to the trench. This figure reveals that oxidized trenches are set so that the process of depositing wide trenches is like θ, which reduces the difference between the thickness of the deposited copper and the height of the step. == The groove is smaller than the width of the groove compared to the bottom, and the electrical property of the wide inner wiring will be small = 2. Utilizing the electrical simulation function of the enemy, such a slot U can be calculated. “This calculation result will determine the density and density of such slots on the wire.

V. Description of the invention (91) While the total amount of such slots is limited to a low CMP front step height, "Although the oxidation dummy structure will be added, the CMP process will be lowered, and a flatter CMP process will be obtained. B · Consider the layout parameter layout system It is a set of electronic stems and geometrically distributed space bits w. Second, the structural design of each layer of the storage integrated circuit has a space of t, a disk, a line width, a process level, and a flat level. "Process variation and implementation will use layout capture. Relevant. In order to characterize this relationship, the line width and the degree characteristics are actually taken out. Profit: The geometric description of the chip in the local area. Extraction and reference information can determine the area on the chip where _see / and j degrees exceed the design specifications. Note: Although the layout parameters of the dummy filling are calculated, although the dummy filling method is Lingtiantiantian &, the tea is fixed in the line and the line width * ^ ffl, § „. Know the density and line width of the capture, other embodiments You can use the capture line spacing method. Fig. 9 is a flowchart showing steps in Fig. 7 for layout operation. In the ninth round, the bureau file was transmitted or uploaded to the dummy filling system, u — i. The cloth is divided into separate grids, the size is small enough to aggregate calculations, the largest and smallest elements can be used to represent the structure in the grid, and the dummy fill can be correctly configured. The general grid size can be 4 〇 # ^ X 4 〇 #melon. Web screens can be arranged by g or 31,3. In the preferred embodiment, multiple processors are used to calculate the grid in parallel. Select a grid, 3 and 5 and in this grid, each target 31-6 'has a calculated line width, 3 and 7. Repeat this process for each target in this grid, 31-8. Calculate the maximum, minimum, and distance from the average line for each group of adjacent targets, 3 1-9. Then calculate the effective density of the full grid, 31 -10. Repeat this process on the remaining grids, 3 丨 _ n. Due to all grids

1057-5667-PF (Nl) .ptd Page 94 200405184, Description of Invention (92) Perform the above steps to recombine the extracted features from different processors 3 1-1 2. Create a form and fill in the maximum, minimum, and average line width, line spacing, and density, 3b13. A range is calculated using the maximum and minimum line widths. The line-of-sight range (M) is divided by the desired number of lines (n), 3 丨 — 丨 4, to determine the relative size of each N line segment. For example, the first line segment is the minimum line width, or a small non-zero value △ corresponds to the line width (M / N) until the Nth line segment line, where the line width will be from the minimum (M / N) to the maximum lw_ = n • (M / N). At this time, there are three sets of line segments. A set of line segments contains the minimum, minimum, and average line widths. Each grid is based on maximum, minimum, and average

Si from the line of the line, 3 Bu 15. Each segment line forms a bar chart to show the distribution value of the segment line, 3 to 16. This information repository is imported into the process model, and special counties are only responsible for this. ^ Rule, 3b17. Don't stomp the karyotype, and generate dummy fills ... f Calculate the maximum, minimum, and average line spacing range on the whole two wafers, 3-18. The line spacing range (M) is divided by the number of lines (n) to be obtained, 3i —. : Modal line is the smallest ㈣, or a small non-zero value △ corresponds to the line spacing (, up to the Nth line segment, where the line spacing will be from the minimum 4 ί ηη = (Ν_1) · (Μ / Ν) to the maximum "" ax LWBinN = N · (Μ / Ν). = Yes: Group line segment line 'A group line segment line contains the maximum, minimum, and average lines: line;: The grid is separated into 20 according to the maximum, minimum, and average line spacing. A bar graph is formed for each segment line to show the line segment module θ 21. This information is stored with the database and imported into the process, 'especially the ECD model, and a dummy filling rule is generated, 3 bu 22. V. Description of the invention ) In the whole chip of ancient times + Zeng ^ Example 3 " 3. Density range divided by the desired line = average density range, such as-the line segment is the minimum number of lines (N), 3 " 4), straight to the bar; to the density minLWBinN = (Nl) · (M / N) to the maximum / a ^ and 1 from the minimum at this time there are three sets of line segments, and one set of lines (M / N). degree. Each-grid is separated into appropriate distributions according to the maximum, ,, ⑧⑦, minimum, and average dense line segments, 3 " 5 second line / post V: / average density 彳 t, Ή% ^ Λ # and the line is formed. The figure shows the _ of the line segment, especially the ECD model, and generates a dummy filling rule, 31_27. After & all the line width, line spacing, and density information are stored in the database or broadcast system for application Subsequent process model predictions or dummy rules generate toilet configurations, 31-28.演 The calculation rules of the dummy filling configuration also need to obtain the correct coordinates of the layout target and its neighboring perimeter. The obtained information includes the size (length and width) of the target and the spatial distribution of adjacent targets in each direction. Determining the coordinates of the dummy fill-in area requires four steps. The first step is to obtain the coordinates of the selected target to determine the length and width. The second step, as shown in FIG. 10A, is to calculate the space between the selected target (target A) 50 and the nearest target, such as target B) 51, (target C) 52, (target D) 53, and ( Underlying E) 54. If there are multiple targets in the same direction, space and range information must be calculated. As shown in Figure 10B, there is only one target on the east side of the selected target, and the space between (target B) 50 to (target A) 55 is 50 // m. In Figure 10C, there are two targets 58 and 59 on the east side of the selected target 57. This solid line spacing has

1057-5667-PF (Nl) .ptd Page 96 200405184 V. Description of the invention (94) Two groups; (subject A) 57 to the farther standard 5 9 has a line spacing of 5 0 // m. (Target A) 57 to the nearest target 58 has a line spacing of 10. Figure 10D also has two targets 62 and 63. However, this example has three sets of ranges. The east side of the untargeted to the target A is located between x = 20 // m, and the range from the target A to the grid boundary 61 has a range. The peripheral distribution of each target produces one or more sets of spatial extents. If there is no '' until the selected block or grid 6 1, the space can be set as the distance from the edge of the target to the grid boundary or the neighboring grid 6 1 until the target is found in the search (or the wafer boundary is reached).

% The third step uses the line width and line spacing information to generate a dummy fill rule from the rule table. Finally, the fourth step is to calculate the coordinates of the dummy filling area according to the dummy filling rule and the coordinates of the selected target and its surroundings.

Figure 11 shows how to use a capture table to represent a whole wafer or crystal cube. The wafer f crystal cube A1 is divided into a grid A3, and a line width A5, a line spacing A6, and a density A7 of each grid element A4 are calculated using the extraction procedure shown in FIG. FIG. 11 shows the line width (LW) in the extraction table about the grid on the (y, X) coordinate (丨, 丨) and one of the grids on the (y, X) coordinate (2, 1). Fishing line spacing (LS) and density values. In many instances, the maximum, minimum, and average characteristics of each grid will be stored in this form. c. Process and electrical model The dummy filling method of the present invention uses a process model or a series of models (ie, processes) to predict manufacturing variations in physical and electrical parameters in IC. In order to characterize the manufacturing variation related to the IC structure, a dummy fill can be added to

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Most: the change between the physical and electrical parameters and the desired value. Attached to any particular type of model or simulation. However, the accessible / $ Cheng tool has individual details, private recruitment period, office, and mother. The mother and child are presented as 1 female / from, but it is acceptable that each model requires standardization of specific formulas: . In Fig. 12A, using the configuration "m" 'such as, 66, the actual wafer on the 64, 64, the second special labor measurement, 67, and the post wafer measurement, 68: two different processes Wafer 69. A preferred embodiment is to use a set of semi-empirical < mouth-shaped parameters, to produce calibration model parameters or match parameters, 70, 7:? Method extraction, or linear deduction (such as neural network) : ,, linear best using specific tools and formulas, 71. The last fork can be calibrated to fit here can be observed, some I c characteristics such as the A and B from the distance directly and electroplating, deposition, and CMP process two flutter Second degree, line width, and line also show that the characteristics of changing some areas on the crystal cube are related to two different gates. Here under the known tools and recipes, the design is: number ==; the circle can be used in J degrees). Manufacturing variation (thin film thickness, dishing, seeing, and line spacing 1) wafers have a variety of possibilities to evaluate the relationship: ^). The cost of noise measurement is low, and the test wafer design can be used in two types of processes and Formula. As shown in Figure 12B, the calibration process or multiple process models or one system for each calibration process of the extensive IC design is also used. Calculate the calibration model parameters using the same method as that used to generate the 1 2 A picture of the test wafer. One of the differences between this and the first is that the available test crystals will not be described in detail. Provided by the manufacturer, And by electricity

1057-5667-PF (Nl) .ptd 200405184 V. Description of the invention (96) Sub-types, such as obtained through the Internet, e-mail, and, and introduced pre-process measurement, 74. Another difference is CD, or file type measurement, 78, which usually spans a large area with different line spacing, so it can be applied to large area components. The density characteristics of the 、、、、 / 、 The 1st 3 Δ chart shows that the test wafer is calibrated to the wafer crystal, 79, which is based on the line width and line spacing, = 1. A test theory. In the manufacturing process (such as CMP, ECD, or deposition), this test is carried out: The patterning process is performed with a known formula, 81, and it is advantageous to use a tool to measure the circle, such as film thickness, 84). This correspondence is the correspondence between 3: Φ variation in -module. As shown in Figure 13B, the value of the specific film thickness can predict the process variation of the new employment plan. It is not necessary to implement this correspondence to create a designed process. Extracted the light from the new IC layout. The range of 2 and 2 falls on the test crystal ... The sign of the wafer == the sign that crosses the crystal η Club 5 ^ ㈤ 门 '8 b), 8 5 〇 will be medium, 87 == width and line spacing Characteristic, input corresponding relationship measurement, heart ::: = fix: Pre-design with variation of film thickness with r. And Beiji produces expensive masks and processes this new I c

Model Π1 Second picture: Shown, the process variation of this prediction, 91, can be imported, 93 —. Then $ 敕 92 to evaluate the electrical performance of the process on the chip's electrical design), _ :: The design layout is filled in & filled in or adjusted to the specific layout parameters, and the evaluation of the process variation is repeated. Repeat the process ^ to achieve the desired level of process variation. The following figure does not describe the use of process and electrical models to characterize variation and

Page 99 200405184 __ 丨 丨 丨 II I 丨 丨 丨 _ιι V. Description of the invention (97) Implanted by dummy filling. Figure 14J depicts the standardization of a process model with specific tools and recipes, as described in Figure 1. 'Calculate layout capture parameters, or test in progress

Si said two ί uploaded by the wafer provider. The second step, 33-4-, allows you to test this wafer. This measurement includes thin ridge thickness and contour scanning = take array and step height. The third step, 33_4_2, includes a specific process or process flow for the test wafer. This process or process can be integrated, or (or a grinding step. The better method is to calibrate the individual process ":: Second exhibition also calibrates the process section, you can get the coupling phenomenon in the process. Here It is also recommended to calibrate the different formulation parameters with the same type of “fine denier q 仃 ^”. In this process, the same position of the wafer is measured by the same order, 34-3-3; this measurement includes film thickness, And can characterize the variation of this process, 34-4-4. The uploaded variation is beneficial to this type 2 type 4: 5 period and later period. Planning the model special tools and / or recipe system The above model database Ϊ: User uploads, or fills in the computer system variation system from the default to meet the g ::: and subsequent measurement and calculated system ##, the 33-4-7 process model is calibrated A calibrated process that conforms to a specific tool and / or process also includes a series of process parameters that can be used to simulate process parameters to predict process variation and subsequent electrification and desired IC products. Steps to organize the new layout or layout file Information on W Zhengzheng, geometry, and design rules can be found on page 100 l57-5667-PF (Nl) .ptd 200405184 V. Description of the invention (98) In the system, 30. The second step is to perform layout extraction, 3 1 to obtain descriptions or feature combinations on the variation of the King of Spear King in several areas of the spanning-Japanese film. A common method is to separate the layout into several grids and calculate the structural density of each grid element. However, the present invention calculates the effective line width and line spacing of each grid. Upload or combine the calibrated process model to the simulation In the process, 3 3 — 4. Import the layout parameters of each space area into the model, and calculate the final process parameters, such as film thickness, dishing, array and step height, 3 3 — 1. Process using target and prediction The difference between the parameters calculates the process variation. The predicted process parameters can also be imported into electronic models or simulations to characterize the IC ^ 丨 wan | number, 33-2. The electronic parameters that can be calculated include film resistance, resistance, capacitance, Variation of RC delay, voltage drop, drive current loss, dielectric constant, and crosstalk noise in the interconnect.

Therefore, the dummy fill-in algorithm is particularly suitable for the adjustment of the virtual link at the interconnect level. Therefore, the interconnect measurement (R, C, L variables) is used as the chip: General measurement of the entire area, as shown in the following list Show. In other specific areas, verify the dummy circuit and fill in the added circuit performance. For example, an additional RC variable is added to 4 j of the signal delay variable to determine the timing limit of a particular path ^ meets the circuit specifications. Similarly, '彳 uses both clock twist and string ^ ^ to determine whether the circuit will operate properly.纟 In this method, rc (or. From the C standard can be used as the first pass evaluation to add a dummy fill. By selectively performing a simulation for a specific signal or a certain area of the chip, the next repeat operation can be performed. Adjust the configuration of the dummy fill.

200405184 V. Description of the invention (99) Table 1 Electrical measurement of dummy filling and adjustment of m-type measurement and star measurement type application nozzle 逋 Inner ridge line BCD, gasification layer dummy infill capacitor (C) Inner ridge line BCD, Gasification layer dummy filling, metal layer dummy filling inductance (L) Interconnection high frequency (BCD, gasification & metal filling) Signal delay circuit loop, wiring, specific line twist 1; clock clock crosstalk The results of the models and simulations described in this section of the low-level engraving sensing circuit of the communication circuit are a full-chip prediction of% range and electrical parameters and performance applied to the new IC design, and how to improve such parameters when adding dummy filling D. The cost function of the dummy filling calculation rule uses the cost function, 3, 5 to measure how the original IC design or known dummy filling structure can achieve the desired film thickness and electrical parameters. When film thickness variation becomes common In the case of electrical problems, the electrical performance will change between the generation of technology and the design group. As described in Section C, the interconnect measurement (RCL variable) can be used as a general amount of overall performance of the chip. Specific areas need to simulate the effect of the circuit performance by adding dummy fills. For example, the measurement of the signal delay variable will add an additional RC variable to determine that the timing limit of the specific path meets the circuit specifications. Similarly, the clock rotation and Crosstalk noise to determine whether the circuit will operate properly. Similarly, voltage drop and drive current loss can be used to determine whether the circuit is

Η 111 1 iil 1057-5667-PF (Nl) .ptd Page 102 200405184 V. Description of Invention (100) will work properly. In combination with a low dielectric constant, in this method, RC (passes the evaluation once. The configuration of the circuit mold is performed in a certain area. Predicted or simulated parameters are changed. Generally, the configuration is filled into the configuration and touched. Levy processing. Cost ^ The sample plot can use the dielectric constant or effective dielectric constant = to determine whether the circuit will operate properly. "It can be used as a scheme to add a dummy fill, and can be used for specific signals or chips in the next place- When a person repeats the operation, the electrical and film thicknesses of the dummy fill are adjusted. Using a certain cost function, the desired film thickness function can be as simple as a check value or as complex as being minimized in a quadratic system. The process and electrical examples will be considered. , The function that can be minimized = (LW, LS, density) delay II reverse II noise Rtr 'CL) function Rtr' CL) / Ctotal, L, Rtr, TΓ, 1 degree non-uniformity criticality Consistency and non-uniform electrical performance that can be used in a well-filled dummy fill-in • Thickness of non-uniform electrical performance = RC II delay = (R, C, L, torsion = (R, C, L, noise) = (R, c_ple where R = interconnecting resistance C = interconnecting capacitance L = internal Line inductance Rtr = Drive resistance parameter will be obtained according to the desired type of target, how to make the special electrical performance specifications ^ whether the number exceeds a specific film thickness' variable includes non-f pre-electrical effects. Column parameters i; The cost function is the function surface of the function. Page 103 1057-5667-PF (Nl) .ptd 200405184 V. Description of the invention (101) Ί; = signal rise time G = load capacitance c_ple = interlayer coupling capacitance ct〇tal = total capacitance (Coupling + Overlap + Edge) 1 = Interconnect length This cost is a quadratic error function U based on the weighted sum of the non-uniformity of the process (thin film thickness) and the variation in electrical performance, where electrical performance is taken as Multiple sets of measurements: RC, delay, twist, noise.

ErrorT = (T -Τ target ± actura1

ErrorKP = (EPtarget, u 1 actural U = (Er rorTT · · ErrorT) + (Error where the vector of the film thickness measurement actual or predicted vector of the film thickness measurement: the vector of the electrical performance measurement = actual Or predict the vector of electrical performance measurement 1 = row vector of film thickness error _lrorEP = row vector of electrical performance error U = quadratic error, a quantity value, minimized-epq

EP

• K2 · ErrorE target

actura 1 FP l 1 target FP ^ 1 actura1 E r r o rT # I = diagonal matrix, weighted along the diagonal components from 1 to q Total film thickness measurement

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〖2 = diagonal matrix Wspi 〇Κ2 = 〇〇〇 ^ Angle component weighted from 1 to! 3 Total electrical performance measurement 0 w ^ ^, can include each signal line or area of the chip .. You can easily adjust the film Thickness vector weighting moment: domain J uses this method Φ _ correct quadratic error to minimize? (Class I and II ;: Provide the overall crystal connection into a large-scale film thickness vector, and for the chain-like negotiation in this gate, adjust the weighting parameters appropriately). Electricity has different error functions in different regions. ^ Is used to weight the center function of B. Here, this weighting parameter is usually kernelized according to the most '4 skins / ditanization / degrees. Such adjustments can be Kntized component adjustments, automated, or via weighting systems.

Although the steps in Figure 7 have an impact on the configuration of the dummy fill, the steps in sub-34 do not make the decision about the size and configuration of the dummy fill in the layout. First provide information on process technology and acceptable design variable standards ’to generate a set of rules for dummy filling of metals and oxides. Figure 丨 6 shows a detailed flowchart of this step in the planning dummy filling rule. Process technology > 5 Where can include the nominal value of the metal layer thickness (nominal value) T,

1057-5667-PF (Nl) .ptd Page 105 200405184 V. Description of the Invention (103) The thickness of the interlayer dielectric layer (ILD) above or below the metal layer Η, the dielectric constant ε and the conductivity ρ of the metal layer. Design criteria may include the proportion of acceptable distortion in the interconnect RC delay and / or crosstalk noise. Enter these parameters, 3 8, and the extracted layout parameters, 3 7, and enter the dummy to fill in the rule generation steps. 34-1 〇 When a standard or the level of a standard is in a set of characteristics, such as capacitance, line width, line After the pitch or density is specifically confirmed or standardized, the standard interconnect structure '3 4 -1 is calculated. Generate a form for each standard interconnect structure found in the design, 34 -1-2. In the subsequent loop (34-1-2 to 34-1-9) Φ, a dummy filling rule is generated to combine a specific line width and line spacing in a known area. Repeat this form for each metal layer in the design. If the technology changes, a new rule list is created using the modified technology and design parameters. ,

The generation of the dummy filling needs to first select a range of line widths and line spacings across all targets in a known layer '3 4 -1-3. Calculate the electrical parameters (such as resistance (R) and capacitance (C)) of all line widths and line spacings and / or electrical measurements (such as interconnect delay, voltage drop, drive current loss, dielectric constant) Or crosstalk noise), 34-1 -4. Calculate the proportional change of electrical parameters based on the dummy fill in the structure and size range of all line width and line spacing, 3 4 ~ 1-5. Take the largest dummy and fill in the size ‘3 4 -1 — 6 to meet the level of distortion and distortion, 34-1-8. Based on the results of all such calculations, a dummy fill-in form is generated for each metal layer in the design '34 ~ 1-9. Figure 17 shows a sample of a dummy rule form. The form shows the maximum dummy line width (or the width of the filled area) as the inner line width and the space between the lines.

1057-5667-PF (Nl) .ptd 200405184 V. Description of the invention (104) '一 ^ distance = function. The dummy filling rule is based on the width of the interconnect, the width of the fillable area, and the electrical rules (such as the maximum capacitance variation of 5% during additional filling). This sample rule form is suitable for metal dummy filling. Each metal layer needs to generate a new form, which is the number of technical parameters and performance measurements / standards. 0

Figure 18 shows the flow chart of the operation of the dummy fill size and configuration calculation rules' 34-2. Metal and oxidation dummy filling calculation rules use filling rules, 34-; 1-7, design rules, 37, and layout files, extracted pattern density, and CMP process variation models, 38. Use computer-aided design (CAD) tools or function databases to retrieve the area pattern density, 34-2—1, to obtain information about the features in the layout. Obtain the coordinates of the target and calculate the area of each target in the layout. Then calculate the pattern density of the small square window, the general side length is 40 // m to 100 // m. The effective pattern density of each grid is calculated in the dummy filling algorithm, and the grid is also marked as a block, which is an elliptical opening set with a flattening length L, 34 — 2 — 2. Calculate the film thickness variation for each block, 34-2-3. The adjustment of this calculation rule also includes the variation of electrical parameters. Specify the order of block filling according to the non-uniformity of the predicted film thickness of the process model, 34-2-4, where the process model is an effective pattern

The function of j degree is also a function of the line width of the patterned structure and the gastric spacing in the trench CMP process. When performing a dummy fill, ‘select one block at a time according to the order, which order is determined by the non-uniformity of the film thickness in the block 3 4 — 2 — 5. Calculate other physical parameters for all targets in the block, such as line width and line spacing, 3 4-2-6. Some flexibility is allowed in the calculus rules, which can be filled in based on the dummy

200405184 V. Description of Invention (105) The rule uses a single dummy to fill in the size and pattern or select various sizes and shapes. Since a dummy fill has been configured in a block, layout extraction is performed to update the density, line width, and line spacing parameters, 3 1 for recalculating process and electrical parameters, 3 3. Using the cost function, 3, 5, change the dummy fill solution to meet the desired criteria. If so, execute the next block, 34_2-4, until the block. The dummy fill-in algorithm operates on each layer of the interconnect. The dummy fill adjustment is generated in two layers, one is the metal layer, and the other is continued at each level of the interconnect. If all blocks are restricted, the confirmation of this design can be completed, 36. The figure shows the dummy fill-in replacement and size calculation rules and details. Select an object in the block, add a dummy fill, and. Use the CAD tool to obtain the bounding box of the selected target, 34-2-7-2. Calculate the length and width of the target, and calculate the distance closest to the target in each direction,. Calculate the type of dummy filling for each target, such as metal layer or oxide layer, 34-2-7-5. In the mother of the block, the dummy filling structure is added according to the two requirements. 34-2-7-6: Complete all levels and fill in the oxide layer, which conforms to the 18th and 19th figure 34-2-7- 1 34-2-7-34-2-7- (1) (2) The dummy filling form is by no means more flat than the design standard. The dummy filling is performed according to the dummy filling rule table. Filling rules also determine the optimal size and pattern for specific targets in adjacent structures. Figure 20 provides two samples of dummy filling rules to determine the size and pattern of filling. Provided in Table 1 in Figure 20a Φ

1057-5667-PF (Nl) .ptd Page 108 200405184 V. Description of Invention (106) As a dummy filling form for adjusting the size of the dummy filling. LW is the line width, LS is the line spacing, R is the resistance, and C is the capacitance. Table 2 in Figure 20B provides a dummy filling form for adjusting the dummy filling pattern. The size and pattern of the array dummy filling target are integrated into a dummy filling database, 34-2-7-1 0, to adjust the design to the new IC design technology. Users can skip the selection of calculation rules for size and pattern, including the parameters selected in the technical design rules sent from the beginning of the calculation rules.

The dummy filling rule checks the area close to the selected target, and a reasonable distance from the target is maintained according to the dummy filling rule of the metal layer. Add the dummy structure of the oxide layer according to the same rules. When any of the restrictions are violated, the structure of this target will not be filled in, 34-2. When any restriction condition is not violated, the dummy filling is arranged in a hierarchical manner to adjust the layout in a more efficient way. 3 2-2-7-8. If you do not consider the size of the layout file, you can directly add each dummy entry in cloth 1, and each entry has its coordinates. This has a verification step, 32_2 —7 —9, to confirm whether there are any other objects in the block, and if so, continue this process. If there are still other talents in the block, then select the next bid, 3 2 — 2 — 7 — 丨, and go through all the processes until all the bids are processed.

_ Figure 21 shows two different dummy filling patterns. Figure 21A and 2 1B /, the dimensions of the filled target are different, and they have a similar density, showing that the size can be provided when the dummy fill is adjusted Alternative degrees of freedom. As mentioned above, the “virtual filling system” can provide users to select the filling type (ground or floating), size, and shape of the filling pattern from the database, or select the dimensional calculation rules in a variety of ways, and fill in the data based on the dummy. Rules automatically choose to fill

200405184 V. Description of Invention (107) Entry structure. — F. Hierarchical dummy fill-in units and unit configuration In terms of process flatness (eg, CMP and ECD) and electrical effects (eg, minimizing capacity across interconnects), dummy fill-in areas typically include several small targets. The disadvantage of disposing dummy fill-in targets on the chip is that the file size will increase significantly. In the present invention, units of various sizes are produced to replace the placement of small dummy fill targets on the wafer. This method requires an additional unit database. However, due to the generation of the unit database, adding a dummy fill _ increased file size only occurs when the unit is allocated. In addition, a hierarchically generated database of f units can reduce costs. Although not necessary, this method has better calculation and storage efficiency. This method is performed during the layout of the unit, 34-2. Figure 22A shows a unit, including two dummy fill-ins with dimensions of 1 // m X 1 / zm, with a pitch of 1 // m, 94. Therefore the cell has one column and two rows, and the cell size is labeled 1 X 2. In order to form a 2x2 unit, another 1 X 2 unit is arranged above the existing 1 X 2 unit to form a new unit, 95. Similarly, the following steps can be used to form a 4 X 4 unit (as shown in Figure 22A): Step 1: Form a 1 X 2 unit, 96 Step 2: Place another 1 X 2 unit to the right of the original unit to form One 1 X 4 mouth early one Step 3: Configure another 1 X 4 unit above the existing 1 X 4 unit (form 2

1057-5667-PF (Nl) .ptd Page 110 200405184 V. Description of the Invention (108) X 4 Units)

X 4 is earlier than the existing 2 X Step 4: Configure another X 4 unit) One unit is formed by the knife level, so it goes down from the upper unit (4 X 4 unit in this example), and each level comes from For smaller units. Continue to form until the final unit is reached, which includes the actual dummy filling structure. The advantage of this method is that it can significantly reduce the file of storing dummy filling information. It is especially suitable for adding dummy filling in large blank areas. You don't need to save the coordinates of each dummy, you only need to store the unit size and unit coordinates. . The grading method is due to the need to greatly reduce the file size, and can be edited in the layout to read the file faster. In comparison, a unit represents storage: a single dummy fills the memory amount of the target or unit coordinates. A single target has the same amount of recall, because both require the same amount of information: For a single two dummy filled target: the boundary block coordinates (χι ,; x2, y2) For the unit: the lower left coordinate (Χι, yi; unit size m χ η) 2 • If the units are arranged hierarchically-4x4 units require 8 units of information, as shown in Figure 23. In this example, each 4X4 unit contains two 2X4 units, 96, each 2x4 unit contains two 1X4 units, 97, each 1x4 unit includes two 1x2 units, 98, and each 1X2 unit contains two independent units, 99 units Calculate 8 units of information for all required units or targets. It must be

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V. Description of the invention (109) For the independent level method, 16 sets of independent units will need 16 marks to describe the four sets of boundary block coordinates of the units. :? In terms of 'when the unit size grows (that is,' fillable area '), the amount of memory saved by using the grading method will increase;. The storage capacity required for a ηχη unit that does not use the grading method is n204. Four sets of coordinates are needed in the stomach to define each dummy fill. However, if the grading method is used in the dummy fill / system ^, the required storage amount is linearly related to η. Generally speaking, the required storage capacity of a group of mxn units is linearly related to η (or m).

If m or η is a power of 2, it is equal to 4 (representing the amount required for a single unit). _ 2 4 is a step-by-step detailed flow chart showing the aggregation and configuration of hierarchical dummy filling. Fill the dummy into the rule table, 4 4-2-7-6, and the target database, 34-2-7-10, and import them into the configuration calculation rules. Select each dummy filling area '34 -2-7-8-1, calculate and determine the number of dummy filling targets of the size that can be configured in the filling area, 34-2-7-8-2. Generated using the input parameter ‘34 -2-7-8-3 ’which defines the dummy fill-in parameters, 34-2-7-8-4, single

Meta allocation calculation rules can be formed, 34-2-7_8-6, various sizes of dummy fill in the unit database, 34-2-7-8-5, select the largest size to fill in the selected area and configure , 3 4-2-7 _ 8 _ 7. Separate the remaining dummy filling area j into a new area, 34-2-7-8-8, and use calculation rules to decide whether to return or not, the area that can be filled in, 34-2-7-8-8. If so, select a new area, 34—f — 7 — 8 — 1, and repeat the original configuration process. If not, the configuration of the dummy filling unit is completed. If other targets need to be filled in, the check operation is completed, 34-2-7-9, figure 19.

1057-5667-PF (Nl) .ptd Page 112 200405184 V. Description of the invention (110) g. Applying the dummy filling method described in this process is mostly used in the grinding and electrochemical deposition process, because it maintains a layer of thin film Flatness is a very important issue. The dummy filling can be combined with the trench process flow to improve the flatness of the thickness of the copper filling film during electrochemical deposition (ECD) and chemical mechanical polishing (CMP). It will be used together when forming a single or multiple interconnects. Two ECD and CMP pattern auxiliary models can be used for 4 main * on * multiple levels of effects. This ditch; === The following functions are connected between adjacent interconnected levels:), or as a network service to improve • layout capture • pattern attached model measurement and prediction • IC design dummy fill in the size and configuration • Optimization of film thickness planarization • Minimization of electrical effects. Improve the film thickness in the two-process process so that it can be used in ECD or CMP processes or planarization or electrical performance. In the application of trench process,

IjECD and CMP process steps. IC layout using the method shown in Figure 14 and described in Section b. The steps and methods shown in Yu Di ^ 's measurement are shown below. .Combined measurement method is to perform the prediction of the steps shown in section c in Figure 14 in a manufacturing process-* step and two: process' and ^ check the critical thickness with the form described in section d; flatness . Wo 4 o'clock check or use cost function

V. Description of the invention (111) The comparison of the results and the expected thinner Using the steps shown in Figure 16, through the second sub 4 = the difference in electrical performance. The calculation rules are filled in falsely. Use this method, section e, and "sections" to apply to each layer, so that the non-makeup of the film thickness can be filled into the variation of the applicable parameters, such as resistance, thin; electricity: "Minimization, will minimize Power consumption, permittivity, or capacitance. 13: Voltage drop, drive current loss, including dummy applied between layers to create multilayer interconnects. Fill in the turtle's ΪΓΓ with UHr and 65nm technology. The dummy filling is used to achieve better process integration, and the thickness, thickness, and thickness are improved. To :: Most of the conventional steel material filling systems are electrochemical deposition methods. Pre-made additives, such as catalysts, flatteners, or inhibitors, improve the mechanical properties of the metal layer. It is changed to # 卩 — again and again. Degrees. Nutool has been rounded, and pads have been used to introduce Lei Qiao ^ from% to _ _ ^ ^ Wait for the plating solution. This contact flattening technique = point c domain and comprehensively flatten the copper film. This Another advantage of the method is that it can reduce the thickness of the handle, reduce the thickness of the copper, and reduce the need for subsequent CMP. In addition, the copper is set to 0, Wei Ti, the second = combined with electrochemical mechanical deposition (ECMD) to improve:-: Application: spoon,: consistency. The dummy filling method can be used with the process shown in Figure 14 of the ECMD system to measure the entire model = model 'and add the model to the process as shown in Figure 15 to predict the film. In terms of improving the flatness of the film thickness, dishing, can be developed using NuTool, internal or other third-party suppliers:

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Network, external network, or internal to provide the following functions: ECMD model and virtual filling method to achieve this method can be used on the network (Internet) and as a network service, • layout capture • pattern Auxiliary model measurement and prediction • Dummy filling size and configuration of IC design • Optimization of film thickness flattening • Minimization of electrical effects can be achieved in Yueliang. After the layer is not copper, the problem is the damage, the dish is adjusted to a low overall 2 feature wafer as a thin film layer as the number of automatic changes in the ECMD process trench process, it is not easy to manufacture the barrier cover, and it is not easy to maintain the copper. CMP step horse traps, invasion of insects, and the filling of the structure wafers that can be layered in this layer (including the development of the overall crystal thickness flatness interconnecting level will be filled into the dummy. This method improves the film thickness flattening. There are many issues for introducing low-dielectric constant dielectrics to overcome the low-dielectric layer, and to complete its dielectric constant in all integration steps such as the barrier cap and CMP termination layer. The yield of many low-dielectric materials is questioned. The soft characteristics of the low dielectric layer will lead to SCMp loss and subsequent electrical defects. The low dielectric material layer is added during the interconnection process. The characteristics can achieve the expected effective dielectric constant and reduce capacitance. The attachment of the pattern can be based on The effective dielectric constant applies the wafer state model and electrical parameters). Use the film model to predict the variation of the effective dielectric constant, which is a function of 碟, p, or 文. When reporting the material for the dielectric lightning, use the pattern I to characterize the result and add it to the low dielectric layer to minimize the effective dielectric. It can be used in the Internet (Internet, external network,

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Or internal network) • layout capture or as a network service to provide the following functions: pattern attached model measurement and prediction and configuration of the dummy IC design fill the size of the thin film thickness flatness minimizes the best electrical impact This can improve the structural characteristics of the low dielectric layer, and improve the development and integration of the process steps using the low dielectric layer.

This application can be combined with dummy filling methods to change the low dielectric layer's properties, structure, structure, and electrical characteristics, and promote planarization during CMP, such as the trench process shown in the figure. The steps to introduce the low dielectric layer into the process flow are similar to those in Figure 7. This application requires the measurement of the ecd, ecmD, and CMP models of the low-dielectric layer, 34, as shown in Fig. 4 and online status. This should = also need to adjust the electrical model, 33-2, to calculate the variation of the effective dielectric constant of the overall chip. Enter the expected effective dielectric constant data and other design parameters, 32, to the cost function to indicate the dummy filling strategy to optimize the electrical characteristics of the low dielectric layer and improve the flatness of the film thickness in the trench process. Structure and Operation The elements (components) containing the present invention are built in software (such as Java, Tcl, Basic, SQL) and modularized. You can choose whether to use all the elements completely when the configuration is filled in. For example, the dummy filling database can include only one type of dummy filling target, and the automatic dummy filling calculation algorithm can be optimized based on reducing process variation without the need for electrical models or simulations.

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200405184 V. Description of the invention (114) Dummy arrangement of landfill Figure 26 method. Users, browsers, and serial electronic layout design Generally speaking, the calculation structure of the dummy filling method will be described below. A preferred software structure is shown to form a dummy filling square 100 ′ via a graphical interface system (GUI) 101, such as a netcom to the system. G U I, 1 0 1, allows users to select and upload reports to the virtual system. 'The fixed device of the format can also use the computer with the electronic interface to pass the virtual space to the following electronic media. Use this media from the storage state, ruler transmission, or fill in the schedule and pre-format: as in this section Definition and use, allowing users to select, upload, or transmit from other media, expected design rules, and special effects described in design files. The user selects the process and electronic model from a server, or transmits or loads the model from another source or computer. Users can also use the server's dummy filling target database to select dummy fillings and patterns, or source or load models from another electronic medium. Users can also use this interface to review the layout results, and / or view the final overall chip layout. Measure the film thickness and / or electrical parameters. This result can be a bar graph or other statistical image & full wafer image of wafer status, or a film of the overall wafer film thickness, dishing, and erosion process in real time at a certain point in electrical parameters during the process steps or processes • Variation of the electrical parameters of the overall chip, such as a film of film resistance and capacitance variation • Numerical form 1057-5667-PF (Nl) .ptd Page 117 200405184 V. Description of the invention (115) This GU I, 1 0 1, and A series of software elements, services, or functions, 10 2 '(here marked as a service module) are connected to manage through the system to the database, 105, and core computing processes, 103, and Data stream. The service, 102, is modularized and imported to start the core calculation process, and 03 is to execute some calculation rules, integrate and format the content displayed in GUI. An example of this element is Java or Tel language, which makes it easier to interact with a database embedded in the SQL core and a GUI using HTML. Such elements can also start the mathematical process and perform calculations to determine the correct imaginary | fill in configuration in the layout. This service module, 102, is connected to the calculation core of processes and functions, 103, and executes dummy filling calculation rules and complicated calculation procedures, such as manufacturing process and electronic model and simulation process. This core also calculates the effective pattern density. This calculation includes instructions, data, model parameters, prediction result tables, images, or image formats, and metrics for files in the file system. This service module, 102, can also be connected to the electronic IC design software, 104, which deals with the poor layout of the layout, such as the position and coordinates of the design target, and determines where the dummy fills in the unit configuration. Database, 105, connected to the service module via S0L instructions, 〇〇2, I 乂 management system data, such as a dummy fill in the database target; user profile, φ includes limited permission and favorite content and presentation methods ; User data 'includes layout extraction data, previous layout design files, model parameters of specific tools and clothing, and overall chip prediction results such as surface topology, resistance, and capacitance. The database used in the example can be 〇racle, θθ

200405184 V. Description of Invention (116)

Informix, Access, SQL Server, f0. The file system, 106, is connected to all the elements 101, ι02, ι03, 104, 105 to receive data and save it as a file. If blocks A, 107 and β, 108 are located in J Brain II 'in the figure, this system and system can be configured independently. If block A and block B: are on different computers and are connected through the network ^ bit-the configuration of the server side. Then, it is sufficient to suspend the client as described in this section. It does not fully reveal the operation of the dummy entry, ^ ^ ^ ^ ^ ^-Nai c. This section deals with three types "Dan 但-. Cheng: if ί is a better way to compose operation and transmission functions. Set / as shown in the m-th diagram, where all the elements of the second type become a 1-crossing 0 6 system located in ^ 09, and 1 single computer acquisition. (101) is located in a feeder architecture of a client, a server or a multi-feeder;: m〇2: i〇6). This connection mechanism can be via the Internet, Intranet, or Extranet. The client or user11 and the feeder can serve one or more groups of customers. As shown in Figure 28, it is the client. -The server model group m2 is connected to the other computers containing the system-or more by our network from the network '114'. For example, a design company can use the Γ: electricity: iV: fill method by dummy, but at the same time remotely use rf, commissioned manufacturing, in which the computer stores a process model and model parameters provided by a wafer foundry ry, 11 7. This combination

Page 119, 200,405,184 5. The invention description (117) also includes a connection to the dummy filling method type and analog processing, 117, which can be stored in the electrical mode of the two suppliers 1 1 8 and via the network, 4,相 连接。 Phase connection. State or server group, in order to make the virtual filling method serve the whole world, use the client # = client shown in Figure 2_28, you must send the virtual filling service. The operational structure is here. Second, the network transmission function is developed into a network-type service. Through the network, the filling method and the Internet can be reached. It can be connected to it. • It is a general structure, which is suitable for providing fake filling services through the Internet. In this combination, the user, 100, warp, brain, 121, accesses a server computer or server group, 123, Dokko network (such as internal network, external network, Internet), 1 ,, ", Second operation of dummy filling. When connected to the network, 2 2, clients, 12 workers, upload or send layout files or files to the server, 123, can also send design rules and the virtual information on the server to fill in the reference information used by the system ^ 料 ^. The dummy filling system, 1 2 3, handles the layout information, configures the dummy filling target's, and connects the layout file via the network, 1 2 2 and returns to 100. The example of this architecture is a dummy providing a network service format. Fill in function. Soundway Service is a target for functions, content or processes and interacts with a web browser, database, or other service. In a preferred embodiment, this network service architecture enables each virtual filling function and content to be transmitted back to the user and can be modularly manufactured, combined, and added or subtracted according to requirements, so that a large use group can be updated. Use this method easily. Another advantage is the third offering

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The internet service provided by the respondent can be automatically accessed and integrated into the history j: W 矣 fixed road service. Another advantage of this embodiment is that through the development of other services on the network, it is possible to normalize the virtual filling calculation rules and effectively push 5 to 4. The best examples of this network service can be Java, Tci, SQL. It can be connected to a SQL actuation database and the core of a mathematical program. Λ lays out information based on the principle of production and determines the function of dummy entry. This service will limit and common the required input parameters, which are optional inputs and provide the parameters and data returned. This system will integrate 1 service according to user parameters and required functions. Figure 30 shows an embodiment of a dummy filling system. The user, 100, is located at a regional client, 124, and uses a GUI-type web browser to connect to the server via the network (such as the Internet, intranet, and external network), 125 " , 126. The functions provided by the dummy filling method are modules and configurable network services, 1 2 8. The filled-in network service, 128, is located in the service module, as shown in 102 in Figure 26, and can be established on the network of a third provider such as IBM, Microsoft, ARSDigUal, or bea. The application platform, this server, 1 2 7 can include web services to manage users, 100, and the profile of the company to which the user belongs, and 1 specific user to log in to increase or decrease content and functions. Some network services can be integrated through the Internet and published by a third provider. Among them, they can be integrated by a central network server or server group, 1 27. Some elements can be used as network service projects, including process models and simulations, electrical models and simulations (129), layout extraction (13), hierarchical unit configuration

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Page 121 200405184 V. Description of the invention (119) (1 3 4), dummy fill size and configuration (1 2 2), dummy fill target database (1 3 3), and design rule generation, adjustment, or publication (1 3 1). The server, 126, allows the user, 100, to create a dedicated network-level dummy fill application function that is suitable for a specific problem or purpose, and prompts the user with related problems through the use of a wizard and integrates appropriate ones from 128 service. The use of such services, 1 28, can also provide discounted or free services for the trial period. According to the needs of users, meta-services or complete network applications can be integrated into smaller arrays of services (or functions). This Shun | Why is it easy to generate a fairly modular network service to improve the flexibility of the integrated virtual setting into the application type. Figure 31 shows how to add, subtract, configure, and integrate a network-type virtual-filled network application in the 102 service module. A user logs in from a specific company, 135, a service script '136, performs license check, 137, the user is based on the target in the system: such as layout, tools and measurement data, dummy fill ^ function Wait for certification. Use this permission to initially generate a dummy fill-in web application 1 3 8. When users use this system, the service module continues to accept user rotation. If the same user loads a specific layout, 3, 9

| Footprints, '1 40, to obtain all the functions and targets of this type of layout, use the process tools, models and recipes obtained by the user to test the integration of the target link of the script integration license into the virtual filling network. Road service to produce I. The same user may select one or more sets of process tools or recipes to produce a production-process flow, 143. Service script, 144, followed by a beta model, and integrating such models into the process flow, 1 4 5 5. this

Page 122 200405184 V. Description of the invention (120) The process flow becomes a part of the dummy filling in network services, 146. This interaction will continue when the user transmits the Qingqiu to the temple server and receives a service response, 1 4 7. After all the components are arranged in the layout, the designer can use this dummy filling method and system in a series of crack states. In such operations or applications, as shown in Figure 32, the design specifications and rules, 148, will be transmitted to the user, 149. The designer designs and configures the components, 150, to complete the layout, 15 workers. Upload the completed IC design to the server, 152, the dummy filling method and the system to modify the IC layout and return the design specifications to the design group, 153. If = dummy fill strategy can meet the design specifications, the designer will be informed, 1 5 $. The wafer factory or wafer foundry can use this configuration method to provide dummy filling services and / or confirm the manufacturability of the layout sent by the design company.

When each meta-designer extracts and configures the components to be carried out, the entrants can immediately repeat the design for each 1C complete. It is necessary to assume that the design-central method cannot know the design components are placed in the layout ( This mode is also called real-time using this dummy filling method and system. In Section 3 3 E, 155, to Design Group, 156. When the designer sets “t 5 components” and uploads the layout to the server, “1 5 8 layouts” even if only some components are deployed, others are not configured. When the dummy filling method is used, the layout specifications are revised and transmitted to the design group, or the central layout is updated electronically, 159. If a dummy is used to determine a dummy filling strategy that meets the design criteria, ^ is 0

The Internet enables design groups from different companies around the world to collaborate on design development. This difficult task is to confirm that all designers can meet the design requirements.

200405184 V. Description of the invention (121) Is there a dummy filling mechanism? 'This pre-designed piece can be integrated into a new design specification. If all designers agree to this design specification, the system / system operation will be as shown in Figure 33-assuming that no configuration component meets the design specification, and when the component violates the regulations, a dummy filling structure is appropriately placed. When selecting the components designed under the unique design rules (such as authorized IP or design), the virtual u can be filled into the system to determine i. As a result, the virtual filling system of the present invention has been implemented as described above. This section will use the diagram Describe the results of the implementation with the test. Figure 34 shows the graphical user interface (GU I) of the Layout Manager. The user can upload the layout through an Internet browser. The web service will be based on user-defined design rules (also input through similar GU I ) Add dummy entry for proper process. Three sets of designs 161, 1, 62, and 163 are using the layout retrieval algorithm to calculate the effective density. The options provide users to use the layout capture method to calculate line width or line spacing, or upload information from other data sources 1 6 4, 1, 6 5, 1 6 6.

Figures 3 and 5 show the results of using this system's layout capture. The line width of the whole chip is displayed according to the position of the line width. Enter this information into method j to predict process and electrical variations. Figures 36 and 37 show the results of the dummy filling method and system. In Figure 36A, the metal lines adjacent to the oxidized area are shown, I ??, which uses the cmp film thickness, dishing, and surplus calculation, 31, and the electrical model of resistance and capacitance, 32, and the acceptable RC variation error Add a dummy fill of the metal layer in the range, 176. In Figure 36B, oxygen is added to the metal layer, 179,

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V. Explanation of the invention (122) Fill in the dummy and fill in it '1 78. Enlarged icon, 1 80, also shows the actual oxidation dummy filled structure 181. Oxidation dummy filling is also calculated using the CMP film thickness, dishing, and erosion calculations, 31, and electrical resistance and capacitance modes, 32 'and acceptable RC variation errors. The dummy filling system also adopts the ratio of dynamic line buffering and moving grooves in the result of the dummy filling configuration. Figure 37 shows how to use the dummy fill method and the system to adjust the dummy fill pattern to minimize the electrical impact. In Fig. 37, the dummy metal filling, 1 84, is arranged in an oxidation area adjacent to the metal line, 1 8 3. In order to meet the electrical requirements of the design, an asymmetric metal figure • I was selected from the database, adjusted in size and placed in this oxidation zone to minimize the effect of resistance. Insert the icon '1 8 6' to more clearly observe this asymmetric metal dummy filling, 1 8 7.

Figure 38 shows the G UI using the dummy filling service. In the example, a web browser can be used as the GUI. The advantage of this is that almost all computers are currently equipped with a web browser and can be standardized across two major browsers, Netscape and Microsoft. The dummy filling function in the GUI can be divided into three main types: design (19 9), manufacturing (1 91), and model (2 0 0). The screen shot in Figure 38 is shown in the header, 190, and the navigation bar, 191 '. The user has selected the t element. The manufacturing element contains sub-elements; among them, the factory, tool, wafer, manufacturing data, etc. have been selected, and the tool item has been selected in the screenshot, 192. There are three types of sub-elements in a tool item: split, recipe, and process. In this screenshot, the user has selected style, 193. The type and setting of the tool is then displayed to the user, and then 194 ° is displayed.

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V. Description of the Invention (123) Formulas with selectable types, 196, and formulas with selectable types of such tools, 197. The calibration measurement and prediction of copper and STI CMP are matched. The system configured in the screen capture pattern provides users with two process modes ^ -98. Design element, 199, uses layout manager to allow users to manage official layout and layout capture. One of the purposes of this dummy filling GUI design is to allow users to manage all the data and results provided by the dummy filling service. Figures 39 and 40 show comparison tools built into the software. ^ The tool allows the user to select and compare two or more groups, whole or part of the wafer image, including thickness, sheet resistance, total copper consumption, step /,

_, And erosion. The door is a GUI for displaying comparison tools. For example, you can use the web browser as the GUI. In this screenshot, the user has selected the overall image. The advantage of this is that almost all computers before a: yes, no, and can be standardized across two major browsers, Netscape and Microsoft. σ Do not show the GUI of the comparison tool. In the example, the network can be used as the GUI. In this screen shot ’, the user has selected the monolithic =: thickness bar image. The advantage of this is that almost all computers currently have a web browser and can be standardized across two major browsers, Itscape and Microsoft. The description is used to confirm and correct the lithographic mask manufacturing method. The area of 5 channels, (IC) i will be affected by the thickness of the film and the topological flatness of the surface, and the electrical effects caused by the fabrication of the integrated circuit. Filming 釭. According to prediction or modelling 1 (: physical and electrical characteristics of manufacturing,

1057-5667-PF (Nl) .ptd Page 126 200405184 V. Description of the Invention (124) Due to the attachment between the preset circuit layout patterns and the characteristics of the integrated circuit manufacturing process' to further predict this confirmation and correction step . This method can be applied to (a) the formation of a shallow trench insulation (ST I) structure with a high degree of plasma (HDP) chemical mechanical polishing (CMP) process; (b) the formation of single or multi-layer interconnect structure lithography, High-density plasma (HDp), electro-clock copper deposition (ECD), and chemical mechanical polishing (CMP) processes; γ c) processes and processes for forming oxidation and low dielectric layers; (d) plasma etching process and key Measurement of dimensions; (e) Lithography process including front and back photoresist deposition and removal steps 'and subsequent use of plasma etching to physically etch back' 3; features; (f) deposition photoresist and selection Photoresist material; (g is in line with expectations: rc: inch⑴ Correct the size of the mask to calculate the flatness of the topological interconnection (also refers to the characteristics of thickness and surface width, line spacing, and toilet pattern (such as material density, line The degree usually leads to the desired size of ϋ1). Non-flat surfaces and thick attachments usually cause this force and process integration to have an adverse effect. Pattern = = ㈡: Layer 1 is deposited and flattened to Shi Xi to define the circuit size " Surface or deposited on the surface of the wafer The size of the geometric pattern of the wafer surface. This example is included. The characteristic size refers to the electrical dimensions. Line width, structure spacing (such as line 200405184 V. Invention description (125) The distance between two lines in the array, or the distance between them) ), The critical dimensions of the circuit (Γη, the minimum distance between the buffer between the circuit and the dummy structure), the line armour and the column) (that is, any geometric pattern in the circuit, the geometric figure or geometric group f or other repetitive structure , As well as individual values, maximum values, and average values, that is, line arrays) (such as the smallest inch, such as the angle of the side wall, the feature height piece; the feature size includes vertical and other ruler mechanisms such as steppers (such as Trench depth). Lithography equipment package conversion process (such as mask j, used to project the pattern image to the wafer and figure wafer. The remaining equipment includes optional = path pattern conversion to cover the% round surface of the photoresist Or the thin film on the wafer is used to remove the 4 装置 mechanical device on the stomach that is patterned by the lithographic equipment on the Japanese yen. The figure 41 shows the basic shot or laser ... "If the light pipe passes through the circuit Light of pattern sign = 14: body's guiding light II-reduction lens, pairing the image: ㈣㈣The equation defines the smallest feature size that can be presented as the exposure wavelength according to Bazhong, and NA is the medium of optical deep ultraviolet; ^ The change of the parameter is in the heart of the change :: Two! In between, it depends on the process and the system, etc. The source of the improvement of the column and the special mask of the mask 4 2 shows how to form a micrometer from the design = Assist system (called _turn the functional circuit = = electronic layout design slot for physical components. This design;

200405184, invention description 026) layer, such as the transistor layer, describes the decoration volume ^ + ^ layer, which can transmit the signal to the transistor-: to the higher layer 'such as the interconnect / iL ^ m, day to day communication , And supply power to each of the chip ^ = electronic count files in the so-called order-out (tape-out) period to produce f 1 12 03 7 rules. Next, a photomask, 1238, was fabricated, and the circuit features were transferred to the wafer using a shadow tool, 1239. Many projection systems use a step-and-repeat mechanism for the secondary area of the wafer, the crystal advances: exposure, also known as the optical area, and then repeats this process until the entire wafer is imaged. The stepper can be controlled to adapt to wafer-level variations such as distortion or zigzag. Usually, the variation that needs to be adjusted occurs from the crystal to the crystal effect 'rather than to the per-crystal. In order to determine that the projection imaging circuit is located within the focal depth (D0F) of the optical device, the stepper can adjust the focus of the optical device according to the formation of test keys or alignment marks on the surface of the wafer; degrees, Variations in thickness of the sensing layer or photoresist layer. Variation usually occurs under photoresist. Figure 43 shows that the stepper can calculate the crystal-to-crystal variation, but it is not enough to improve the variation in the crystal caused by the 1C pattern attachment. The reduction lens 12018 shown above is shown above the crystal surface of Figure 43. The shadowing system shown in the figure above makes the focus length 1 20 24 conform to the test key or alignment standard. Δ round, the distance obtained. Focus depth 1 2028 determines what kind of optical axis; Zheng Ersuo ’s resolution is generated under Mfs. According to the Ray 1 eigh equation, the pair can be expressed as:

As = earth yttrium 2 λ

1057-5667-PF (Nl) .ptd 200405184 V. Description of the invention (127)

Is the light wavelength, and NA is the diameter of the optical device. The parameter K ^ is about ^) in the outer line or DUV image system, which is the same proportion of the change of the characteristic 夂 Zhao. v f 豕 surface spear, or when using oxide or copper dagger, when using ECD deposition steel

Variation within the crystal, 12030. If the wafer-level I focal depth, the mapped feature 1203 may not be able to correctly correct the key dimensions of the job plan, forming an error, and forming 3 on the circle, which will have a negative impact on the performance of the device. As described below, f-adjust the mask design to obtain the imaging size that is more suitable for the design. The following diagrams will describe the causes and results of the process-related c pattern attached. The lithography process is repeated at each layer throughout the semiconductor manufacturing process. The technical scope described here is particularly helpful in the trench forming process for forming metal wires (interconnectors) connecting device components. Connection between multiple floors

Place signals and power between components. π & I Figure 44 shows the trench process flow of the interconnect layer. The process starts with the CMP planarization surface 1 204 0 after its interconnect layer (N-1 layer). Shen 2 Dielectric material (such as oxidized or low-dielectric material), 42, to connect N-1 and N before insulation. (The interconnects are called interlayer dielectrics or ILD ^. Although the pattern is attached to the ILD by the CMP flattening step 'because of the underlying features, this step is optional and not shown in this example). A photosensitive layer (such as a photoresist layer) is deposited on the wafer surface 1 2044. The lithography system maps this crystal and uses the process shown in Figure 41 to define the current circuit characteristics of the current interconnect layer ", and the heart organ selectively removes the photoresist 1 2 0 4 8. Using plasma Etching selection

1057-5667-PF (Nl) .Ptd Page 130 200405184

Alternatively, remove the oxidized region 1250 and then remove the residual photoresist 1250. A barrier layer 1 20 54 is deposited and a metal such as copper 1 2056 is deposited in ECD. CMP grinding was used to remove the selective copper area and the barrier material 1258. At this point, the formation of the Nth layer of metal = connection is completed. Usually, the pattern-related unevenness will be transferred from the lower layer to the covered interconnect layer, which is caused by the variation of LI) and photoresist thickness during lithography.

As shown in FIG. 45, the electroplated copper deposition (ECD) is a step of a copper trench forming process' for depositing copper metal in the interconnect structure. This purpose is to completely fill the etched trench area by a hole-free method, which can minimize the thickness and surface topology of the deposited copper #. The pattern attachments present in the ECD are due to variations in flat surfaces. As shown in Figure 45, it occurs at a narrow line width 'Cunar thickness Tnar ^. There is a difference in thickness Tdifference between # 12070 and the deposited copper thickness Dingxin 2086 which occurred in the wide line width 12082. The variation in film thickness in the chemical mechanical polishing (CMP) process can be divided into several types of ingredients: batch-to-batch, crystal Circle-to-wafer and crystal-to-crystal. Generally speaking, the more significant component is the pattern complex crystal level. The crystal level variation is often caused by the different layout patterns on the wafer. For example, in the CMP process , When the underlying metal patterns are different, even if the regional

g Tanned surface 'will still cause large-scale changes in the thickness of the post-CMP film. The following figures show the variations that occur in copper, oxide, and shallow trench isolation (ST I) CMP. For the grinding of the oxide layer, the main source of the variation is the variation of the pattern density inside the crystal cube, as shown in Fig. 46A. The metal wire 1201 6 is located on the left side of FIG. 46A, and is more right in the plane direction of the integrated circuit

1057-5667-PF (Nl) .ptd Page 131 200405184 V. Description of the invention The metal wire on the (129) side 1 2 1 0 8 has a low density composition. In this example, the pattern density is defined as the ratio of the area of the raised oxidized area 1 2 110 by the total area. The area of this area can be some length, such as the square of the flattened length. This flattening length is usually determined by process parameters such as the type of polishing pad, CMP tool, polishing chemistry, etc.

Figure 47A shows how the density of the underlying pattern affects the variation in film thickness. Figure 47B plots the variation in film thickness for each density pattern. For the square area defined by the flattening length, 12132, the higher the characteristic density of the lower layer leads to the larger film thickness variation 2135. The designer usually needs meals | try to maintain the density at about 50% 12133 to improve the flatness. After filtering the density of the design layout, the effective pattern density is calculated for each area of the crystal cube. Usually, two different density filters are used near the area. Figure 46A shows the variation caused by the topological features 12 106 and 12 108 on the surface of the area (step height) 12104 and the overall unevenness 12102.

When fabricating a shallow trench insulation (STI) structure (as shown in Figure 46B :), depositing dioxide in the trench with the name of carved stone 12111, and using cMp tank? b Electrical insulation device. When the interlayer dielectric layer (il) is being researched, the pattern of the lower layer of the insulation trench causes the deposited oxygen cut to produce $, which is the result of the two. If a nitride stone invades 12H, the layer may be damaged. "Under the Bare" and suffered this ^ widening the trench and exposing the silicon layer 1211〇 while the damage #

= Trap will lead to 2 topological variation and subsequent lithography ns 2, pattern density is an important feature of topological variation and other CMP effects P

200405184 V. Description of the Invention (130) Figure 46C shows the effect of grinding the embedded metal features (such as lines 12122 and 12126) to the dielectric (such as stone dioxide) 12120 in the CMP process. In terms of metal grinding, the calculation of the 'pattern density' characterizes the overall pattern attachment; however, the physical layout effects, such as line = and line spacing, also need to be determined. Two types of unwanted effects are caused by the pitting and invasion of the metal trench process. Measure dish depression 121 24 as the metal thickness at the difference between the edge of the wire θ and the center and center °: The last name 1 2 1 2 8 is defined as the thickness of the oxide layer above the metal wire, which is usually located in the wire array and is not patterned in the vicinity. The difference in the thickness of the oxide layer in the area. Another unwanted effect is the residual copper, 2, and 3, and the electrical layer (or upper area) of the shoulder I is removed and remains on the wafer after polishing. In general, the process engineer sets the grinding time to remove all copper deposits. For the patterned area where copper is removed first, dishing and erosion will continue to occur, thereby increasing the unevenness of the wafer surface. Figure 47 illustrates another embodiment of the relationship between density and flatness. …, The CMP process of each description will cause the surface to be uneven, and will adversely affect the lithography. The techniques described here can be applied to any pattern-related process. ECD and CMP are two types of processes that cause unevenness. Although this process will be used to illustrate the method of the present invention, this method can be applied to any process related to the f pattern. η ΐ4 』! ? Shown is the effect of pattern attachment on the lithography process. Fu Zhizheng's width (FW) is the minimum size of any target, etc .: and: the layout standard & of the ruler, such as line, rectangle, polygon, (cd) is the minimum size of any feature in the layout, also

200405184 V. Invention Description (131) is the smallest FW. The mask 121 84 displays two features 12 180 and 1 2 1 8 2 with the same feature width, and is used to map to the wafer surface 1 2 1 9 2. When performing lithography, the internal unevenness of the crystal cube 12192 due to the process-related pattern attached (as shown in Figures 4, 5, 46, and 47) will result in a difference in film thickness between the two mapped wire widths ^ 12188 and '12190 ( △ h) 1 2 1 8 6. In this example 1 2 1 9 4, the mapped wire visibility '12190 is much greater than% 12188. Although the widths of the two mapped wires,% 12188 and '12190, have the same design and consist of

The non-flatness of the surface layer produced by the photomask will cause significant dimensional differences, and g will affect the performance of the IC. The process related to the pattern attachment can also be applied to the lithography itself. The feature degree usually affects the ability of the mapping feature to reproduce the design. In Figure 49: The cover 12214 has two sets of characteristics: one is high density 1221 and the other is low density. When the features on the wafer are quite close to each other (that is, the special 1 is added), the diffrecti0n pattern And its changes will vary in size from design. Even in completely Hiragaki / 12216, the mapped feature size (such as line width) (w + M) ® + + Δ2) 12219 may vary 1222. Topology variation may occur on all components of the chip, # $

% Predict the overall wafer. In some examples, the emphasis will be on the characteristic circuit: on the unit's secondary network. Overall Chip Prediction ”Any topology variation in the network. The critical relationship of the 1C pattern can be used to verify that the micro is consistent with the design. If not, then adjust the design layout and

200405184 V. Description of the invention (132). The shadow model can be combined with the etch model to predict the size of the litter size. The characteristics of the toilet (such as visibility, depth, and side wall angle) are captured electrically, and specific errors are fine-tuned. Therefore, the electric shadow region Γ is one of the method embodiments of the Guang 2 Er Ming. number 5. The man in Figure A, L. Ghost (12310, 12400, 12600w a boat TΓ〇 + times, 1 2 80) will be detailed below. ,-/ & = Counting materials in electronic format such as graphic data stream (GDS) format = 280 Λ Λ Defines the position and junction of each-layer in the integrated circuit, although the relevant characteristics of the μ slave process change But the more efficient archives of Zhao Dan's paintings are quite large. The layout extraction 1231〇 process will benefit 4 = majority, such as feature width, feature space, and density summary 1 C set grid (secondary part). Layout capture is not necessary, but it helps to limit the number of different materials. The next section details how to perform layout capture. 1 9 9 7 Π In the prediction element (Pr) 1 2 3 0 0, the layout characteristics of the design correspond to the parameters from 1 ^ 10 to the wafer topology (Δ1ι) 58, such as film thickness, dish

, K-etch, and overall loss of copper. The process model (model) can use this information or a set of process models Mp (such as ECD and multi-step iCMp manufacturing or more complex process flow) 1440. When the heat expressed by the layout features 2 is manufactured in the modeling process , Predicting or simulating the process results and the corresponding variations of the moon. The variation of the final manufactured component can be physically measured, such as' using optical measurements on the film thickness or wafer surface profile to determine the actual topological data (such as dishing, or step height, and erosion or array twice ). Calculate the surface topology of the wafer level of the overall wafer and the electrical parameters related to the expected specifications of the car parent 丨 2 5 8 0, at the same time on the cube and multiple mu l 057-5667-PF (Nl) .ptd page 135

V. Description of the invention (133) Performed in crystal. The predicted chip chip U600 is input to the wafer surface topology 12580 into the lithography model. The mapping feature size variation 1 2580 corresponds to a specific lithography tool grid and equipment to minimize shoes 2680. This corresponding step can be used to calculate the feature size variation based on the tool's surface topology (such as the 88th inch (M4 and depth of focus (Df), root optical approximation correction | I), and use (as shown in Figure 89; ： = This) According to the characteristic density of 76A and 76β and f ^ \ / size, Ai Yi. Another method is to use the lithography process or process: there are more choices for the wafer line. After the photoresist deposition, the photolithography process steps are used. If the actual time is equal to '//// = 之 / photographic process flow, one of the patterning feature options provided., 17 as the photolithography button model, where Provide additional dimensions such as sidewall angles and grooves. This step terminates the prediction element d 1230. Additional features of 邠 _ Variation of this predicted size 1 268 0 and the desired material p 丄 750 input verification and correction elements The characteristics of distortion, this element can also be ... J ;;; two U = the size of the confirmed feature in the U = to complete the overall chip, so the system is adjusted for the 1C design. Therefore, the structure needs to be re-inserted and a new layout generated. 200 405 184

The density is removed by adding the metal case density, removing other parameters, and the same as the existing layout of the wire. On the other hand, if the line is changed, the general will be changed to improve the integrated circuit or remove the known total area of the existing structure. Therefore, the addition of oxidized dummy lines ’will reduce the pattern visibility and line spacing. If the distance between the two lines. Also change the effective line width. Use methods such as pattern density and line film thickness to achieve metal filling (degrees. Add a dummy gold ground, and add false widths and finishes. Because of the dense dummy filling, that is, adding the filling, it is also placed in the two oxidizing dummy filling. The definition of K such as the line spacing will be increased by _ slit) and the setting of its parallel lines can be changed. Fill in I method to adjust the physical parameters.

y Next, enter the new layout into the predictive elements to determine that the new design not only meets the lithography-related feature size conditions, but also meets the design and electrical rules. The rule will be repeated until all conditions are met. Alas. .

Figure 50A shows the preferred process for design verification and mask correction. Figure 5 p 50C shows a more detailed process. The motivation for design verification is to predict the two-sign width and topological variation, and confirm whether the known design meets the design specifications by electronic simulation. To this end, the design needs to be adjusted to reflect the characteristic size of each interconnect layer. As shown in Figure 10B, the first part first generates an g-board of the interconnect layer (such as layer N). Use the capture of the overall chip design, the key area of the circuit design, or the layout to predict the feature width variation caused by the lithography process (and such as plasma etching etc.) 1 222 2. This is similar to the prediction element 3 0 0 shown in Figure 10A. Save this original design 丨 2 2 2 3 for future use ’If the design is verified, the original design can be used to make a photomask. Revise a temporary design broadcast to reflect lithography (and plasma etching etc.)

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Variation in feature width. The electrical impact assessment of the characteristic width variation can be performed by using resistor-capacitor (RC) capture to perform key circuit simulation of the overall chip or other electrical simulations 1 2 22 5. This can test for problems caused by variations in interconnect width, such as coupling capacitance, noise, timing, etc. According to component 1, check physical characteristics (such as total copper loss, dishing, erosion) and electrical characteristics (such as thin-film resistor variation, timing termination, signal integration, power grid, and overall performance) 2 226. A validation step weights this result or passes or rejects this design level. If this design is adopted, the original mask 1 2228 will be manufactured. If the design is rejected or rejected, the results of the special width and topological variation are provided to the designer, or a design or mask correction element 1 2 229 is entered, as in the aforementioned mask correction method. The methods of design verification and reticle correction are described in Section e.

Figure 50C shows reticle correction technology that can be integrated with electronic design automation (EDA) tools (shown in Figures 94 and 95) or used separately (shown in Figure 96). First, the layout of the interconnect layer (such as layer 1 ^) 1 2 23 1 is generated. Generally speaking, EDA tools are used to generate layouts to configure the circuit elements and the interconnect routing layers. Dummy filling is usually added to improve flatness. False, filling can be performed at this stage, or when calculating the topological variation due to pattern matching, execute 1 2235 in the prediction step. The next step 2 23 is to physically verify the design to confirm that it meets all design rules and manufacturing parameters (eg, foundry parameters). Physical verification is usually part of the general EDA tool process, including steps 1 223 ι, 223 2, 1 2233, and electrical simulation 1 2234. When the optical approximation simulation (〇pC) is completed, it is part of the physical verification, and the features are further adjusted to compensate

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Order wavelength distortion error. However, it is suggested here that this element can form an interaction in any design process, and this OPC method can be replaced in step 1 2235. If both methods are used at the same time, the design of the reticle is adjusted before the topographic pattern effect of the lithography is properly evaluated. The next recommended step is electrical simulation to verify that the feature width of the design meets electrical specifications 1 2 234. Then the whole chip is designed-human-level circuit network, or the input feature width prediction element without layout is used to characterize the impact of pattern attachment in the lithography process (and plasma etching etc.) 1 22 35. This is similar to the prediction element 23 00 in Fig. 50A. The optical approximation correction (0PC) 1 2 236 can be performed in% steps shown in 1 264 0 in Figure 62A, or an existing commercial tool can be used as shown in 12236. The next step is to correct 1 2 2 3 7 and modify the design so that the mask features can compensate for the width. It is recommended to coordinate any changes made to the design files with these elements (12235 and 12236) 2 2 3 7. This step 12230 is repeated for each interconnect layer until the highest interconnect layer. When the design file for the mask design for each interconnect layer is completed, an electronic file is sent to make the mask. Maintaining individual design files is a very important issue. Design files that have been modified to compensate for line width variations are only used for mask making. If properly corrected, the characteristic size of the mask will be very close to the original design file. This allows further simulation and analysis using the original design file. 1 'This size will be repeated correctly when the circuit is manufactured.苐 5 1 and 5 2 are two examples of how to use the trench manufacturing process. They are marked as modes A and B respectively. The trench process flow is a good example, because the non-flat state will diffuse from the first layer to the second layer, all the way to the last Nth layer. 'The following figures will show the process of repeating this method. To simplify the process

V. Description of the invention (137) After the state: m: i II affects the processing of the wafer topological pattern. The front layer of the wafer 2: m is a high-level trench flow. "Interconnection or money engraving steps to form this :; No additional oxidative deposition double or other trench processes are shown. In addition, Figures 51 and 52 are shown separately and are not included in the lithography process module 1 2600. If this point of view is used to predict the rhyme or physical shape and system, and the comparison step 1 224 6 or the modification step 1 2260, the etching model 1 2225 is used in == 轾 轾 'machine element 1 2600. As a virtual $ There are differences between the two methods. This design is based on the mask system: the rain of the species is modified to produce the desired size, so the original design _ ° 0 reflects the size of the actual mapping circuit (if a mask is used Correction _ pi original ° and counting features). The layout extraction of the original design still reflects this aunt, η, or the size of the design can be fairly assumed to be used in the subsequent ECO process steps. In the branch β, This design has been modified to reflect the effects of wide variation due to lithography The feature size variation of each layer will be reflected in the subsequent steps with patterns. In this way, the design file can be adjusted to perform other layouts and the variation will be passed to the next interconnecting layer to test the multilayer effect. Mode A is applied to light Mask correction to reduce the minimum feature size change. Mode B can be used to characterize the impact of lithographic processes. This can also be used to determine the measurement of the impact of special government changes—or it can exist in the manufacturing device process' The photomask has been manufactured and used in the product. Therefore, the overall wafer feature size variation can be considered as a subsequent process impact. This design can appropriately modify 200405184 V. Invention Description (138) to generate a new layout capture and apply it to Subsequent process prediction. If all physical and electrical effects of lithographic variation are examined, the change in feature size needs to be adjusted and corrected before the simulation (such as using an RC picker or EDA tool). This can make the electrical characteristics of lithographic variation The effect is characterized. Figure 51 depicts in Mode A, after etching prediction, the design is adjusted to reduce the minimum feature size variation. Please Note the description of each step in each subsequent section. The following descriptions will guide the processes and operations of various elements in Figure 50. "1 First perform sample applications on the interconnect layer 1, from layer 丨 to the final layer. For the N-product layout, the process model element 12401 is used to capture the layout parameters 1 2240, and the ILD process model 1 2242 is used to predict the overall wafer dielectric layer thickness, which is labeled Ah in Figure 50. Using the lithographic model element 600 to predict the feature scale △ fw ^ can optionally introduce the feature width variation into the electrical simulation tool to influence the feature ς H, and transfer the electrical feature of the feature width variation to the verification 1 "4 b 〇 = Yuan :: 246 Compare predictions and specifications, and confirm the problem area. Ϊ = 8 Correct this design so that the lithography process achieves the expected mapping characteristics currently meet (or close enough to a certain creep i: parameter 1 2 240 'unless characteristic Specification setting ° 'and a new layout. Because the lithography variation is minimized, this technology can be used to open up the micro-denier for the interconnecting layer 2 rather than suffocate ~ Man Wu Gan Xiao: f 、 Design rules. Therefore, the steps below the process steps are shown in the figure below. The first page describes the two lithographic wafer topologies △}), the predictive elements M;,: The second is the entry of the calculation layer 2.

Tp layer 2 1 2402 needs to use predictive ILD topology

200405184 V. Description of the Invention (139) Case 1 2242, Etching Model Prediction 1 22 50, ECD Model Prediction Topology, CMP Model Prediction Topology Pattern 1 2252 of Inner Link Layer 1, and subsequent ILD Topology Pattern 1 from Layer 2 2256. Map this solution when interconnecting layer 2 lithography, where the design of layer 2 is captured 1 2254 and input into the lithography model. Finally, through the model flow, feed-forward delay is used to suppress the input topological graph variation 1 2256, which is accompanied by layer 2 fetching parameters 1 2254 input to the lithography model to predict the characteristic variation 1 2 0 0 of the interconnect layer 2. "In addition, you can choose the application in Figure 51 to combine the feature width variation calculated in steps 12600 and 1 2 250 with the ^ flutter variation calculated in steps 丨 22 52 and send it to the electrical simulation. Transform the electrical performance of interconnect layers and repeat this operation in each layer. Figure 52 depicts mode B. Mode β determines the pattern attached to the wafer and wafer level to multiple interconnect layers or the overall wafer. Impact during the lithography process: In this method, the mapping or etching characteristics formed by the lithography process flow are different from the expected feature size, so any pattern in the subsequent process steps = the size of the mapping or etching. Because of the circuit size There is a big difference. Here we update the design or capture according to the difference. When the design is updated to reflect JL, another capture is performed and sent to the subsequent model prediction steps. The following domains: ϊ? Detailed description of each step, here The element in Figure 50 will be described. The key difference between Figure 51 and Figure 52 is that in Figure 52] 99βη, the lithography model prediction of 仏 size variation 6 is used to modify the layout. Correctly represent actual mapping Wherein the upper surface of the wafer scale process step + existing or new fetch fetch 12,262 and introduced into a subsequent etch king ^ Alternatively etching updated layout model, implementation of the new captures

200405184 V. Description of the invention (140) -------- =, and import subsequent ECD steps 1 22 52. In mode B, the verification operation of the process can be used to determine the measurement and sampling plan, and enter the area where the problem of measuring the size variation of the heart is generated. Lane: In Figure 50, you can choose to add electrical capture or analog elements to pre-shirts to cause feature size variations that affect resistance, capacitance, and all electrical properties. The lithography process includes the etching process. It can also combine the feature width and topological graph variation predicted by the aunt ECD or CMP to characterize all:, the electrical properties of the line layer, and provide this information to the electrical capture or simulation tools. In order to evaluate the electrical impact in Figure 51, the% sign width variation calculated in step 1 2600 and the topological variation 5 calculated in subsequent process step 1 2252 are reached in the electrical simulation to characterize the interconnect layer. Electrical performance, and repeat this operation in each layer. In order to evaluate the electrical impact in Figure 52, the feature width variation calculated in step 12600 is tested and transmitted to the verification elements 1 2246 and 1 2 250. The topological variation calculated in step 1 2252 of the process is transmitted to In the electrical simulation, the electrical performance of interconnect layer 1 is characterized, and this operation is repeated in each layer. 0 ”Pass the 1C design at the time of final confirmation, and use the process model and electrical model to measure the 1C design. And compare the expected wafer quality and electrical prediction with 1 meter rule specification 1 2800. 乂 1 m The following sections will describe another embodiment. Section a describes the production process. Section b Describe the layout related to the variation of the extraction process. Transform the huge design file into a manageable feature combination. Although it is not a countless, 'station extraction, but it is still needed in a better situation. Section. Section describes the use and control: and

200405184 V. Description of the invention (141) The electronic model is attached with a characteristic pattern and the process changes ~~~ 'ring. Section d describes the wafer topology. Prediction of the daily wafer level due to the lithographic process flow # 二 匕 =) Circuit feature comparison: Compare the predicted and expected feature size values on the overall wafer. The features and processes of creating a new design file are described in the following paragraphs. This section describes the fabrication and use of test wafers to create / form photomasks. Fth subsidiary. Section g describes the two scenes of sections b to f =, the pattern of the spear. Structure and calculation network of the method and application of section g: using the method and system of two ^. User operation a · Generate the cloth according to the use of this technology (as shown in Figures 50B and 50C), or · EDA design flow as shown in Figure 95, or use the factory as shown in Figure 96 The EDA design process performs lithographic prediction. No. In Figures 51 and 52, lithography modeling can be performed before or after capturing elements from the layout. Generally speaking, the layout design goes through the 0PC calibration procedure to produce ~ 0PC layout design files after birth. This 0PC correction can be performed according to rules or models. However, in any example, the layout design file is modified. After passing through the lithography process _ optical device, the lines actually mapped on the wafer surface are almost the same as the lines presented by the original 1. In Figure 6 C, verification is performed with the expected feature resolution, and feature extraction is replaced by layout extraction. With this, the lithographic variation is characterized in this example and corrected at the feature size resolution. The layout extraction elements need to be executed on the first 0PC design file. It is estimated that 0PC can correct any errors that may occur, or executed on the latter 0PC design file.

〇57-5667-PF (Nl) .ptd Page 144 200405184 V. Description of the invention (142) The 0PC correction effect must be removed to present the result of actual mapping on the wafer surface. If you use the lithography model element on 0 PC and trust its ability to change j) s design slot, you will get a file designed as a GDS, and then amend it according to the topological variation of CMP, and you can also move to lithography module 〇 Above the PC block. In other words, if this technology is integrated into the EDA tool, the feature width can be corrected before 0pc, so the 0PC tool can be placed and adjusted to change to a GDS file (in its normal operating mode). In addition, the topological variation (△ h) can be imported into the 0PC tool, and the surface variation and optical approximation can be adjusted at the same time. All of the above are optional, depending on how to use this technology and whether to use EDC tools and 0pc components. Ο Figures 53A and 53B show two methods for generating a process layout (or electronic design file). Figure 53A depicts the masking method used in the layout of the design process. A general example is an EDA tool. Layout Generation 1 2 8 0 Describes the process of converting a functional circuit design into a layout. The IC design is generally expressed as a layout design file (such as a graphic data stream format, GdS), and the file structure database defines the structure and location of each layer of the integrated circuit. This process starts with the photomask 'whose main component (circuit block) is located on a physical wafer 12282. Then perform the configuration and loop winding 21284 to determine the position of each unit or j 'and how the components are connected. Perform a dummy fill and add T286 to correct a layer of material density to minimize electrical effects. The dummy filling can also be performed later after characterizing the topology mutation as part of the predictive element 1 2300. The next step 1 2288 is physical verification. Check the design to confirm that it meets the design specifications and parameters of all manufacturing constraints (eg foundry).

1057-5667-PF (Nl) .ptd p. 145 200405184

V. Description of the Invention (143) Generally, during or after the physical verification step, the design is optically corrected (0PC), and a mask is formed according to the characteristic density to adjust the design file. In the method described here, this step can be performed in the lithographic modular element 1 2 6 00, and the variation produced can be regarded as the characteristic density. Usually when performing electrical capture and simulation 1 22 90 to verify the $ chip, confirm the previous steps and add dummy fills to comply with the electrical performance bar θθ pieces / In the method content described here, the electrical impact also includes The overall chip prediction includes sheet resistance, total copper consumption, capacitance, drive current, and timing termination parameters.

% Generate design corrections in the layout design file format and integrate them into the database. In order to obtain a smaller electronic file size, a hierarchical method can be used to compress the size of this design file. When the layout is complete, you can enter this file into the layout capture element 1 2 3 1 0. This layout is extracted as the feature resolution or the actual overall chip design for a certain part of a circuit such as a critical network with a predictive element of 12300. The layout generation process of Figure 53B includes the generation and verification of a design. The elements described in Figure 53A are the same, and the aforementioned pattern is used. However, due to the different order, the physical and electrical effects of the feature width variation will be directly introduced. Let • Process +. The process shown in Figure 53B is similar to the process shown in Figure m. This process starts with the main components (circuit blocks) located on the physical chip 1 2282. Then perform the configuration and loop winding to “彳 以Decide on the location of each unit or H 'and how the components are connected. Perform a dummy fill and add 1 228 6 to correct the -layer material density to minimize electrical effects. Dummy filling can also be performed later after characterizing the topology mutation as a predictive element

200405184 Part of the description of the invention (144) 1 23 00. The next step 1 2288 is physical verification. Check the design to confirm that it meets the design specifications and parameters of all manufacturing constraints (eg foundry). In this mode, the technology described here is used in conjunction with physical verification elements. As shown in Figures 9 4 and 9 5 below, physical verification is directly embedded or integrated into the EDA tool. In some instances, the computational load is limited and layout fetching can be performed (described in detail in section b). In other examples, actual design files or some circuits (such as key secondary networks) can be directly imported into physical verification 1 22 88 and predictive elements 1 2300. % This predictive element examines and characterizes the feature width variation of 1 2 3 0 0, and updates a design right to reflect the variation that would occur in circuit manufacturing if the photomask used the original layout procedure in step 1 2280. The variation of the electrical performance of the circuit can be evaluated by electrical excavation and simulation to evaluate the electrical performance of this chip. In the method described in this example, the electrical impact also includes the prediction of the overall chip, including sheet resistance, total copper consumption, capacitance, drive current, and timing termination parameters. For the interconnect layer and the expected device specifications, the overall impact of feature width variation on physical and electrical characteristics can be evaluated. In the following descriptions and illustrations, the layout generation will be marked as L ,, and also includes all the examples included in this section, but does not include the d examples of Figures 53A and 53β. b. Extraction of layout parameters As described in section a, the layout is a set of electronic files that store the integrated power

1057-5667-PF (Nl) .ptd Page 147 200405184 V. Description of the invention (145) The structure and geometry of the first layer of the road mother The six steps of the empty door of the Tan process variation and design. Influencing the process level to equalize this relationship, in the embodiment, the second and the degree are related to the variation of the line width. For the purpose of ... description of what is taken; not for general use = areas beyond the design specifications. degree. Although the dummy filling method needs to be adopted: the local parameters are valid for the pattern density. The line spacing and line width can be used to capture 4 degrees of 其他. In other embodiments, whether it is electrically active or not! Factors: = All features need to be considered. • The design of the design and the accompanying layout = = = use the dummy number to achieve the purpose of capturing layout parameters. (Ί 54Α, 54B, 54C shows the layout of the capture Figure 50: Flow chart of step ΐ23ΐ〇. In Figure 9, 'Layout file is transmitted or uploaded to the dummy filling system' 12311. The layout is divided into separate grids, small enough to aggregate calculations, and the largest and smallest components It can be used to represent the structure in the grid, and can be correctly configured with dummy fills. '1 231 2. The key to the resolution of the grid is the increased acquisition, calibration, and prediction calculation time, which corresponds to a more reliable layout presentation and more accurate. The grid size suggested here is smaller than the g-sign size; however, section e and 69A show that the grid size can be used for verification and correction. The grid can be ordered or arranged. , 12313. In the preferred embodiment, a multi-processor parallel computing grid is used, 12314. A grid is selected, 12315, and in this grid, each target i23i6 has a calculated line width, 12317. Here Every bid in the network Repeat this process ’12318. Calculate each group of neighboring targets (such as neighboring targets or distance

200405184 V. Description of the invention (146) The maximum, minimum, and average distance between the target and the target within a defined distance, 1 2 3 1 9 Then calculate the effective density of the full grid; i 2 3 2 0. Repeat this process on the remaining grids, 1 2 3 2 1. Since the above steps are performed on all grids, the extracted features can be recombined from different processors 1 2 3 2 2. Generate a form and fill in the maximum, minimum, and average line I, line spacing, and density of each grid, and the maximum, minimum, and average width of the overall wafer, 1 232 3. Calculate a range using the maximum and minimum line widths. The statistical area (bi ns) is used to calculate the uniformity and probability distribution of layout parameters within the area. The statistical line width range (M) is divided by the desired statistical area. (N), 1 2324, to determine the relative size of each N statistical area. For example, the first statistical area is the minimum line width, or a small non-zero value A corresponds to the line width (M / ν) 'until the Nth Statistical area 'where the line width will be from the minimum m 丨 nf wBinN = (n) • (Μ / Ν) to the maximum max F WBinN = Ν · (Μ / Ν). At this time there are three groups of statistical areas' Contains maximum, minimum, and average line widths. Each network is divided into appropriate statistical areas based on the maximum, minimum, and average line widths, 1 2 3 2 5. The parent-statistic area forms a bar chart to display the distribution value of the statistical area , 1 2326. Store this information and database into the process model 丨 232 7. Calculate the maximum, minimum, and average line spacing range on the overall chip, stomach 3 28. Line spacing range (M) divided by the desired The number of statistical areas (N), 1 2329. For example, the first statistical area is the minimum line width, or a small non-zero value. Corresponds to the line spacing (M / N), up to the Nth statistical area, where the line spacing will be from the minimum minFWBinN = (Nl) · (M / N) to the maximum max FWBinN = N · (M / N). Statistical area The limiting conditions can also be set manually by the user. At this time there are three

200405184 V. Description of the invention (147) Group statistics area,-group statistics area contains maximum, minimum and flatness--grid is suitable according to maximum, minimum, and average line spacing: :: area, 1 2 33. A bar chart is formed for each statistical area to display the statistical area ~ of the number 222.331. Storing this database and database into the process model and calculating the maximum, minimum, and average density ranges on the overall chip, 1 2333. Divide the density range (M) by the number of statistical areas (n) you want to obtain. For example, the first statistical area is the minimum line width, or the density should be as small as the density (M / N), up to the ^ statistical area, the degree of which is ^ nFDB.nN ^ Nl) o (M / N) ^ t Amax FDB , nN .; 0 ^ ^ only. At this time, there are two groups of statistical areas, and one group of statistical areas contains the maximum and minimum average density. The per-grid separates the adult two areas according to the maximum, minimum, and average density, 1 2 33 5. A bar chart is formed for each statistical area to display the knife cloth value of the statistical product, 1 2 3 3 6. This information is stored with the database and imported into the process model, especially the ECD model, and a dummy fill rule is generated, 1 233 7. Mostly, all the line width, line spacing, and density information are stored in the database or file, first, and then applied to the subsequent process model prediction 1 2 4 0 0, 12 6 0 0, 12800, 12338. < 1 Fig. 55 shows how to use the flow shown in Figs. 54a, 54B, and 54C to generate (representing the whole chip or crystal cube) to retrieve the table 1 2 3 6 2. Divide the wafer or square 1 2 3 6 0 into grids 1 2 3 6 4 and use the extraction procedure shown in Figure 53 to calculate the line width of each grid element 1 236 8, line spacing 1 237 0, and the density of 12372. For each separated mesh 36812368 on the crystal cube 12364, the grid coordinates of the features and associated features of the associated patterns are stored in the extraction table, such as

200405184

Density feature width (FW) and feature width (FS). This figure also shows an example of Gan = lattice, whose coordinates (x, y) are * (1, 1) 1 23 7 6 and "饤 Jiang 廿 2 2 2 8 'and how it appears in the capture table. Figure 53 The display of such features fills in the extraction table 12362 with the values of such feature two feature width (FW) 1 23 68, feature distance (fs) such as, and fork degree 12372. In many cases: a 'This table will exist The maximum lambda, minimum, and average of each grid are special. ~ C · Pattern attached process model Φ Use the process model or-series model (such as model flow) to predict the physical and electrical parameters of the 1C component of the design Manufacturing variation. Lee 1 ”process variation of the IC structure can predict the topological graphics on the wafer: differences, and evaluate the variation of the mapping feature size during lithography. The t feature name causes the physical feature size. / ° I ~ or As shown in Fig. 56, a pattern-attached process model is used to match the feature 12310 to the wafer, and the level = variation 1 258 0. The master-manufacturing tool has specific characteristics, so the model needs to be calibrated for specific recipes and tools by 12500. Therefore, this = g model 7G prime 1 240 0 includes a calibration step of 125 〇 and steps = 0. Or the electrical effects of topological variation. The calibration steps will be described below: In general practice, the integration process will be physically performed according to the 1C design to determine the impact of the process on physical and electrical parameters, & development or calibration

1057-5667-PF (Nl) .ptd Page 151 200405184 V. Description of the Invention (149) The process model of a specific tool or formula is shown in Figure 57A. In the calibration process 1 2500 shown in FIG. 57, the actual manufacturing wafer 1 2464 is processed by using the recipe 1 2465 and the specific tool 1 2466. Pre-processed wafers were used to measure 1 2 4 6 7 and post-processed wafers were measured to 1 2 4 6 8 to meet model parameters 1 2 4 6 9.

Use semi-empirical models to characterize pattern attachments in the process. Use any counting method to retrieve the calibration model parameters or meet parameter 1 2470, such as regression, non-linear optimization, or linear deduction (such as neural networks). Finally the model can be calibrated for specific tools and recipes 1 247 1. In other words, it is a model suitable for a specific tool and recipe, and can be used to predict the characteristics of a completed IC based on a specific wafer design. Pan Here we can observe that certain 1 c characteristics such as component density, line width, and line spacing are directly related to the topological variation of plating, deposition, and CMP processes. Also shown here are test wafers that change the characteristics of certain areas on the crystal cube, which can be used to establish 'design parameters (such as line width, line spacing, density) corresponding to manufacturing variations (thin film thickness, dish depression) under known tools and recipes. , Erosion). ^ Test wafers have a variety of performances to evaluate the impact of the manufacturing process. Generally speaking, the manufacturing cost is low. The test wafer design can be used to characterize various types of processes and recipes of a wide range of IC designs. As shown in Figure 5B, a test wafer can also be used to generate a calibration process model or a multiple process model or a process flow. Distinguish the calibration model parameters in the same way as in Figure A. One of the differences is that it can be provided by the test wafer manufacturer and obtained by electronic type, such as via network, e-mail, magnetic disk, or CD, or file type, before the introduction of pre-process measurement 1 24 74. Another difference lies in the final measurement, which is usually 2478, which usually spans large areas, and has characteristics such as line width, and density.

200405184 V. The element of invention description (150). Because test wafers are usually designed to meet a large number of design specifications, it is recommended to use the calibration process described in Figure 57B. Figure 58 shows the use of test wafers in the calibration process. A test crystal The round crystal square 1 2 4 7 9 ′ was subjected to a patterning process with a line width and a line spacing value of 4 8 0. Manufacturing process (such as CMP, ECD, or deposition) This test wafer tool uses a known recipe 1 2 4 8 1 ′ and uses a measurement tool to measure the final variation of the wafer 1 2 4 8 3 (such as film thickness 1 2484) . This correspondence relationship 1 2482 is a model that uses this tool and formula to generate a correspondence relationship between wide-area line widths and line spacing values, as well as specific film thickness variations. 'φ As shown in Figure 5 9 A, this correspondence can be used to predict the process variation of the new j c design, without the need to actually manufacture a mask and complete the design process. The characteristics of line width and line spacing are extracted from the new IC layout (the range falls within the range of the test crystal and the wafer 1 2486) 1 24 85. The line width and line spacing characteristics obtained across the wafer are input into the corresponding relationship of 1 2 4 8 6 and 1 2 4 8 7 to obtain predictions of film thickness variation 12489 and 12490 for specific tools and formulations, without the need to actually produce expensive Photomask and process this new design. As shown in Figure 59B, the predicted process variation 1 249 1 (which may include variations due to lithography) can be imported into electronic models or simulations 1 249 2 to evaluate the impact of the process on the electrical performance of the chip 1 24 93. Then adjust this setting: Ten-curve layout (such as adding a dummy to fill or adjust the design), retrieve the layout parameters and repeat the evaluation of the process variation. Repeat until the desired layout reaches the desired level of variation. Calculated electrical parameters include thin-film resistance, resistance, capacitance, interconnect RC delay, voltage drop, drive current loss, dielectric build-up, IR drop, and variations in “crosstalk noise.”, Using such prediction '

200405184 V. Description of the invention (151) Determine the influence of the characteristic size and the electrical performance of Lianli # 一. , Positive_chip or critical network (also known as critical network) The following diagram will describe the profit variation. Figure 60 of the private and electrical model to characterize lithography. Figure 60 depicts the steps of using specific tools. Calculate the layout acquisition parameters 123; 〇 ,, _ standardized wafer process provider upload. The second step 1 25 0 1 in the example of Erita f test wafer. This measurement includes the film thickness of the wheel 1 measuring device to measure the crystallinity. The third step 1 2 50 2 pairs of test crystals / advanced ^^ to obtain the array and step height Qin process flow. This process, or a specific process f of a process, has been characterized. A better method is to calibrate the individual process product: and / or research sections to obtain the continuation of the process and the process. It is also suggested here that for different formulation parameters, a light-duty standard of 0 u is used. In the same position j of the wafer in this process, the calibration of the model is performed. 1 rm · Shi Yue, Japan 丨 a Measurement of the same period 125 03, this measurement includes film thickness, contour, or electrical properties Measure the variation of this process 1 2 504. Upload a process model or project12. Features: Phase and post-measurement and calculated variations to this model or pattern: 疋 Calibration of tools and / or recipes. This model is planned and selected by the user of the case, or filled in the model database on the computer system. • Periodic measurement and calculated process variation are model or simulation parameters 1 2 506 to match specific processes: and or formula. Finally the process model is calibrated to fit the specific tool and / or recipe 1 25 07. This result also includes a calibrated process model that can be used to simulate the process flow. When feeding prediction ’, 1 1 25 20’, calibration models for specific models (such as ECD, etching, and CMP)

lOH- 5. Description of the invention (152) _ type parameters, tools, recipes, and ☆ Figure 6i A description of the calibration = database and model. The electrical parameters and performance variation, the prediction process variation, and the subsequent process are used to predict the wafer before lithography. Figure = Step: This example reveals that the trench process flow does not need to replace any process or a single process step to display. How to make a prediction without skipping it will not significantly affect the wafer topology: the first 2 simplify this process description 'This example is a high-level trench process, "^ wafer processing. To simplify the generic and plug layer. _ 中 未Display any amount = line layer "— the word refers to the golden step. This trench process shows that it can be easily replaced by: sinking or etching step trench process. The "ground extension" is applied to the double trench process and it will extract 12310 and load it into the predictive element 1 254. The predictive element extracts the imported b-topology 12542. For the interconnect layer that is larger than one layer, this is the former internal The final process step of the connection layer. As far as the first interconnect layer is concerned, the generated pattern topology modelling element and the initial flattening prediction can be used to introduce the wafer topological graph. The imported topological graph and extraction parameters are loaded into the ILD. Process model that predicts the final wafer surface 1 2 5 4 4. The ILD deposition model can include the use of dioxide or low dielectric constant materials. It is recommended to include a pattern attached here to obtain the overall wafer prediction, especially when introducing oxidation CMP is used to planarize the I LD layer. Therefore, pattern-attached oxidative deposition and oxidized CMP models can be used and need to load the model correction parameter 5 2 0. The predictive elements of this method can also promote the introduction of low dielectric materials into the trenches In the manufacturing process. The result of this step is the expected final IL d thickness of 1 2546. '' This prediction is part of Mode A (Figure 51) or Mode B (Figure 52)

〇57-5667-PF (Nl) .ptd page 155 200405184, invention description (153) f, the process can be selected 1 2548. In Mode A 1 2552, adjust the design by using any feature size variation that falls outside the specifications of the first layer, such as the size of the mapping feature of the first layer corresponding to the design. Therefore, for mode A, the thickness of IL D 1 254 6 can be directly fed into the etching model 1 2566 in Fig. 61C. In mode B 1 25 50, the feature size variation due to lithography needs to be used to update the layout to capture the appropriate feature variation for subsequent processes to receive. 1. In this mode, ‘load the topology and layout parameters of the wafer into the lithography model’ 2 5 5 4. Jian Jian here includes the pattern attachment in the lithography model to obtain the overall wafer prediction, and if the model calibration parameters are obtained and loaded 1 25 2 0. The predicted feature size varies 1 2 5 6 6 ′ and is used to adjust the layout feature, shrink or expand the feature, to accurately repeat the lithographic result 1 2558. Layout 1 2560 is generated and used to generate new acquisitions 1 2 562 to more accurately represent lithographic feature size variations. The new acquisition 1 2564 is fed into the etching step 2566. For the connection process in the layer B * N of the model, this step needs to be repeated for each lithography step, so all the effects of the feature size can be observed at the Nth layer.

Load the ILD thickness and layout parameters from the previous step 1 2 56 6 into the etching model. It is recommended to include the pattern attached in the etching model to obtain the prediction of the overall wafer, and the model calibration parameters need to be loaded into 1252. This etch pattern predicts the final wafer topology 12568 and loads the layout parameters into the ecj) model 12570 together. It is recommended to include the pattern attached in the ECD model 12570 to obtain the overall wafer prediction, and the model calibration parameters need to be loaded into 1 252. The wafer topology prediction of the overall wafer after the result of this step is planarized 2 5 7 2. Some processes can be replaced by electrochemical mechanical milling (ECMD) steps, and it is recommended to use a pattern attached model.

ZUU4UD154 V. Description of the Invention (154) Wafer topology and operation pattern 1 2574 to be formed by ECD. The CMP of the trench process can be introduced into the CMP process mold for several / new number. The entire CMP step is used to remove most of the steel. A typical example is to slowly remove all copper in this area, but the characteristics are I: or end-point grinding and corrosion inhibition, and finally perform a barrier layer grinding to remove the resistance. . It is recommended to include the calibration parameters and load 1 2520 here. Final output: prediction, and requires a model circle topology. The wafer topology can: profile, dish, and erode. Exhaustive, Surface Wheels An optional step may be to include 1 2576. CMp ::: capture or performance analysis of the overall chip Capacitance, driving power ☆, and test D = can include the influence of thin film resistance, inch variation. Pass = = = lithographic feature ruler for performance, which can be properly measured = ^ 2 or the specification does not provide a method for better characteristics with better resolution. And f inches, and may be obtained when the CMP step is a pre-internal winding step, the current physical measurement of the current interconnect layer (line such as layer first (such as the first layer)) to obtain the wafer surface Topography 2 layer ^) 1LD deposition needs to be given lithographic prediction. Use "3 test" for the current interconnect layer (such as type 2 to predict the final wafer table topology and capture parameters into the ILD deposition model with dioxide dioxide or: == 58 °° ILD deposition model can Includes pre-viewing materials to obtain the entire wafer. It is recommended to include a pattern attached to

Layer time. Therefore, the pattern is attached when the oxidation CMP is introduced to planarize the 1LD τ 7 emulsion deposition and oxidation CMP models.

Page 157 200405184 V. Description of the invention (155) and need to load the model correction parameters 1 2 52. This approach has led to the introduction of low dielectric materials into the trench manufacturing process. In this step, the company can also perform micro-prediction of the surface of the wafer before 258. Crystal; ^ plane is added in the extension; y and is used in the 2 material or broadcast system to predict the subsequent interconnection '' no need to feed the wafer topology between the interconnect layers, where ^ is after the IL D deposition Do not perform the oxidative c Mp step. 11. Do n’t-light is not revealed in this process. If the pattern shadow is nine thousand resistances, you can attach a photoresist model to the ILD deposition and lithography model (or use a test wafer, and The temporal import map should become a model, and the lithography model is directly imported). , ~ First resistance and lithography effect d. Use lithography model to predict the variation of feature size. The modeling and prediction elements can be regarded as the process model Λ, and, the 2nd process modeling element J 2400 is input before the process. Knife. Wafers are processed after each step in the process. Lithography said topology and prediction wafer topography ’Simultaneous imaging design or figure • special two = different. In this description, they are separate elements (=: Qiao inch changes, as shown in Figure 62A, the whole will be predicted). Surface (such as due to the topology of the first layer of the manufacturing process) and 1260.1, design or manipulation (such as the layout information element 12_ from the N + 1 layer), the predicted wafer topology and the degree of lithography modeling (_) Corresponding to the feature width of lithography prediction features such as = ^) variation_. The lithography process can also be based on 1057-5667-PF (Nl) .ptd page 158 200405184 V. Description of the Invention (156) Wafer or optical numerical relationship guide attached 12640. The lithographic pattern formed by the distortion of this library can be used in the system or calculation, and the optical approximation correction (（^ 2, the expected variation of the V input will be due to topology and misalignment); Figures 48 and 49. The change in the visibility of the sky, the sky, the sky, the sky, and the sky, respectively, is to capture the variation in the width of the pattern due to the etching process or the corresponding topology, which can be formed by # 5 ^ 5 4A, using the etching The karyotype 1 2 6 4 1 maps the mapped steam to physical plutonium characteristics. As shown in Figure 62β, the body feature 1 265 1 is mapped to the feature # 1, which is formed by the topology 12620 and the misalignment 12fi4i). Use the etch model to characterize the pattern number to do complex and different mappings to physical or etching features, and change the orthopaedic sun-slice mapping features. Second, the groove degree, sidewall angle, and groove width. Establish the object-to-object separation The mapping variation of the grid corresponds to the physical special variation of 1 26 55 f. This variation can also be applied to the layout features in each grid of 1 2626 to adjust the overall chip design in response to the mapping and physical variation, depending on whether the prediction resolution is required Applies to the grid or individual feature level. ^ When 1 2 6 00 is combined with the verification element 1281〇 'Apply the grid-level feature text to individual layout features, and skip steps 丨 2 6 5 6) .Using the lithography process model 1 2 60 0, the elements 1 2620, 1 264, and 1 264 1 can be the main contributors of the feature master or predict the feature width variation. The selective etching element 1 2641 can be used with the following two methods One of them is used in combination. Figure 6-3 shows the predicted surface topology pattern 12608 projecting the current layout information to the crystal cube. This crystal cube is separated according to the level selected in the layout extraction of step 12312 'and the thickness is controlled. Variation of feature size resolution with pre

Page 159 200405184 V. Description of the invention (157) The typed element 1 26 00 will be located on the grid's design

:: ΐ Ϊ Should be to the feature variation of the same grid area (such as FW or CD S side on all grid areas, and can obtain the corresponding situation of the overall Japanese and Japanese side special size variation. The following two types will be described Self-topology method. The first method, such as the 64th and =: inch variation formula :: 6 = case interference. Topology and figure formed by anti-long distortion Figure 64 describes the black surface of the moon Corresponds to the shadow mapping or feature shadow; Ruler ::::::: Special 1 2620. This package contains eight steps of uranium and one step of doing talent variation. "Design or capture 12:01: Same as: J Second chip topology (heart) Calculate the difference between the chip topology and the general reference. 12620. The test or alignment key is calculated. It can be adjusted due to the image system and the pair's proximity to the edge of the chip. This can quickly calculate the contrast depth. ς I align with or test the bond-form to separate each of the: characteristics. The optical value of the entire distance can be used for the logarithm of two = resolution of the focus: Q: Similarly, for the whole chip \ each 2? ^^ 丨 combined measurement (such as maximum or average), number; grid, or poly corresponds to the accompanying feature size ^ Layout captures parameters and heart, and imports the ㈣eigh equation: using prior engineering tools; ^ appropriate kl for clothing-general close mm 1057-5667-PF (Nl) .Ptd p. 160200405184 V. Invention Explanation (158). The variation in feature size can be used to lay out features in the response to generate mapping features; grid analysis (such as FW or CD) 1 2 628. Will be mapped ^ γ ^ volume chip prediction (such as provided by line magic 1 2 74〇 Give the verification element to the second, the body prediction. Figure 6 5 describes the step 1 264 of the variation of the feature of the pattern, and the size of the feature. Before X, a ^ grade shirt, Yu or video Into and integrate into a form, the layout features θ, the bureau are loaded h ^ ^ ^ ^ 〇 # ^ f # / " J Δ Tian ΐ? Η A τ said wk / Bei Yi rules' as many Shangzi: EDA tools, Corresponds feature density to feature ruler Commercial: The feature density variation is based on layout resolution and manipulation analysis. Nine; ten: sign resolution 1 2646. Feature density or feature: the degree of degree is different ... If k is provided to 12740 verification Element 12800. The X7th picture shows the implementation of lithography modeling and prediction element 12600: a method. The second method uses Generate a calibration micro-1 type as described in section c, which combines surface height, design ⑶, feature width ⑽, and pattern interference effects into feature size variations (such as CD and 躇). Benefits of calibration in the steps described in this model in section C This model. Figure 66A shows a test wafer using a lithographic model calibrated with specific tools and settings. A pattern of lithographic test wafers using a range of width and pitch values 1 26 79 (FW and FS available Calculated density), which includes one or more sets of structural levels. Selecting the structure at this level can represent the multi-layer effect of variation in line width, line, and plug chain (such as the interconnect level). A more detailed description and examples of test wafer structures are provided in Section ". A recipe was used to process the test wafer 1 2681 on the lithography tool, and then based on the key dimensions of the lithography mapping

1057-5667-PF (Nl) .ptd Page 161 200405184 V. Description of the Invention (159) An etching process is performed to remove the material. Use a measurement tool 1 2684 (such as SEM, physical surface grinding tool, or optical characterization tool) to measure the final variation 1 2 1 683 of the feature size (such as CD or FW) on the wafer. The measured lithographic model is calibrated using the measured parameters to provide a correspondence between two pitches 1 2 680 and 1 2684. This correspondence formed by the calibration model parameters can be regarded as a model, and the wide range of features and surface topological values 1 2 6 8 0 corresponds to the specific features of this tool and formula. Size variation 1 26 84. This correspondence or calibration model can be used to predict feature size variations in new IC designs, as shown in Figure 68. The width, pitch (and density) of the features that fall within the range of the test crystal 1 2 6 8 6 will be extracted from the new IC layout 0 will cross the spatial position of the wafer 丨 6 6 Feature extracted 1 26 85 Enter the corresponding program 1 26 82, and you can get the correct predictions of the characteristic size variation of known tools and recipes 1 26 89 and 1 269 () before manufacturing a new IC design. As shown in Figure 5B, the predicted process variation can be imported into an electronic model or simulation to evaluate the impact of the process on the electrical performance of the chip. Can be calculated Second: The sexual parameters include film resistance, resistance, capacitance, internal wiring to delay, drive current loss, dielectric constant, signal integration, ir drop,

^ M: 4. I of Λ Λ. Use such predictions to determine the effect of feature size variation on electrical performance. 4 夂 ... Hit inch change. itl 5 ^ Γ uses the pattern-attached lithography model to calculate the predictive feature scale and Example 7 for it ΪΓ can use a lithography test wafer, as shown in section, only j, for the positive model, such as a specific micrometer level The bottom stack of the M ^ ^ θ ^ field, and, and photoresistive type. This is from the previous process step

200405184 V. Description of the invention (160) Prediction (160) measurement or step (such as ILD deposition, oxidized CMP, or photoresist coating) prediction (measurement in some examples) wafer level surface height variation △ h is loaded 1 258 0 . It will accompany the layout information of the current design level, which may include layout, capture, or a combination, and is loaded from the file system or database 丨 2 601. The quasi-model parameters are loaded into the model for prediction of 1260.2. Using the pattern attached to Zheng Zhengying to predict the characteristic size variation of the known design layout, and provide it to the verification element 12800. e. Verify and correct the lithographic feature size variation grid to verify the mapping range. Confirmed. As shown in Fig. 50, the electrical mode is also introduced. It can also be combined with the total internal method content, and the resistance and copper are always eliminated. The main purpose in the verification mode is because the class design file will vary the width and will not apply C or etch more than the error. It can also be used to verify the connection level electrical impact on power consumption, electricity, and characteristics simulation, and will not be used as the following The light ratio predicts the feature size and design rule. The feature position and coordinates do not exceed the design specification and error range and are stored. The feature width variation is used to modify the design file, which has an electrical impact on performance. Feature width variation Topological variation of electrical characteristics. What is described here includes the prediction of the overall chip, including the film capacity, drive current, and timing termination parameters. The correction and adjustment of the design file of the degree variation simply reflects the variation including the manufacturing. This mask is used for manufacturing. To correct the predicted features. Mask correction method. The system corrects the design features used to make the reticle. Next, the order is made to make the size and feature g of the interstitial lithography mapping.

The user can choose to use this correction design when the actual mapping size will be equal to the mask 200405184, the invention description (161) is in line with the original design and expectations. The following paragraphs and diagrams describe verification and calibration. Figure 68 is a flowchart showing how the verification and calibration elements operate to meet the conditions. The layout information may include design and retrieval data 丨 2601, key dimensions for prediction, and feature sizes 1 268 〇, which are loaded into the verification and correction το prime 1 2800. This critical dimension and characteristic dimension specifications are also loaded into 1275, and electrical specifications can be optionally loaded to compare the simulated electrical performance of the mapped circuit size. The verification steps are specific to predictions and specifications, such as feature size variation: = able; the tested elements can be used alone or combined into corrections; = (= file) "manufactured expected circuit circuit size. According to early alone or The verification and correction elements used together, the system or database is provided for users to further observe and divide 29 ^ 〇. Case: = 1 2830, you can further carry out secondary wavelength distortion and leading test of the final layout, " Direct: The mask-on-order process. This is the first step of the mask process. 12 = The format of the optical verification step can be completed by three methods, depending on the grid resolution 12312 obtained by the bureau. 〇 Can be standardized. ; As described in section a, the extraction is thinner: = = = = the solution is to dare to represent the small feature size. However, it is necessary to reduce the grid size to correct more subtle features. Retention is increased, and the correct choice is determined; but the next paragraph will have two validators: Retention: user resolution (as shown in Figure 69A) is greater than the feature size and allow grid solution (as shown in Figure 6 9B) ) 〇if it -T is smaller than the feature size) is not possible here Selection of all 1C features = 200405184 V. Description of the invention (162) ^ Grid resolution. However, the size of the graded net can be reduced. Figure 69C also shows the verified square resolution as the special resolution of the lower layer: Combining feature resolution '$' needs to be used for calculation when the grid solution is in all conditions, the feature width varies, and the grid resolution. In the tool, characterizing electrical effects and physical luxury keys, sexual simulation or extraction The electrical performance of the line can be combined with subsequent ECD steps to verify complete interconnection. The two mutation calculations are introduced into the topological variation of the second step of the electrical capture tool, and the chip level or some key secondary areas are electrically characterized. Figure 69D shows another method. The description (such as the maximum, minimum, and average squares and two-grid statistics is used to describe any characteristics that violate the range of distortion. When competing for degrees) determine the supply on the chip. Compared with the 69A, 69B, and 69C maps, this method can be used to correct the correct time. This method can improve the characteristics. In this method, the distribution of individual signs in the H grid of the test knife (such as reducing the most , ^ Way to change the special, the description of the big picture Verification of the separation grid at the minimum IC size. Load the layout level (such as the N + 1 sound of the interconnect layer) fish scale, step 12812. Also load the 12814 overall layer) and talk shirt = different 1 2 680. The predicted variation of the parent-mesh grid is assigned according to the features in the grid (possible probability statistics). 12816 丨 In terms of connections, many such assignments can be reduced or expanded. $: Green layer 816 to provide The common basis is to compare the layout size with the prediction and the size. The design specifications and error range of the step = Zhi_ level are loaded into the system 12818. The corresponding variation and specification of the car parent step 12816 is 1 282 〇, and the excess error is stored. The range value is 1 2822. Any area in the current design that exceeds the margin of error will be

2UU4U5184 V. Description of the invention (163) Informs the user that if it is beneficial, it will cut ^ 6QR R d, and make sure that the plan passed the verification test. Option eight in Figure 69B describes the grid size. Compared to the 69A_n size test in Figure 6 9B, the average separation grid is different only = step 2 8 2 6, i / r ife ia fi / j. Degree and the same layout relay to calculate a j-solution basis to compare the layout features and the predicted size. Where this step is used, k is used for the common option in Figure 69C (: Describe ^. Compared to Figure 69A and 69B: the second size 4 is the smallest IC size. The point is to remove any need to transfer to the brain or ㈣ΓΓΠϊΐΓ 'without any steps to detect whether the anti-solution solution is reached / used in the general trial and error steps 1 2830), and apply 5 analysis degrees to calculate the difference Correction (in the figure 70, there is a width of 1 0. ,,,, and all the features (as compared in the reduced grid is relatively simple. / Tian Shu is written only in Figure ^, and other methods already described) The calculation method does not need to convert the mesh = = = = minimum and maximum size evaluation! It is converted into layout resolution, but it is useful to predict 2 degrees of feature size or feature size to generate different distributions in each grid. Comparison: Make 。. Use the feature size calculated by 1 2828 to try (such as enlargement; dimensional design specifications and error 12829, and use errors). In addition, i line width 10%) to correct (such as Figure 70 Figure 1 2830 as the first The figure 7 is similar to J ί. In this element, if Α is not, the verification result is imported into the correction element 12830. In the 12832, and was ^ \ individual characteristic dimension error range by design calculation of the correction adjustment of the electronic design layout feature sizes, and system

200405184 V. Description of the invention (164) Create the expected mapping or etching. The dummy filling or other geometric structure is created. Pick up. In some cases, 0 1 2280 is required, and if the layout is significantly adjusted to generate the design layout, Figures 71 and 72 are display meters / layouts ^; then a new capture is performed. In the description, two methods using the characteristic wide household ° ° = are used. It is related to the following key dimensions (CD); do Π: (FS), and calculate the feature size, but other types of features =; = what adjustment or the figure shows the first method, and the related operations. For example, the 71st partial derivative is used to map # with the inverse of L element, pseudo-inversion, and the partial derivative to correspond to the mapped feature width FWp. This method first twists from the first net, m is 々i Anticipation FW *. 1 9 ^ 4. w Batch & grid positions or features that exceed the error range start operation 1 2 8 3 4. You can extract forms or acres to pick you up. From the top, you can get the expected S or other key dimensions 1 260 1 from the layout level. From the verification elements, 1 2838 is the predicted lithographic base map size FWp obtained from the ML prediction, or the feature level prediction variation calculated in step 12816 or 1 2 826. The surface topology h can also be obtained from the verification element 1 28 38 and used to correspond to the expected and mapped line width spacing. The calculation described in Figure 73B is used to calculate the partial dFW * derivative or gradient of the known topology h. Another method is to invert (invert) 12600 of ML conversion, as shown in Figures 62, 64, and 65. ^ = f {FWp) h 4 where f is the detailed or approximate inversion of ML. The conversion of 26 1 26 00 is an optical equation (such as the Ray 1 e i gh relationship theory), which can be applied to the development of specific lithography tools or pattern complex models using lithography test wafers. This deposit 1057-5667-PF (Nl) .ptd Page 167 200405184

The error between the expected and mapped dimensions can be calculated as 丨 2 8 4 4: E-f {FW ^ -FWp) Feature adjustment can be calculated as: dFWp where AW is the adjustment of feature width or size 846, which can be used in Figure 33β The procedure shown in 1 completes the operation. In the interconnect hierarchy, AW is the finesse or expansion of the line array. In order to adjust the width 1 2 848, the predicted FWp variation needs to be recalculated. This system will repeat steps 2844, 1 2846, 1 2848 until the error falls within the designed error range. Perform an inspection step to confirm that all meshes or + features that have exceeded the error range have been adjusted. If not, continue with this process 1 28 52. If it is 1 28 5 1, the correction layout 292 is physically adjusted. As shown in Figure 72, the second method uses the data obtained from the lithography test wafer to map the mapped feature width FWp to the preset width of the layout "*. This method starts from the first grid position or exceeds the error range. Features start operation 1 2853. You can obtain "Tun expectation = FW *, FS *, or other key dimensions 1601" from the fetch form or directly from the current layout level. From the verification elements, it can be known that the predicted lithographic base map size FWp obtained by 1 2 838, or the feature level prediction variation calculated in step 1 2 8 16 or 1 2 8 2 6. The surface topology h can also be obtained from the verification element 1 28 55, and is used to correspond to the expected line width spacing from the mapping. The calculations described in Figures 73B and 74C are used to calculate the partial derivative or gradient Lang of the known dFW ^ topology h. Another method is to invert the conversion of ml

1057-5667-PF (Nl) .ptd Page 168 200405184 V. Description of the invention (166) 1 2 6 0 0, formed by using the calibration model: FW ^ f {FWp} k where 'f is the detailed or roughly opposite of ML相 处理。 Phase processing. . The error between this existence expectation and the mapping size can be calculated as 12858: E = f [FW * -FWp) The feature adjustment can be calculated as ... gland = 5 ^! DFWp where 'AW is the adjustment of feature width or size 846, can Use the procedure shown in Figure 33B to complete the operation. In the interconnect hierarchy, W is the reduction or expansion of the line array. In order to adjust the width 1 2 862, it is necessary to recalculate the predicted FWP variation. This system 1 2865 will repeat steps 1 28 58, 1 28 60, 1 2862 until the error falls within the design error range. Perform an inspection step to confirm that all meshes or features that exceed the error range have been adjusted. If not, continue with this process I 2868. If it is 1 2867, the correction layout 1 292 is physically adjusted. Figure 73A shows the feed from the preset feature width or size FW * to the mapped feature width or size LWP. The process model 1 2873 predicts the surface topology h 1 2874 of the wafer, and then the lithography model Ml 1 287 5 is introduced along with the design of iFW *, FG *, and fish *. Lithographic Model 1 2875

II 8 ^ 6 # ^ ^ ^ ^ ^ ^ ^ F WP 1 2 8 7 6. This correspondence can be used in the known chip. The numerical relationship between the size of the lithography and the size of the lithographic mapping "create a preset circuit size in flutter.

1057-5667-PF (Nl) .ptd Page 169 V. Description of the Invention (〖67) Use of partial derivatives to provide inverse approach shows such a mechanism and approximates the mapping rule. Natu: ^ ί;:;, '1, ^ 1 Map the size to calculate the expected ruler; Ladder 2 28: Derivatives There are several ways to derive the derivative J of the wafer based on the process and measurement of the photolithography chip. One way to do this is described in section f. Another method is as shown in Fig. 74c, which introduces the M1 element in detail and stores the minimum sign width variation, which can be thinned * as FWp changes. Use this numerical table to integrate or calculate the number of bismuth partial v-numbers. This process can refer to various micro-value textbooks. Another approach is if A consists of a series of equations for the size of the flow. Textbook on linear verification and multiple variable control. ^ r,.. ^ is the last step in the fabrication of photomasks based on the design of different electronics (applied to each design level). Figure 75 shows how ϊ does not combine and use the elements described in sections a to e to repeat operations at the / ίΐ level.胄 The first interconnecting level 1 2 0 0 1 The feature size of the design level is lost to verify and correct the expected features Ϊ. +, ^ The benefits 1 3 0 1 4. Repeat this process 1 3 0 1 8 until all mapping dimensions, design, and electrical parameters (this level) meet the 5 and calculate the tolerance range of the feature size. The overall chip topology of the interconnect level 丨 will be extended to the level 2 box such as-. Mainly for the second interconnect line level 1 3002, the layout 13002 and FAN 13024 are used to generate the chip-level topology, which accompanies the current design level, page 170 1057-5667-PF (Nl) .ptd 200405184 V. Invention Explanation (168) Critical dimensions (level 2 in this example) Verify and correct 1 3 0 2 8 Variation of preset feature size error 1 3 026. Repeat this process 1 3030 until all mapping 1 etch feature size, design, and The electrical parameters (the level) conform to the design: ten error range with feature size. The overall chip topology of the interconnect level 2 is extended to level 3, and this process is repeated until the final level. 'F · Manufacture and use Lithographic test wafers As described in the calibration procedure described in Section b, test wafers use variations in the test structure to correspond to circuit characteristics and pattern dependencies in one or more sets of process steps. Five methods include forming and using test wafers In order to obtain lithography tools, photoresist materials, and patterns deposited or subsequently etched. Micro-testing & wafers contain test structures, characterizing feature density and importing topological graphics based on mapped key dimensions (Single and multiple levels). This test wafer mold / / patterning introduces topological variation of the wafer to control the equipment so that the structure can be adjusted and adjusted according to the specifications of possible circuit patterns. Figure m shows how to use the test wafer The pattern of the characterization lithography process is attached. The pre-process test of the wafer topology according to the measurement recipe is carried out. The production position of the wafer is 136 °. The measurement data is integrated in the form. This table 2: the circuit pattern below the y position Features wide and quiet Xing special administrative distance FS *) and the surface; booth h ^ the most extensive production port topology h (such as thickness) 1 36 02. Utilization, the second production deduction 1C through the lithography process flow to the wafer Production process. Micro-private 々1_private includes many types of steps, such as photo-etching steps. Y _ n product, lithographic forming, and subsequent Π 2. After this final width variation of the process, measure 1 36 06 and calculate-y 立Mapping or etching feature size (such as width

200405184 V. Description of the invention (169) and spacing)% 5 Health " Fruit Form 13 6 1 〇 Used to calibrate the pattern attached to the lithography model, scholastic = punch to meet the expected mapping or etching size, or evaluate specific processes The best implementation of the machine learning, the power of shadow and the tools (such as tool and process configuration ^) and consumables (such as photoresist materials). Figure 76B shows this type of form, where the (X, y) position is stored in rows 1 3 62〇 and 1 3622. The design or phase 1 line sees (x, y) as row 1 62 4, which measures the surface topology. (X, y) is 626, and the (x, y) of the mapped or etched size is line ι3628. The difference between the preset and mapped (remaining) features is located at line 1 3 63 ().

^ "y mapping and etching" is a replaceable term in this description. This is because of the difficulty: it is difficult to measure the mapping width immediately after lithography, so the etching step is performed to measure the features. Etching will also affect the overall Width variation, female second / day / woodiness is the same as the side wall, which becomes the final result of the pattern attachment. Ben ^ ί The variation of the width or size of the feature, taking into account the variation of the two shots and ㈣. 1. The validity of the measurement state and the requirements of the measurement method, and the direct measurement of the mapping features are provided. In the same example, this method is used with this type of wafer. The following figures are shown in micro Film brake m ,,

Affiliated. Figure 77A shows a stack of spears in a multiple test wafer. The test wafer is used to manipulate Tuya 1056, followed by an ILD layer (such as oxidation or low ^ 2. Beginning in Shixi wafer metal layer 1 1 3052, plug layer 1 1 30 5 1 、 Several layers) 1 30 54、4 The stack of test wafers is related to 2 layers due to the lower layer ®❿ 1 1 3050 ° This commissioning change. Figure 77B shows the layout of the metal layer 1 and the metal layer i.

〇57-5667-PF (Nl) .ptd Page 172 200405184 V. Description of the invention (170) Use the block 1 3 1 00 that changes the line width and spacing to obtain the line width and spacing of the interconnect layer. In the metal layer 1, the block 1 320 () of changing the array size is used to obtain the pattern interaction between the array and the plug. In the metal layer 1, the block 1 3250 that changes the slit structure is used to obtain the interaction between the slit structure, the line segment, and the multilayer pattern between the plugs. Figure 77C shows an example layout of the non-plug level. In the metal layer 1, a block of a fixed size and pitch plug array is used to obtain the pattern interaction between the plug array and change the array structure. In the metal layer 1, the block size 1350 of the plug chain with a fixed size and spacing is used to obtain the pattern interaction between the plug chain and the slit structure. Change the plug between the line width and spacing areas. The level area is the I LD area. There is no structure to capture the interaction between line segments. 1 32 99. Figure 77D shows an example of the layout of two metal layers. In the metal layer 2, a block 1333 which overlaps the line width and the space structure is used to obtain the line width and the space of the interconnect layer. In the metal layer 2, another block 1 3 4 0 1 with overlapping line width and space structure is used to obtain the attachment between the plug array and the metal layer. In metal layer 2, another block with overlapping line width and space structure is used to obtain interlayer attachments of the plug wires, arrays, and slit structures. The following paragraphs and illustrations will describe the areas 1 3 1 0 0, 1 3 2 9 9,

In 1 3 3 0 0, the interactive area of line width and spacing of each layer spans metal 1, plug 1, and metal 2 with structural support. Figure 7-8 shows changing the line width and spacing 13110 across the larger element 13100 in metal layer 1. Figure 79 shows an array structure 1 3 1 2 0 with a fixed width of 0.35 micron 13123 and a pitch of 0.35 micron 1 3 1 2 1 in each of the secondary regions (eg, 13120) of metal layer 1.

1057-5667-PF (Nl) .ptd Page 173 200405184 V. Description of the invention (171) " 一 " "------ ^ 1 ^, the region 13 in 1 and the metal layer 2 In the middle area, the plug 2M between 1 33 0 (): Q layer such as oxidized or low dielectric constant material), so there is no;; Surname 0 is not shown in the area 13122 of the metal I # ^ ° configuration. The purpose here is to characterize the line width of the metal layers between two and two distances, so the area 13 has changed the width and spacing to overlap the fixed width and spacing of the metal layer. This overlapping step allows the combination of wide pitch values to become better specifications to make the circuit. For example, the element 丨 3 丨 2 2 has four sets of overlapping structures (13128, 13129, 13130, 13131), which are also located in the larger area 13300. A set of regions has a line width of 0.1 micrometers and a line spacing of 0.25 micrometers. The other set of regions has a line width of 2 microns and a line spacing of 13129. Another set of regions has a line width of 0.13 microns and a line spacing of 0.113 microns. Another set of regions has a line width of 0.50 micron and a line spacing of 0.50 micron 1 31 31. Figures 81A and 81B show the overlap of two metal layers. Fig. 81A shows a structure 13124 having a fixed line width and line spacing in the metal layer 1. FIG. 81A also shows a structure 131 26 in the metal layer 2 with a change in line width and line spacing. Figure 81 shows how the test wafer uses the method of superimposing metal 2 on metal j to characterize the interaction between the two layers. This overlapping structure is 丨 3 丨 4 〇, 丨 3 丨 4 2, 13144, 13146. The plug layer 1 of the area 1 3299 is a relatively large area and k electrically isolates the two metal layers, which is not shown in the figure. The next set of illustrations and paragraphs describe the structural area 13200 that characterizes the array and plug. Figure 82 shows the layout of the structure in area 13200 of metal layer 1. The area defined by 1 3 21 2 is enlarged to show the pattern of the larger array structure 13211 in the oxidized area 1 3 2 0. The region 13145 in the plug layer 1 on the metal layer 1 and

1057-5667-PF (Nl) .ptd Page 174 200405184 V. Description of the Invention (172) In Figure 83, a large plug array pattern 13412 is shown, which is a gray square area in the enlarged area 13410. Figures 84A and 84 show the overlap of metal and plug layer. FIG. 84A shows a large-scale array structure 1 3 2 1 0 in the metal layer 1. Figure 8 4 A also shows the plug structure in the first layer of the plug. Figure 84B shows how the test wafer uses the method of overlapping plug 1 with metal 1 to characterize the interaction between the two layers. This overlapping structure is 1 3 2 11 and 13412. The next set of illustrations and paragraphs describe the structure that characterizes the slit structure, the plug chain, and the interactive relationship with the overlapping metal wires. Fig. 85A shows the slit structure region 1 3 2 50 of the metal layer 1 with three regions 13540, 13542, and 13544 selected in the 85B drawing example. In Figure 8 5B, an example of a wire without a slit is shown as 13540. Examples of two slit patterns are shown in 13542 and 13544. The metal 1 (Ml), plug 1, and metal 2 (M2) layers are illustrated as 13546. Fig. 85C overlaps the plug chain structure of the plug layer (shown as 13500, 13552, 13554) on the slit structures 13540, 13542, and 13544 shown in Fig. 85B. Figure 85D superimposes metal 2 on the wire, and this wire is connected to the metal layer 1 through the plug structure of the slit structure of the three types 1 3560, 16562, 1 6 566. The 1 3 5 6 6 series provides a picture. This completes the description of the three sets of structural areas in this particular layout example.

The lithography test wafers described in the other #each Luo are not limited to such structures, and may include many structures to characterize the feature width, feature spacing, dummy fill, or dummy fill between the metal layer and other plugs, or Interactive relationship of the slit structure. It is not necessary to perform all processes here to characterize the lithographic process. It is recommended that the type of the imported process can be received according to the lithographic process.

200405184 V. Description of the Invention (173) ---- The pattern depends on the attachment. The actual process of manufacturing test wafers can also be applied to the CMP and ECD processes before levitation lithography. g. Application The above methods can be widely used. Figures 48 and 49 have shown how wafer level pattern attachment, topological variation, and image pattern density affect the lithographic feature density variation, respectively. The following diagrams and paragraphs detail the solutions that make use of streams. That is, the figure describes the solution to the problem appearing in Figures 4 8 and 49. Figure 8 6 A below describes the first problem of how to reduce wafer-level topological variation. Figure 86B shows the topological variation of Figure 8 and the solution of Figure 86A. In this application, the Nth layer layout is loaded into the computer, and the software of the above method 1 4 008 has been installed. The process model predictive element 1412 acquires, fetches, and predicts the wafer-level surface topology 1414. This topological variation of 1,046 plates of high yield variation, 14G48, is also shown in Figure 86B. The inductive wafer-level topology-14014 and the N + 1 layer layout 1426 are loaded into the lithographic model element 1416, and the size (such as line width) is changed by 14G18 in advance. The figure can be retrieved from layer N + ι. Load the design error 1 4 022 into the computer 140〇8 and ^ 1 4 020 to predict the size. Verify and correct the element 0 to reach the qualified mapping feature size (such as line width). Figure 86B shows the results of the "," described in Figure 46A, in which the 14040th N + 1 layer mask 1 4 040 is adjusted in the layout so that the mapping _ /, w is the expected width. This solution enables the lithography process to be

200405184 V. Description of the invention (174) Adjust the mapping feature to form the film thickness in the crystal cube. Figure m describes the reduction of the feature density in Figure 49. The feature density variation similar to that in Figure 9 is the same as that in the computer, which has been installed. The above method / upper 7 layout 14 ° 7 ° load m4m to obtain the table and predict the wafer-level surface extension; ΐΐ; :: It will be used in combination with characteristic density information. Optical interference due to feature density may change the focal depth, so topological graph information can be used. Thousands of the Nth layer layout 14 () 71 manned to capture n4 () 75 2: poor = using the process of the second tool or optical approximation correction tool holder capture. The feature density extraction and topological information "" 彳 are loaded into the micro, type element 1 40 76 to predict the feature size variation 1408. Load the design with a margin of 1 4 082 on a computer 1 40 6 9 and compare the predicted size of 14 0 80. Verification and correction elements 1 40 84 Repeat the adjustment process and layout until a qualified image is reached; feature size. Then, the layout is used to fabricate the N + 1th layer photomask. Figure MB shows the result of the solution described in Figure 87A, where 1 4084 N + 1 layer mask 1 4092 feature scale fwa 1 40 96 and wb 1 4 098 are adjusted in the layout, so that the feature w + △ 1 is mapped 14102 and w + Δ 2 14104 are the expected widths. This solution enables the lithography process to adjust the mapping _ characteristics to change the feature density, regardless of whether the film thickness is flat 丨 41 〇 〇 or & Change 1 4046 (as shown in Figure 86). ’This method also provides the same functionality as a conventional stepper. The stepper can be controlled to adapt to wafer-level variations such as twists or bends (such as bends or twists), and use this to adjust the lithographic image to wafer-level or wafer-level variations. No. 8 8 200405184

The figure shows the basic stepper technology, in which a mask with an IC pattern 1 4299 is imaged at points A 1420-8 to 142 ^ 9 at different heights on the wafer surface. Generally, a stepper will be mapped on a defined area or an area containing one or more and a side. The lithography light measuring alignment marks 〖4 2〗 2 and 1 4 2 1 4 X and ^ alignment and tilt. For example, a curved or twisted wafer level variation of 1 4 2 1 0 is more common, and the characteristics on the wafer surface at point A 1 4208 are different from those on 6 14209. The tool will adapt the mask 14220 to the accompanying optics to compensate for such long distance variations. The focal plane f! 4 2 丨 8 may or may not need to be adjusted to maximize the resolution power. The step and scan tools expose the cubes on the strips, and the pattern is connected to each strip. In most applications, the stepper is adjusted to a wafer topology with a length ranging from i to 50. Topology and wafer-level or wafer-level variations occur within a similar range to the wafer level, but this length range is between about 0.008mm and 25mm. Fig. 89 shows such a case. Adjust the mask 1 42 23 (wafer surface of Fig. 88) to map the ^ feature to the ILD layer 1 4 20 1 of the wafer. This adjustment needs to refer to χ and 乂 alignment lever notes 1 4222 and tilt and focus distance 1 4221. However, the wafer / level change 1 4 2 2 4 occurs in a smaller length range and certain features. This difference is not the same as the focal length. It may exceed the error range of the key dimensions in the design specifications. The method described in the present invention can be applied to Completely familiar with the technology of stepper, and can adjust the chip-level variation when mapping the image like a small stepper operation. This method can be applied to wafer-level lithography correction stepper (CL) system 1 4266 to receive the following inputs: layout and design specifications 142 ^ 〇, lithography tool parameters and settings 1 4 2 6 2 and test wafer data 1 4 2 6 4.

200405184 V. Description of the invention (176) (1111 system 1 4266 uses the stepper shown in Figure 86, 868, 87, 878 to perform the three basic steps of step 1 426 8, 1 427 0, 1 4272 Function. The first function is to verify whether a known layout passes the lithography process steps of a known layout design level. Step 1 4 2 6 8. The second function is to confirm the layout area 14270 beyond the design error range (described in step 14271). The same situation is also shown in Figures 4 to 9). The third function is to modify the layout so that the mapped (or etched) dimensions and features conform to the preset value or design error range. Specification and production of expected mapping (etching) feature size 1 4 2 7 4. This layout is then used to make photolithographic masks 4 2 7 6.

In some cases, tightening parameters within the design error range can be of great help. This can be done by reducing errors in counties and cities or expanding prediction and correction elements (step 14024 shown in Figure 46A or step 14084 shown in Figure 4A) until the errors have dropped significantly. The cost of continuously optimizing the design and electrical parameters will increase significantly. It is up to the user to decide whether to use this method. h. Implementation and use The above methods can be implemented on a computer or server by software. The computer can connect to various types of electricity by two-way or other electronic media. This method can be used as a micro 2 2: # tfL) system to verify whether a specific circuit design should be on the wafer. I = 2 ^ μ, f correction design, features will not be actually produced. Df L can be used to determine the design and process development process. This Lang will describe such as >-I, 4 L ... 彳 7 ^ ordering software and how to link with other design and manufacturing elements. This section also protects how + and ▲ ^ & edge software combines lithography tools and electricity meters.

Page 179 200405184 V. Description of the Invention (177) Automation (EDA) tool. The elements containing the present invention are built in software (such as Java, Tcl, Basic, SQL) and modularized. You can choose whether to use all elements completely when generating a measurement plan. For example, this method can not only be used in process models to produce film thickness variations, tb is wider than design specifications, and it can determine where the two rules are violated. The following will describe the general computing network 0 used in this method. Figure 51 shows a software structure using this method. User 1 4353 is connected to the system via a graphical interface system (GUI) 14354, such as a web browser. GUI 1 4354 allows the user to select and upload design files to the virtual filling system. Look at the party, TF, and the Electric Power Bureau. Probation will be done. e The calculated design area is also calculated. When the system is installed in the eda tool, the user is a designer and the GUI is part of the EDA tool. And 13 such as the definition and use of GUI by the user, allows users to choose from the electronic media box of other formats, the expected zero and the rule, and the design file 定 = the electrical performance of the device, Uploading or transmitting the project = You can also use this interface to select the process and electronic model from a server, and j to transfer or load the model from another electronic media source or computer. User ί: ί: The interface selects a source or computer to transfer or load the model from the database of the virtual filling target stored in the server. Make a certain; 丨 After adjusting the result, also check the final overall crystal a = s cost, predict the film thickness of the process and / or electrical parameters. This,, and ° results can be in the following formats:

200405184 V. Description of the invention (178) • Bar graph or other statistical graphs • Full wafer image of wafer status, or real-time electrical parameters at a certain point • Film thickness and dish of the entire wafer during the process steps or processes Video of the process of trapping and invading the name • Variation of the electrical parameters of the overall chip, such as film resistance and capacitance variation • Numerical form This GUI 1 4 3 5 4 and a series of software elements, services, or functions φ 1 4 3 5 5 (labeled here as a service module) are connected to manage the data flow through the system to the database 1 4 3 5 8 and the computing core process 1 4 3 5 6. The service 1 4 3 5 5 is modularized and imported to start the core calculation process 1 4 3 5 6 to execute part of the calculation rules and integrate and format the content displayed in the GUI. Examples of this element are Per 1, Java, or Tci language, which makes it easier to interact with the GUI using a database embedded in the SQL core and using html, xml, or dynamic HTML language. Such elements can also start the mathematical process and perform calculations to determine the correct dummy fill configuration in the layout. This service module 1 4 3 5 5 is connected to the calculation core of the process and function 1 4356 ′ Executes dummy filling calculation rules and complicated calculation procedures, such as manufacturing and private /, sub-models and simulation processes. This core also calculates the effective pattern density. This calculation includes instructions, data, model parameters, 2 squares of prediction results, images, or image formats, and indicators of filing in the file system. This service fork set 1 4 355 can also be connected to electronic 1 (: design software or office

Page 181 200405184 V. Description of the invention (179) Information on the physical layout 1 4 3 5 7 such as the location and coordinates of the design target, and deciding where to place the dummy filling unit. Database 1 435 8 is connected to service module 1 435 5 via S0L instructions to manage system data, such as filling in database targets by default; user profile, including limited permission and preferred content and presentation; user data, Including layout operation data, previous layout design slots, model parameters of specific tools and processes, and overall chip prediction results such as surface topology, resistance, and capacitance The databases used in the examples can be 〇 r a c 1 e, I n f 〇 r m i X, Access, SQL Server, Foxpro. File system 1 4358 connects to all elements 12280, 12300, 12750 '128005 to receive data and save it as a file. ~ This system can be directly connected to the measurement equipment to generate a measurement plan, and the measurement results can be obtained before or after lithography. This system can be directly connected to a sub-design (EDA) tool to receive the design layout and provide a revised design. The system can be directly connected to electronic design (EDA) tools and foundry to generate test structures and test crystals, and further develop and supply process flows and recipes. This link operation can be done via computer network ⑷ brain bus. y ^ 1: Shi, sigh, the two systems of R & D 14dbU Xing block B 1 436 1 are located in the same neighborhood f brain ’, you can configure this system and system independently. If the area server configuration. This network can include electronics and light through external networks: home network, internet or vpn, internal circuit, internal block can be used as part of the tool, and I 'is used as an example—in the design area

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This section does not fully reveal all the possibilities of the dummy filling method, and still provides some better operation components. This section refers to the three types of basic calculations, which are based on the user's needs to form a better method of operation and transmission. The first type is an independent configuration, as shown in Figure 92A, where all elements are included. 12280, 12300, 12750, 12800 are located in 14363, and the data access (14364, 14365) is obtained from a single computer. The second type consists of a client-server configuration, as shown in Figure 92β, where the GUI is located at the client computer 1 43 67, which is accessed via the network 437 0 and located at a server or multiple temples. Other elements in server architecture 1 4371. This connection mechanism is via the Internet, Intranet, or Extranet 1 437, and the server can serve one or more groups of clients or users. σ The first type of composition, as shown in Figure 92C, is an extension of the client-server model, including the connection to eight computers with one or more elements of the system via network 1 4376, as in section b. As described in section c. For example, the design company f servo ^ 11 8 'Design using lithography tools' but does not require remote ground fines' (where the server stores ❿ tools 1 4382 or wafer generation = recruiting) provided process models and models Parameter 1 43 79 and setting. This network can also send the measurement plan data to the amount if 2 玖 2 ^ 3 81 and return the actual measurement result to the server 1 4 3 8 〇. This transmits process-related information, such as calibration model parameters, to or from the brain system 1 4381 to the feeder 1 4380. The network can also be transmitted ^ ^ ° 〇, Qianjin system tools 1 438 for characteristic density analysis and design

200405184 V. Description of the invention (181) This system method can be implemented using a lithography design (D fL) system to verify whether a specific circuit design should be manufactured or imaged on a wafer, or to correct the design. Features will not be actually produced. DfL system includes the elements shown in Figure 50A 1 2280, 1 230 0, 1 2 750, 1 2800 0, and provides layout capture, chip layer

Level topology calculation, lithography CD variation calculation, design verification, and design adjustment. As shown in Fig. 93, the DfL system 1 45 22 can be used or installed in an electronic design automation (EDA) tool 14500 through an application programming interface (API) through direct integration or connection to a bus or network. Figure 93 shows the integration of the d fL system 1 452 2 into the EDA tool 1 4500. Known EDA tools include system-level design 1 4 5 0 2, logical integration 1 4 5 04, design layout 1 4 5 0 6, configuration and loop 1 4 5 0 8, physical verification 1 4 5 1 0, and signal integration 14512 . The electronic design file is used in the order process to manufacture the photomask 14514, and is used to manufacture the IC product 14516. Most designs of manufacturing elements interact with physical verification and configuration and loop elements. The D fL system 1 45 22- 1 4525 is not limited to interact with any kind of elements, and can include configuration and loop 1 450 8, physical verification 1451〇, signal integration 14512, and inter-kraft photomask production 1 4 5 1 4. But the most likely role is physical verification 1 4 5 1 0 ′ to confirm that the design conforms to the rules and restrictions of manufacturing.

The possible applications of the D f L system are the configuration and specifications of the buffer areas that facilitate the interconnection of plugs and line segments during configuration and looping. In this application, special visibility variation or topological pattern variation can help determine the position of electrical active features and elements, and determine the circuit that enables the sexual features of two components (such as plugs and wires). % D f L system can be used for the configuration and geometry of plugs and wires

〇57-5667-PF (Nl) .ptd page 184 5 Description of the invention (182) Dimensions to improve the signal integrity, application, feature width changes; What is the final feature here? : Yipu figure consumption can help to determine the process (such as expanding or reducing some of these two and determining how to geometrically modify the electrical characteristics or better installation compensation topology effect), to achieve a better circuit clothing structure and reliable sound . D f L system is possible and buffer area. In this application; ',,, helps the configuration of dummy filling in the design and helps to determine the dummy or: the width variation of the slit or the topological pattern variation can be virtual 5 or the buffer of the slit mark and the adjacent electrical active area buffer distance

For example, η 2 elements will be combined to verify or correct electrical performance. With 7 雔 料 拉 ##, use the D fL system to adjust the circuit layout: Jade. Then, send the result to the Rc capture tool. The RC capture tool will be used to re-simulate the circuit characteristics. Finally, the final characteristics are verified, or further used to adjust the unplanned layout. In addition, several different types of layout adjustments can be made; RC capture and subsequent simulation can perform all conditions, and choose the best adjustment layout according to the circuit simulation performance.

Figure 94A shows how a design group (or design company) can apply the Df L system 1 465 9, which can be installed, merged directly, or connected directly to the EDA tool 14670. Most of the initial design includes specifications 14655 such as feature size and resolution error range and electronic 1C parameters. Design group 14656 uses this specification when manufacturing integrated circuits 1 4 6 5 7. During the process, designers or subgroups can use this logic to design 1 462 2. Another designer or subgroup: design memory 1 4 6 4 4 while others can design analog components 1 4 6 6 6. Manufacture

1057-5667-PF (Nl) .ptd Page 185 200405184 V. Description of the Invention (183) The purpose of the design is to consider the manufacturing constraints of each stage of the design, which is produced by the ED A tool 1 46 7/0. EDA tools can include designs for several manufacturing elements, and

The DfL system 14659 can be one of these elements, as shown in Figure 94. In this application, as the designer designs and incorporates elements, the DfL system continuously verifies and corrects the 1 4 6 5 6 design. In this application, the d f L system can directly interact with configuration and loop functions, physical force verification functions, electrical simulation functions, and capture and optical approximation functions to provide feature width variation data. This process may include repeating the addition of dummy fills. If the system cannot find a layout correction that meets the design specifications, it will inform the design group that the design failed. 4 6 6 〇 Crystal Industry or manufacturers will provide manufacturing information based on the calibration model 14672.

The DfL system provides a flow of information between the design and manufacturing end. The DfL system can also be connected to the design tool through the network on the manufacturer or the Internet. Figure 94B shows the use of the DfL system 1 469 7 and can be connected to one or more sets of EDA tools 14680 or directly. This design specification 14682 includes a CD or accompanying electrical error range and can be supplied to Design Group 1 4684 and Manufacturing Element Design 1 46 94. Designers use this EDA tool set to manufacture and add elements 14686, 14688, 14690 to the 1C layout. Complete each level 1 4692 and electrically transmit 1 46 96 to manufacturing element design via the media, network, or internet 4694, including DfL system 1 4 6 9 7 This network includes the d f [element as a network service, which can connect design and manufacturing groups via the Internet. Each design level uses process information for process 14693 ′, including calibration parameters set according to specific tools and recipes. Upload the designed correction to the EDA tool and server 1 4698. If the system cannot

200405184 V. Description of the invention (184) Found that the layout correction that meets the design specifications, why not? The network failure shown in Figure 94A and the figure below tells the design group that the design failed. • The DfL system installed on the lithography process flow can: Connect. And connected via the bus or network • Installed on the etching tool, and installed on the network of the wafer foundry via the bus or network • 制 板 制 &A; Model development, ϋMade by manufacturing or process development members , ':. U-Shirts (Ethai Women's Clothing) are connected together in the design and manufacturing group, such as-network service. And connected to the design company or group through the network, but located in a specific eda It can also use the network to connect various types of EDA tools of different suppliers. ㈣The network is connected to various types of EDA tools of different suppliers. ㈣ Γ5 and: 96 The picture shows a large-scale manufacturing system. Or the DfL system in servo state. Figure 95 is one of the design of manufacturing system: gen :: or ^ 3: 3: upload 1 4880, and extract key patterns: gen parameters. Use one or more steps of the process model Or simulate 1 480 2 and work: and recipe calibration 1 4804 and 1 4806 to predict the overall wafer topology (such as film thickness, dishing, erosion) or electrical parameters 1408 (such as film resistance, electrical ί, timing termination value, or effective dielectric constant). Set the self-setting \: to take the expected result, such as physical and electrical parameters and key dimensions: upload the system to the system 14812. Perform comparison 14810, use more than The position and specific c range of the specific error range and the accompanying variation 丨 4 8 丨 4 Row design and calibration process. '

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V. Description of the invention (185) Use this variation feedback to promote the modification of the 彡 and 50 / claw private, use the 卩 and fill in the element 14818 to determine the size and position of the dummy fill, and adjust the design 1 4822. 1C The selection and configuration of dummy filling in the design level includes the use of pattern attachments to improve physical and structural characteristics (such as using low dielectric constant materials) and 1C electrical performance. When the main cause of the variation comes from the secondary shadow or the combination of surface variation and lithography, the D f L system or element 1 4 8 2 0 is used to adjust the IC design 14800.

(I use variation 1481 4 to adjust process parameters and recipe settings 1 4824. This element uses models to calibrate multiple types of recipe settings and apply various consumable materials to determine the best known process and consumption combination. This element can provide this information to tool operations or Directly adjust tool recipe settings 1482 6. This element can also be used to integrate multiple types of process recipe steps in a process to optimize process parameters. This process optimization element can be combined with the D f L element to match manufacturing and feature dimensions Variation evaluation lithography tool settings and consumables (such as photoresist materials). This element can also be used to generate a measurement formula 14825 when the circuit is manufactured in the standard or actual. Because the design and manufacturing process parameters are used to manufacture the best circuit at the same time, use The electronic design orders the photomask for photolithography, including adding dummy structures into this design. The best process and manufacturing formula can also be transmitted to the corresponding tools of the manufacturing process.

It can also be used to select the best lithography formula in lithography tool settings and consumables. In this application, MM private, evening shovel, and 隹 —refer to the various types of formula lithographic models required for the test wafer and lithography described in Section g, to obtain a pre-calibration evaluation Process] The minimum feature size of the month specification. State map showing i

200405184 V. Description of the invention (186) Use the flow chart in Figure 50 A to predict the first variation in feature size, or repeat 1 49 0 6, 1 490 7, 1 4 908 until each set of calibration parameters is accompanied by formula conditions 1 4 9 0 1, 1 4 9 0 2, 1 4 9 0 3 The optimized mapping size is reached. Compare the results and decide on the best recipe setting 1 4904. The above process and test wafers are used to generate calibration parameters for the master-formulation conditions. The design of the manufacturing system can also use optimization methods to process the conditions of the lithography process recipe with difference or sum.

The following figures are screenshots of graphic user interfaces (GUIs) used for lithography design and manufacturing. The layout management elements in Figure 97 allow users to upload layouts through a web browser and web services, and add dummy fills for appropriate processes based on user-defined design rules (also entered through similar GUIs). Three types of designs 15161, 15 162 '15163 were performed using layout extraction algorithm to calculate effective density. Provide user options to calculate feature width and spacing using layout extraction methods, or upload this information from 1 5 1 6 4, 1 5 1 6 5, 1 5 1 6 6. Figures 98A and 98B show the layout capture results using this system. Figure 98A shows an image 15167 of characteristic wide yield (this = line width) on the overall wafer according to the right-side grade 151 68. In Fig. 98, the space line width of the whole chip according to the root line position is shown.

15171 '15 Π2, 17173, 15174, 15175, and form a distribution map. This type of information, such as line width, is input into the model to predict process and electrical variations. A " A picture shows a graphical user interface (Gn) to set & lithography elements, which can be operated in a manufacturing capability server. The GUI is shown in Fig. 100. = Use browser 1 530 0 as the GUI to communicate with the web server with DfL elements. The advantage of using a browser is that almost all computers are currently equipped with the Internet

200405184 V. Description of the invention (187) Browser, and can be standardized across two major browsers Netscape and Microsoft. The overall chip topology is shown as 1 5 3 0 2 and the positions that violate the feature size error range (such as 1, 2, 3) are marked as 1 53 04. This location is also shown as 1 5 3 0 6. A button is displayed to initialize a correction element 15308 that adjusts the design to pass the design error range. Figure 9 9B shows the G U I of the manufacturing element design. A better implementation example uses a web browser as the GUI. The dummy filling services and functions are divided into three main elements in Gui: design (1 5 499), manufacturing (1 549 1), and model (15400). The screenshot in Figure 62 shows that the user has selected the manufacturing element in the header 4190 and the search bar 4191. The secondary elements of manufacturing elements are: factory, tool, wafer and manufacturing data. Tool 15492 has been selected in this screenshot. There are three types of sub-elements in a tool item: style, recipe, ', and process. In this screenshot, the user has selected style 15493. The user is then presented with the tool's style and settings 15494. Next, the recipes that can be selected for this tool type 5466 and the recipe procedures that can be selected for this tool type 1 5 497 are displayed. For copper CMP calibration measurement and prediction, the system configured in this screen capture pattern provides users with two process models 1 5498. Design Element 1 5499 uses layout managers to allow users to upload and manage layouts and layout captures. One of the purposes of this dummy fill in the GUI design is to allow * users to manage all the data and results provided by the shadow. 〃 = As shown in Figures 6 1 A and 6 1 B, the characteristics of the variation in structure thickness and width due to the attachment of patterns formed during deposition, etching, planarization, and grinding can be used to generate the complete circuit structure of each layer in the component Three-dimensional space model (^ Predicts the error feature thickness and width variation of each layer). This model can help

200405184 V. Description of the invention (188) Predict the electrical properties of the interconnect layer. Variations in the thickness and width of the interconnect structure will affect the timing, transfer delay, and power characteristics of the circuit. Figure 100 A shows the application of the pattern attachment model to the prediction of the full three-dimensional spatial feature thickness and width. Generate a single-level layout of Ni 56〇2, and extract the pattern attachment 1 560 04. This capture is loaded into the system, which includes the oxidized deposition j 56〇8, etching 1561, E-CD 15614, and the CMP 15614 pattern attachment model shown in Figures 12A, 12B, 14, 4, and 60 . The characteristic thickness of the mother step is wide and wide. JK ^ Complete the second line level and pass to the next step until it is characterized. # I: / Multi! Second, the third-degree spatial feature changes * ′ Whether or not the characterization process is completed 1 5 624. If not, this word = next two: ς send 15626 to the next inside; line: = 2 2 topology extension 15618 and pass, step 1 5608 of the sibling line level. Intermediate buffers are usually used in integrated circuits) to optimize long interconnects (such as buses) H = the so-called repeater buffer placement strategy is related to the buffer size (electrical delay. Best Length ratio) and number of buffers. Buffer size: Zhao gate width corresponds to the function of resistance and electricity ((C), both of which are fish; ^ is an interconnecting switch. If the interconnect geometry is not properly modeled, the 2-link geometry has a town evaluation. This will lead to the failure to ensure that the buffer placement technology is delayed. ^ & size and number as the internal buffer placement method not only affect the power consumption of the circuit. Figure 101B shows that the loss will also affect.

1057-5667-PF (Nl) .ptd page 191 5. Description of the invention (189) The circuit of the actuator has a wire. " " Buffer, so its transmission delay circuit is not optimized. It does not include any worst case of intermediary (such as 20% Rq and .Variable. According to the conservative number of resistors and capacitors. This leads to the best buffering. The number of devices is estimated to be the optimal buffer size and device will increase through the wire layer to the buffer cry to 2. However, increasing the buffer step will increase the existing metal wiring on the wafer, and also enter the worst-case interconnection variation. :: The amount of wiring. This additional wiring 3. This 3 plus the actual number of buffers is accompanied by RC, in order to "up (female): slow" because of the additional wiring wires and buffers increase the resistance of the bus line 1 丄.External force σ RC and external device capacitance). Although the heart, ^, and electrical values (low internal wiring, power consumption increases. / Machine, and because of the external repeater, it does not feature 5) as the process model ( Or multiple sets of process models or processes) different (such as the 15th, 5 °, or Wei Tu's process model is not possible ;: :: points, or the key network on the chip. Good progress 眈 '^^ For example The "number" shows the worst-case evaluation of the 2-drop type with only 5%. Here In the case of the best number of retarders, Gade said to 1. Because adding buffers will again be compensated by the required loops between buffers, making the delay of $ :: total Rc amount. This is due to the addition of another 'retarder'. The number of generations is increased to 2 (see figure 100D). If it exceeds page 10557.5667-PF (Nl) .ptd 200405184 V. Description of the invention (190) ^ ΐ is not =, maybe only a single buffer is needed Yes. In another example (only 1 or 2 buffers), the process model can be used to reduce the total load capacitance and resistance to predict or simulate the interconnect geometry. This can save a lot of power / power. This application can be used by the user Used in conjunction with EDA tools, as shown in Sections 94α and 94B, to determine the size, number, and configuration of the buffer, and to reduce the power consumption of the device. This application can be used by users on the network (such as intranet, Extranet 'or Internet), or electronic design steps that can also be used to feedback the guidance circuit and configuration. The following will describe the method of identifying and characterizing the problem area of the chip, which is due to the integrated circuit manufacturing process. Pattern attached to film thickness, Predictive variation of the influence of surface electrical properties. This method; applied to the shape: grinding process) forming a single or multi-layer interconnect structure) two mechanical south-density electro-polymerization (HDP), electric ore copper deposition (ECD), 7 machines (CMP) Plasma etching process and measurement of key dimensions; lithography process includes, first resist deposition and removal steps, and subsequent plasma etching to physically etch patterned features; deposition photoresist and selection Any step in the process of photoresistance; correction of the size of the mask 舛 I ', / # Monkey key 1C size. The size of the dry light is positive, and the difference is in line with expectations when manufacturing integrated circuits. The degree of connection flatness (also referred to as topology) is related to the characteristics of the circuit layout pattern (such as material width, line spacing, and other feature sizes). Non-flat = face and thickness

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Degree often leads to adverse effects on manufacturability and process integration. Pattern attachments may also affect device performance due to variations in capacitance and resistance at known structural locations. 9 The variation of film thickness in the chemical mechanical polishing (CMP) process can be divided into several types of components: batch-to-batch, wafer-to-wafer, and crystal knife. ° Generally speaking, the more significant components are patterns Complex crystal hierarchy. Crystal square sound variation is often caused by differences in layout patterns on the wafer. For example, in the CMP process, when the underlying metal patterns are different, even if the regional planar surface is reached, it will still cause a large-scale change in the thickness of the post-CMP film. The variation in film thickness in the mechanical polishing (CMP) process can be divided into Several types of ingredients: batch-to-batch, wafer-to-wafer, and crystal-to-crystal. In general, the more significant component is the patterned complex crystal hierarchy. Variations in cube-level thickness often result from differences in layout patterns on the wafer. ^ For example, in the CMP process, when the underlying metal patterns are different from each other, even if a regionally flat surface is reached, the thickness of the post-CMP film may vary widely. The following figures show the variations that occur in copper, oxide, and shallow trench isolation (STI) CMP. Say

— For the grinding of the oxide layer, the main source of variation is the variation of the pattern density in the crystal cube, as shown in Figure 2A as an example. The metal wire 1 650 1 is located on the left side of FIG. 102A and is more rightward in the plane direction of the integrated circuit = the metal wire 1 6 50 2 has a low density composition. In this example, the pattern density is defined as the ratio of the area of the raised oxidized area 6550 divided by the total area. The area of this area can be some length, such as the square of the flattened length. This flat

1057-5667-PF (Nl) .ptd Page 194 200405184 V. Description of the invention (192) The length of the process is usually determined by the process parameters such as the type of grinding mill, CMP tools, grinding chemicals, etc.

Figure 102D shows how the density of the underlying pattern affects the variation in film thickness. Figure 102E plots the film thickness variation for each density pattern. For the square area defined by the flattening length, 16521, a higher characteristic density of the lower layer results in a larger film thickness variation of 1 6 5 2 3, and a lower characteristic density of the lower layer will result in a film thickness reduction of 1 6 5 2 4. Designers usually need to try to maintain the fork around 50% 1 6 5 2 2 to improve flatness. After designing the density of the layout, the effective pattern density is calculated for each area of the crystal cube, and density filters of two different sizes are usually used near the area. Figure 丨 〇 2A shows the variation caused by the topological features of the lower layers 16501 and 16502 in the area surface (step height) 16004 and the overall non-flatness 1630.

When manufacturing a shallow trench insulation (ST I) structure (as shown in Fig. 10B), silicon dioxide is deposited in a trench etched in silicon 1 6005, and C is used. MP flattens this electrical insulation device. When the interlayer oxide dielectric layer (ILD) is polished, the pattern underlying the insulating trenches causes variation in the deposited silicon dioxide. The problem area is usually the result of CMP, such as the occurrence of silicon nitride erosion 16 0 0 7 (where the removal of the silicon nitride barrier layer may expose the underlying silicon layer and be contaminated and damaged), corner rounding 丨 6 〇〇 8. Oxidation dish sink 16009. Corner rounding may widen the trench and expose the silicon layer and damage the device. Oxidation dishing will cause topological variation and affect subsequent lithography processes. In sti grinding, pattern density is an important feature of topological variation and other CMP effects. Figure 102C is not for grinding metal features during the trench CMP process (such as

200405184 V. Description of the Invention (193)-The effect of the copper wires 16011 and 160 12) scattered into the dielectric layer (such as silicon dioxide) 1610. For metal grinding, a, the pattern feature calculation is a very important step to characterize the overall wafer pattern; however, physical layout effects such as line width and line spacing are still required. Sinking and erosion are two known effects of metal trenches CMP. Measure the dish sink 1 6 0 1 3 as the difference between the thickness of the wire and the center of the wire. Invasion is defined as the thickness of the oxide layer above the metal line, which is usually located in the wire array and is different from the thickness of the oxide layer adjacent to the unpatterned area. Another unwanted effect is the residual copper 16015, which has not been removed from the dielectric layer (or the upper region) of the wafer. The 9th 03B and 103C diagrams show in more detail the copper when manufacturing interconnects? The resulting electrical effect. The purpose of the trench process is to achieve overall and regional planarization on the metal surface 1 6 0 1 6 in oxidized or L D material 1 60 1 7 as shown in Figure 103A. When the grinding time is insufficient, the residual copper 1619 will remain on the wafer, and a protrusion or short circuit 1619 is formed across the two electrical active area structures or wires as shown in FIG. 103B. When the same structure is studied for too long (as shown in Fig. 103C), the removal of copper from the conductor 1 6020 will cause a so-called dishing effect. The influence of the dishing on the electrical properties will increase the resistance of the wire 1622, and the subsequent influence of the RC time constant of the chip in this area.

As shown in Figure 1 01 β, the effective measurement technique is used to measure 6 0 2 8 I c. The only problematic area in the active area 1 60 27 is the area most likely to violate & design specifications or conditions . If this area is measured within the design specifications, it can be assumed that other areas of this chip are also the same. Design specifications or conditions can be wafer state parameters such as minimum or maximum film thickness variation, or critical dimensions ’or electrical parameters such as maximum film resistance or minimum film resistance change

1057-5667-PF (Nl) .ptd Page 196 200405184 V. Description of the Invention (194) Different. One method is to use the feature attached to the pattern during the process to confirm the location of the problem area and determine the appropriate measurement formula for measuring this variation. This method can be used to compare the geometry formula (that is, the geometry tool settings where to describe and how to measure) and the process to characterize and minimize variation ’, so the learning time of the pre-production line and workshop can be reduced. In general, the difficulty of implementing this method is increased because the designer does not know the location of the problem area in advance.

This method can also be used to pre-store geometric formulas and measure the day. In some cases, a predefined measurement pattern can be used to measure in the same room (or the same cabin) or online. When this method is implemented in a factory environment, it can be used to add possible problem locations to pre-stored measurement plans accepted and verified by some factories. In this way, the method can be used independently or in parallel with existing day-to-day strategies. This method can also be used to generate complete measurement recipes, not just locations. For example, from the variation in thickness predicted across the array structure, this method can be used to define the scan position, scan start and end positions, and measure the number of samples ^ to obtain the scan length—all based on predictions comparing expected chip specifications Variation in thickness. This method can also be used to integrate measurement points and recipes across multiple geometry tools. For example, when measuring the erosion of copper CMP test wafers, this method can

ΐ ΐ Measure the thickness of the area adjacent to the array structure and generate the appropriate formula for the Metapulse photon measurement tool. This method can also specify contour scanning, starting from thickness measurement or nearby locations, ending at other sides of the array, setting, and the number of samples that should be sampled during scanning. All execution methods can be used as a strategy. The measurement location and measurement recipe are generated by predicting the characteristics of the wafer and wafer level, and transmitted to more measurement tools.

1057-5667-PF (Nl) .Ptd Page 197 200405184 V. Description of the Invention (195) Automatically produces flavors according to the design auxiliary process measurement tool Ten days, the system can confirm that the problem across the chip is as explained above:? Or CMP of HDP and subsequent interconnect features. The film thickness changes. ^ ^ The problem area is due to the variation of wafer quality (such as thin (resistance R ΐ *, such as dish sinking and invasion of money)). The electrical parameters are based on the -process two η. The process and each step of the multi-step process are measured and understood. The main r is modeled and simulated. Generally speaking, according to the physical circle, the semi-physical model will use the The actual process test or manufacture of crystals: shell material, to adapt to specific tools that meet specific parameters and conditions. The adaptation of this mold to better tools and formulas is called calibration. = Engineer, determine how to select the measurement location to confirm the process steps or The impact of the procedure. Each measurement may delay the subsequent process steps and produce a bad response to the yield. For the new 1c design, it is very difficult to determine the most likely problem areas in the chip. In addition, dummy fills in The structure may be placed in the layout to improve the thickness and surface topological flatness of the wafer during manufacturing. The electrical properties will maintain the expected or designed values. However, the introduction of dummy filling will further complicate the change in wafer topology. Therefore, the problem area can be moved to another area. Using the methods discussed here, the measurement tool can be controlled to confirm that the overall wafer variation conforms to the design specifications of the actual manufacturing device. Figure 104 shows that the sub-blocks 1631 and 16 are included. 33, 16〇34, 16 0 35, which will be described in detail in the following paragraphs. This method can be used for online, same-room, and offline measurement. This figure shows the method of online operation. General IC design information is electronically such as Graphical Data Stream (GDS) Format

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And no, the structure 1 60 3 0 is defined in the archive database. Although the location and description of each layer in the phase changes with the process, such files are quite large. The characteristics can be described more efficiently using array parameters, such as feature width, feature three = the individual grid (secondary part) that will benefit from the process of taking 1630. = Second, and the density summary I C is set at the limit of the calculated data. Section a will be detailed, but the helpful layout features will correspond to i 6 033 wafers; "extract. Electrical parameters 'such as thin film resistors or capacitors. (Two, eight such as / film thickness' or τ map .) Utilize this information and process mold (type 1V such as knife in mr step cmp process or more complex process flow) to simulate the manufacturing results: 臃 燧 彳 7 ς Λ 7, temple prediction or corpse making 7 50 1. This variation can be physical

"Optical measurement of Hi film thickness." The contour of the surface of the wafer is used to "measure topological patterns (such as dish height or step height, and erosion or array height). Electronically measure such variations, such as film resistance or capacitance. 17502 'and may need to use the original 1C design 16039. The calculation parameters from 17501 to 1. 7 5 0 2 are all-chip integration, and are applicable to the cube or multi-crystal 1 75 03 across the wafer. This The information is stored in the database 1 755 2 and used to compare the expected chip and wafer specifications. The combination of process models and electrical simulations can be used to predict and compare the performance and wafer quality and electrical parameters and design rules of known ICs. 1 6 0 3 2. The dynamic measurement meter day 丨 6 〇 5 elements perform two basic functions. The first function is to compare the predicted and expected parameters, and the second is a wafer measurement meter to generate a specific measurement tool. This ratio For simple inspection to determine the prediction wafer or electrical parameters

200405184 V. Description of the invention (197) Whether the number exceeds the design critical value or is still within the error range. If so, load the location of the cube into the measurement plan for the specific tool. The measurement site usually requires multiple recipe settings to properly guide the operator. For example, a 'contour measurement scan requires not only the scan position, but also the starting point and beam spot and the number of samples to obtain the scan length. In this way, the method can specify the formulation parameters based on the variation in film thickness. Position and other parameters can be used to generate one or more sets of measurement tools to complete the measurement recipe and apply it to a specific point in the process flow. Measure this position, and store the accompanying meter day and measurement recipe in database 1 755 2 for users to view or automatically electronically transmit to the measurement tool 16 0 3 6. The measurement tools 1 6 30 6 use measurement recipes (such as one or more sets of measurement positions and tool parameters, such as the start and end positions of contour scanning) to guide. Where 16037 should be measured on 16037, the above is done by one or more sets of steps (such as process flow) 1 60 38. One selective application of this system is to use 1 6040 to repeatedly store any errors in prediction and measurement positions. Μ adjusts the correction model 1 6 04 2 and achieves a better prediction. This is a process drift that may occur after the calibration. In some examples, the manufacturing process can adjust the model without recalibrating the entire wafer of the tool. 7K ^ One embodiment of the measurement method will be described below. The first and second processes mutate the relevant layout parameters, and combine the characteristics of the large η extraction system. Although it is not necessary to perform layout, it is necessary. Part b describes the use of manufacturing processes and electronic models to characterize the characteristics of the wafer level. Section 栌 The pattern is attached and measured by manual or automatic measurement: 丄 的 刀 ”” 利… ,， 里 里 ° 十天。 Section d describes

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Large, minimum, and average line spacing 1 7 3 1 9 Then calculate the effective density of the full grid 1 7 3 1 0. Repeat this process on the remaining grids 1 7 3 11. Because all nets

1057-5667-PF (Nl) .ptd Page 201 200405184 Description of the Invention (199) Perform the above steps on the grid to recombine extracted features 17312 from different processors. 'Generate a form and fill in the maximum, minimum, and average line widths, line spacing, and bifurcation 1 7 3 2 3. Calculate a range using the maximum and minimum line widths. The line width range (M) is divided by the desired number of lines (N) 1 73 1 4 to determine the relative size of each N line segment. For example, the first line segment is the minimum line width, or a small non-zero value △ corresponds to the line width (M / N) until the Nth line segment line, where the line width will be from the minimum minLWBinN = (Nl) · (Μ / Ν ) To the maximum max LWBinN = N · (Μ / Ν). There are three sets of line segments. A set of line segments contains the maximum, minimum, and average line widths. Each grid is separated into suitable line segments 17315 according to the maximum, minimum, and average line width. Each segment line forms a bar graph to show the distribution value of the segment line 1 7 31 6. This information is stored with the database and imported into the process model, especially the ECD model, and a dummy fill rule 17317 is generated. On the normal day-to-day film, the maximum, minimum and distance from the average line of the nose are 1 7 3 1 8. The line pitch range (μ) is divided by the number of lines to be obtained (ν) 丨 7 3 丨 9. For example, the first line segment is the minimum line width, or a small non-zero value △ corresponds to the line spacing (M / Ν), up to the ν line segment line, where the line spacing will be from the minimum minLWBinN = (N-1) · (M / N) to the maximum max LWBinN = N · (M / N). At this time, there are three groups of line segments. A group of line segments contains the maximum, minimum, and average line spacing. The mother-grid grid is separated into suitable line segments 1 732 0 according to the maximum, minimum, and distance from the average line. Each line segment forms a bar graph to show the distribution of the line segments 1 7 3 2 1. Store and import this information into a process model

200405184 V. Description of the invention (200) --- Special ECD model in China, and a dummy filling rule 1 732 2 is generated. Calculate the maximum, minimum, and average density range on the whole wafer. Reduction: The range (M) divided by the number of desired lines (N) 1 7324. For example, the first line segment, the minimum line width, or a small non-zero value △ corresponds to the density (M / N) until the ^ th line segment line, where the density will be from the minimum minLWBinN = (Nl) • (M / N) to Up to max LWBinN = N · (Μ / Ν). At this time, there are three sets of line segments. A set of line segments contains the maximum, minimum, and average density. Each grid root is separated from the average density by a maximum of 1 and a minimum of 7 3 2 5. Each line & line forms a bar graph to show the distribution of the line segments 1 7 3 2 6. This information is stored with the database and imported into the process model, especially the ECD model < type ' and a dummy fill rule is generated, 7 3 2 7. Finally, all line width, line = distance, courtesy, and degree information are stored in the database or file system for application to subsequent process model prediction or the generation and configuration of virtual rules, 1 7 3 2 8. Figure 106 shows how a capture table can be used to represent an entire wafer or cube. Divide the wafer or crystal cube into a grid 16 0 4 5 and use the extraction procedure shown in Fig. 105 to calculate the line width 16 0 47, line spacing 1 6048, and line spacing of each grid element 16 0 46. Density 1 60 49. Fig. 106 shows an extraction table about the grid at (y, x) coordinate (1, 1) and one of the grids at (y, χ) coordinate (2, 丨). 1 60 5 0 , Line width (LW) 1 604 7 and line spacing (LS) 1 6048 and density value 1 60 49. In many instances, the maximum, minimum, and average characteristics of each grid will be stored in this form. b. Process and electrical model The dummy filling method of the present invention uses a process model or a series of

1057-5667-PF (Nl) .ptd 200405184 V. Description of the Invention (201) The model (ie process) predicts the manufacturing variations of physical and electrical parameters in 1C designs. In order to characterize the manufacturing variation related to the K structure, a dummy can be added to fill in the variation between the most physical and electrical parameters and the desired value: a model or simulation of any particular type. • It is acceptable that each process has its own characteristics, so the model needs to be standardized on specific recipes and tools. The design of 1c needs to determine the impact of physical and electrical parameters on the process, and according to the process The model develops or calibrates out specific tools or recipes, as shown in Figure 107A. In Fig. 107A, the actual wafer 16064 is processed on a specific tool 1 606 6 using the recipe recommendation 5. The front wafer measurement 1 606 7 and the rear wafer measurement 1668 were used to meet the model parameters 1 60 69. A preferred embodiment is to use a set of semi-empirical models to characterize the attachment of known process patterns. Use any counting method to extract the calibration model parameters or conform to the parameters 1707, such as regression, nonlinear optimization, or linear deduction (such as neural networks). Finally, the model can be calibrated for specific tools and recipes. 6 0 7 i. Certain 1C features such as component density, line width, and line spacing are directly related to the topological variation of plating, deposition, and CMP processes. Also shown here are test wafers that change the characteristics of certain areas on the crystal cube, which can be used to build on known tools and recipes, and design parameters (such as line width, line spacing, density) correspond to manufacturing ^ film thickness, plate Subsidence, erosion). There are various possibilities for test wafers to evaluate the impact of the process. Generally speaking, the manufacturing cost is low. Test wafer designs can be used to characterize various types of processes and recipes for a wide range of IC designs. As shown in Figure 107B, The test wafer 16701 can be used to generate a calibration process model or a multiple process model or a process flow. Utilize the same as Figure 7A

1057-5667-PF (Nl) .ptd Page 204 200405184 V. Description of the invention (202) The method calculates the parameters of the calibration model. One of the differences is that it can be provided by the test wafer manufacturer and obtained by electronic type, such as via the Internet, e-mail, magnetic disk, or CD, or document type, and the pre-process measurement 1 6074 is introduced. Another difference is the final measurement of 16078, which usually spans a large area of line spacing, line width, and density characteristics, so it can be applied to large area components. Figure 1 08A shows the use of test wafers in the calibration process. One test Wafer crystals 16 0 7 9 were patterned with line width and line spacing values of 6 0 8. Process (such as CMP, ECD, or deposition) of this test wafer; using a known recipe 1 608 1 and measuring the final variation of the wafer 16083 by a measuring tool (such as film thickness 1 6084). This correspondence is a model that uses this tool and recipe to generate a wide-area line width and line spacing value, and a specific film thickness variation. As shown in Fig. 108B, using this correspondence relationship can predict the process variation of the new 1C design 'without the need to actually manufacture a mask and complete the design process. Features of line width and line spacing are extracted from the new IC layout (the range falls within the range of test crystals and wafers 1 986) 1 6085. The line width and line spacing characteristics 1686 obtained by cross-chip capture are entered into the corresponding relationship 16087, which can be used to measure the thickness variation of specific tools and formulas 1689 and 1690 'without actual production. Expensive reticle IC design. 1 As shown in Figure 108C, the predicted process variation 16091 can be imported into a sub-model or simulation 16> 092 'to evaluate the electrical performance of the process on the chip ~ 16093. Electronic parameters that can be calculated in 30s include film resistance, resistance, capacitance, interconnect RC delay, voltage drop, drive current loss, dielectric constant, or

200405184 5 Description of the invention (203) Crosstalk variation. This prediction can be used to determine the appropriate location for the measurement. Implant dummy fill in. Using clothing knowledge, the electrical model is used to characterize variation and Fig. 10 depicts the steps of Elaine. As in Fig. 105, the process model is described using measuring equipment:者 上 #. The second step η “ι cats to obtain the array fish ρ Ϊ :. The first; including the film thickness and contour sweep, white step A 2 0 step 17442 ponder, heading + + m, the public bank has been characterized The specific process of the process is the following: 2 pairs of test 5 crystals, 0, electroplating, sinking, and so on. This process or process can include calibration. Also: The Λ grinding step is a good method. Calibrate to get the continuity time in the process. It is also recommended to measure different formula parameters, such as the previous measurement. · The same position of the wafer in the θ process is the same or electrical, and can be; = two, this includes the film thickness, contour, or pattern 1 7445 4 Υ process variation 1 7444. Upload the process model This model or pattern is measured and the calculated variation is selected for the library. Before: iL, ί fill in, the model information on the computer system meets the specific process requirements / ^ / monthly measurement and the process variation calculation is used for ^ ^ I Λ ^ ^ ^ ^ Π 4 4 6 〇 ^ „t It also contains / or Formula 1 7447. In this result, the electrical threshold number Λ describes the steps of using a calibration model to predict the effects of process variation and subsequent electrical energy ... and performance variation.

Page 206 ri ijv 200405184 V. Description of the invention (204) Combination and desired 1 (: feature, geometric structure, ί = 3 °. The second step is to perform layout 22 = the description or feature combination of process variation in the area .- = Separate the layout into several grids and calculate the per-grid element value ^, the present invention calculates the effective line width per-grid = spleen or transfer the calibrated process model to the simulation process. The layout parameters of the acquisition of the spatial area are imported into the model, = the final control process parameters Λ, such as film thickness, dish depression, array, and step height 1 7501 The difference between the target and the predicted process parameters is used to calculate the loan variation. Forecast The process parameters can also be imported into the electronic model with the parameters of 1750.2. ▼ The calculated electronic parameters include quasi-thin applications: special = interconnected RC delay, voltage drop, drive current loss, dielectric: electronic change Electrical models and simulations can be used as packet capture or other 1C-related CAD software elements. Therefore, the dummy fill-in calculation rules are particularly suitable for interconnection measurement (R, c, L variables) at the interconnection level. Is the truth of the crystal Τ: Ϊ :: Γ 测, As shown in the following list. Other specific areas require circuit performance. For example, the signal delay variable ΪΪ meets the circuit specifications. Similarly, 々 = = the timing limit of the path. It will work properly. In this method, the RLC standard can be used as a dummy to fill in a 5 by selectively targeting specific signals or the chip-to-person pass zone. The plan can be used next-time. 1057-5667-PF (Nl) .ptd 200405184 Adjust the configuration of the dummy fill when repeating the operation. 5. Description of the invention (205) Fill in the configuration dummy, and then select the prediction key difference = position for online or same-room measurement. In other words, the dynamic measurement system is used to determine how the chip should be measured and tested to confirm this. The term dynamic includes the use of measurement data obtained from the test report and the shape to determine the measurement location of the new design. Dynamic 2 Words, including the use of the same measurement data and models described above, but without the addition of ^ measurement feedback from the measurement tools on the wafer to determine the current test location of the product wafer. For example, 'thin film resistance at a certain location Variation prediction can improve Terry's contour scanning to measure dishing or erosion. Electrical resistance measurement type Application resistance (R) 3 ^ _ BCD, dummy fill capacitor for gasification layer (C) ^ Connect BCD , SL layer dummy road entrance, gold: session virtual people inductance (L) connection ____ high frequency (BCD, Boom & Jin Yajin) signal delay circuit loop, wiring, specific line twist Circuit clock crosstalk noise «Two low-amplitude off-sensing electrical sensors _., ^ Π Tuntan is used to apply the new character to the new C setting; system, full-chip prediction of electrical parameters and performance, and When adding dummy filling = how to improve the prediction of such parameters. The next section will describe this _ 夂 input measurement plan generation elements, and design specifications and conditions to determine the measurement location and tools. Ride the car right 义 Φ c · Generate a dynamic measurement plan

1057-5667-PF (Nl) .ptd Page 208 200405184 V. Description of the invention (206) As shown in Figure 104, the dynamic sampling meter generates elements 1635 to compare design specifications or conditions to predict wafer stage parameters such as thin films Thickness, electrical properties such as film resistance. Generated by using wafer positions that exceed or are close enough (as defined by Design ^ to specify different distances in different circuit designs):] = 2, as shown in Figures 111A and 111B. Figure 1UA shows that the thickness of the thin film on the two metal wires 1609 5 and 1 096 is predicted to be a result of ground copper. As a result, the residual copper of the two wires will form bumps or short circuits at this location. Although the target thickness is τ, this & start or short-circuit location will have a thickness τ plus a copper thickness R. The result of the model prediction stage is the calculation result of film thickness or electrical parameters such as film resistance. This model can be used to predict the thickness of the bump or short circuit, and from the model: the thickest and thinnest points of the measurement position, so that the measurement tool can actually measure this position. 0. Figure 11B shows the use of model prediction decisions Measure position. Use the design specifications of the film to determine predictive parameters such as film thickness variation. For example, the formation of a large positive variation or an increase in film thickness will result in a bump = 5. Due to the huge negative variation of cMP or the decrease of film thickness, it will cause the driver to sink and increase the film resistance by 16m. When the predicted thin film— = reaches a certain predicted amount or exceeds the thickness variation level, select this area to enter ::: f takes a measurement position of 1 may include the accompanying specific wafer. ★ The electrical parameter variation level 'is shown in Figure ⑴AmuB. This In this case, the maximum variation of the thickness of the copper film (if a bump occurs) is determined as + ΔΤ 16101. This predicted film thickness is on the metal line, as

200405184 V. Description of the invention (207) 111A, drawn in Figure Π1B, and the maximum height 16103 is T + R 16102. In this example, the location of the raised point 16103 will be introduced into the sampling plan for film thickness measurement. This is a critical example. The cost function is used to determine the selected location. Read · Use measurement and tool types to monitor parameters. For example, the dishing that affects the film resistance of the interconnects is usually measured with a profile measurement tool, while copper film measurements are usually measured with a film thickness tool. Therefore, the resulting measurement meter can be planned for a specific tool type available to the user. Since the measurement day is generated, it can be displayed through a graphical user interface (as shown in Figure n 丨 C), and the user can manually select a measurement location to load. This measurement plan can be automatically transferred and loaded into a specific measurement tool. I process map. Enter the design specifications of the wafer and according to the design specifications, as shown in Fig. 11, Fig. 11 shows the step of generating the measurement plan and the full chip prediction of electrical parameters 1 6 0 3 3 Condition 1 7452, and the selected measurement tool 16035 ^: = also for full-chip wafers and electrical parameters 1 74 53-% wafer Η 丄 H; predict critical values of wafer stage and electrical parameters. The same system, or has been removed, such as the 15% limit. The preferred error range can be determined according to the system: 1 In the stored s prediction, some modular errors are calculated. Therefore, there must be a limit on the number of measurements, with: = can also be defined statistically, so the limit is higher. This calculation also includes: Priority of the location of the problem, poor diagnostic methods, and advanced hypothesis testing and other statistical error calculations. Machines that affect chip performance

200405184 V. Description of the invention (208) Integrate and try all measurement positions and errors, and select the measurement tool 1 75 4fi. Cobalt is produced, and the high-thickness film 1 formed by dishing is measured by Dongcha. At the beginning, the convexity caused by the profile 1 measurement tool is used to measure the film thickness and the film thickness measurement equipment is used. Copper residue. The measurement tool requires a recipe, and uses the error ^ t to generate a test recipe, which is appropriately developed for existing tools. 1. Stored the plan and recipe of the measurement position in the database 1 745, and nt ^ sent 1 745 7 and carried 1 6036 to the surveyor 1 to help you with measurement. The measured amount of the plan is, "two two." check. ;: 1 4 ， Fork 疋, and form this plan according to the model prediction output ^ 7 Other accounts, this method also generates one or more sets of measurement tools to measure g? ': Use thickness and contour measurement to measure copper Invasion, bug. In this case, the measurement formulas of the two tools can also be stored in the database 1 74 57. The computer-controlled measurement and judgment system can also use this method dynamically. = Provide measurement position and recipe information to guide the measurement 'and use the measurement results to generate additional in-measurement positions and recipes. The measurement data can usually indicate the ice making movement, so the model used for prediction needs to be adjusted or properly calibrated. In this case, t is still measured with a small threshold value until a more accurate prediction and inclination are obtained. Corrected predictions can be obtained by calibrating the models according to different process stages, and can be selected from other shell models in Figures 124A, 124B 'and 125 ^ 75 ^ 2 for further process models 1 62 57, 1 6260, 1 6 263 . The error block attempt step can be used to measure one position at a time, for example, for the maximum thickness variation, detecting the position where the copper residue may not be removed in the CMP process. Another erroneous step provides tools to measure location information.

Page 211 200405184 V. Description of the invention (209) 'And according to the actual measurement, select another calibration model that is more suitable for the current state of the process. Figure 11 3 shows the erroneous attempt steps that the system can take during the CMP measurement of the rear trench process. Figures 113 and 1138 show several methods of erroneous attempts, of which only the measurement meter is generated from the model prediction (Figure 113): and the measurement and overall wafer prediction are continuously used to select the next measurement The location snapping is used to determine the dynamic measurement and icon of the wafer < 1 or trace. Therefore, this method can be used with any wrong attempt to step the problem area of the wafer. Several types of error attempt steps are discussed later. d. Implementation and operation Generally, this method is used to measure in multiple crystal cubes. The effects of pattern attachment in the process of level 1 (such as film thickness, ellipsoidal measurement, equipment, electronic capacitor, and electrical point probe film resistance test). Operation modes, such as offline, online, 114A and 114C, are described in the same way as wafer-to-wafer. This method is based on the wafer stage or the position of the crystal square 1 6 1 1 0. If the J type is used to calibrate the square of each crystal 16113, please refer to Figure 4 for the measurement tool on the crystal or on the wafer. This guide can be based on the crystal and wafer layer application. This method can also use any measurement, contour measurement, atomic microscopy, optical measurement resistance test, or material property test (such as the four methods can be used for any operation of the measurement tool or the same room operation. '于 在 晶 方 与Characterization on the wafer level is generally round. As shown in Figure 114A, using the electrical variation of the square 1611! Can be determined as shown in the overall Figure 14B. This method can also use the mold method to characterize multiple crystals on the 16112 wafer. No. 3 4. In this application, for each crystal 200,405,184 V. Description of the invention (210) " '—' '—-1 ------- prediction of mold shape 16115. According to design specifications and according to Figure 104 = 〇The measurement plan generated by 35 is compared with the individual and total crystal cube variation i6ii4. Common: Said circle: the variation of the level is radial, so three groups of crystal cubes are used; one group is located at the center of the wafer, One group is located between the two-as shown in Figure 11c. This method can be used to characterize and crystallize multiple sets of r :: test 211 '. Usually process drift will change the wafer process. Use two: secret π ί'shows 70 shifts, model predictions can be used to confirm the requirements of measurement =: design specifications of shift direction Or limit. In this method, use 1 fi 1 »: Calibration models at different times to predict how wafer-to-wafer changes i π ^ ^ + + ^ Use this feature to guide this amount when drift is more serious The testers are mostly used, but guessing and possible problem locations.-Class t ϊ ?: There are several types of methods shown in the figure to interact with the measurement tools. And 16 ^ 2 ^, female computer 161 21 system 16 122 direct The machine connected to the measuring instrument is installed in the computer control system of the measuring tool. The manufacturing plan will be processed and the software system 16122 will process this design and generate a measurement step_22 == internationally guide the measurement process. The actual process step measurement results are stored in Xunzi = 1; 123 to measure the wafer 16125.-General engineer 16126. The GUI is transmitted to the operator or connected to the measurement tool.-This method is installed in the computer, The connection via the Internet or VPN may include connection via an external network, an internal network, another or an optical connection of the present invention. When an error occurs, the difference between the selection and the actual measurement occurs. (Please refer to Fig. 104 1 6 040) adjustment

Page 213 200405184 V. Description of the invention (211) Model. As shown in Figure 1 15B, the design specifications and layout information 16 127 are provided to the dynamic measurement method 1 6 1 2 9. This method 1 6 1 2 9 can be installed in a computer 1 6 1 28 connected to a measuring tool or a computer control system installed in the measuring tool. Load the design specifications and layout files of the manufacturing bureau (if they have been captured) or layout capture 1 6 1 2 7 into this method. This method 1 6 1 2 9 processes this design 'and generates a measurement plan, which is connected to the software and actually guides the measurement process. After the actual process steps 161 31 such as CMP, the tool 1613 30 is used to measure the wafer 1 6 1 3 2. The general measurement results are stored in the electronic medium 17 μ 4 and transmitted to the operator or engineer 16134 via the GUI.

Another method is shown in Figure 115C, which uses the same method as in fU5B, but adds 1 16 1 4 3 to provide feedback from the process control system or tool to optimize the process settings and recipe combination. Another method is shown in Figure 115D, using the same structure as in Figure mc, but also adding element 16149 to transfer the measurement variation to the medium, such as a dummy filling tool 161 52 or a shovel to occupy a few shims, + 1ej M ^ ^ FREE 4 I optimize the method 16 16 151 with the most variation. The dummy filling tool is used to modify j Γ? 呌 ;; once, ^, ^ ^ 1L ° and then to minimize the measurement variation, the optimization of the abandonment process is to find the adjustment process bar 侔 I 1汆 仵 To minimize the t-path effect caused by mutation. Another element, 16150, can also be used for calibration and maintenance # 3. Feedback to process tools

Basic, SQL) and be modularized. ^ (Such as Java, Tcl, whether to use all elements completely. For example, when planning, you can choose to generate film thickness variations and compare the official itch machine. The second is not only used for process model reflection The location of the specifications. The following will describe the two = leaf specifications, and can determine the general calculation network used to describe this method.

200405184 V. Description of Invention (212) Road.

Figure 116 shows a software structure using the present method. The user 16153 is connected to the system via a graphical interface system (GUI) 16154, such as a network browser. GUI 14614 allows users to select and upload electronic layout design files to the dummy fill system to view areas that need to be modified or design areas that have been modified by the lithography system design. When the system is installed in the measurement tool, as shown in Figure 115, the user is a tool operator, and it is installed in the tool command and control computer. GU I can also be installed on a computer screen or touch screen built into the tool. Figure 111C shows an example of a GUI from other users, or from other sources, or you can also set the source or read the layout. The layout of the device can generally be a format, but also a computer with an electronic interface. Use the virtual space secret as the following electronic medium. Use this medium to come from the storage state, ruler transmission or fill in the schedule, pre-format: Lang's definition and use of the GUI, allow user interface, expected design rules, and design File performance is selected, uploaded, or transmitted. Select a process and electronic model from a server, source or computer to transfer or load the model. The user fills in the target database in the virtual database of the server and selects the size and pattern, or loads the model from another electronic medium. Users can also use this interface to check the results after the adjustment, and / or check the final overall film thickness and / or electrical parameters of the process. this

Bar graphs or other statistical graphs Full wafer image of wafer status During process steps or processes, or real-time electrical parameters at a certain point Overall film thickness, dishing, invasion

Page 215 200405184 V. Description of the invention (213) Video of the etching process • Variation of the electrical parameters of the whole chip, such as film resistance and capacitance variation Video ^ • Numerical form

This GUI 14614 communicates with a series of software elements, services, or functions 1 6 1 5 5 (here labeled as service modules) to manage the system-to-database 1 6 1 5 8 'and core computing processes 1 6 Data flow of 1 5 6 °. 'Modify services 161 to 55 and import them to start the core computing flow 16156 to execute some calculation rules, integrate and format the content displayed in the GUI. Examples of this element are Java or Tel language, which can make the interaction between Gui easier by using embedded core database and by using HTML, XML, or dynamic HTML language. Such elements can also start the mathematical process and perform calculations to determine the correct dummy fill configuration in the layout.

This service module 1 6 1 5 5 is connected to the calculation core 16156 of processes and functions, and executes dummy filling calculation rules and complicated calculation procedures, such as process and electronic model and simulation process. This core is also included in the calculation. This calculation includes data, model parameters with pre-formats, images, or image formats, and indicators of files in the file system. This service module 1 4 3 5 5 can also be connected to the electronic design software or process layout information 1 4 3 5 7 such as the location and coordinates of the design target, and decide where to place the dummy filling unit. The database 1 6 1 5 8 is connected to the service module via the SOL command. 6 5 5 and uses SQL commands to manage system data, such as measurement location; user profile, package

l〇57-5667-PF (Nl) .ptd Page 216 200405184 V. Description of the invention (214) --- Includes limited permission and preferred content and presentation methods; user data, including layout extraction Layout design files, model parameters of specific tool trays, and overall = chip prediction results such as surface topology, resistance, and capacitance. The database used in the examples can be 〇racle, Inf〇rmix,

Access, SQL Server, Foxpro. The file system 16158 communicates with all elements to receive data and store it as a file, typically as large and inefficient storage in a database. This system can be connected directly to a measurement device to produce a measurement meter day. This connection can be done via computer network 161 59 or computer bus. ~ If block A 161 60 and block B 161 61 are located in the same computer, you can configure this system independently. If block A and block β are located on different computers and are connected through the network, the system is usually configured with a client-server structure. This network may include electronic and optical media via extranets, intranets, the Internet, or VPN. In the example, the blocks A and B may be part of a measurement tool, and the user 丨 6 丨 5 3 is a designer. This article does not fully reveal all the possibilities of the dummy filling method, but still provides some better operation components. This section deals with three types of basic calculation components, which are better methods of composing operation and transmission functions based on user needs. The first type of composition is an independent configuration, as shown in Figure 11 7A, where all elements (16154-16159 in Figure 116) are located in 16163, and the data in and out (16164, 16165) are obtained from a single computer. The second type consists of a client-server configuration, as shown in Figure 11B, where the GUI is located on a client computer 16 167 and accessed via a network 16 170 on a server or multiple servers.

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Other elements in the server architecture of the server 丨 6 丨 7 1. The connection mechanism can be an Internet, Intranet, or Extranet i 6 J 70, ^ J,, & service one or more groups of clients or users. The server can serve the second type of composition, as shown in Figure 1 1 7C, which is an extension of the client's prostitute type, including the connection through the network 1 6 1 76 to the system containing the second device, group elements (1 6 1 7 7-1 6 1 8 3) other computers. For example, 々 交 ^ 更 ^ It is generated by using a dynamic measurement meter through the temple server 161 80. Second, “the other computer can be used, where the server stores the process model and the remote 1 6 1 7 9 and the design. Specifications and restrictions 1 6 1 7 8. This network can also send data to the control computer of the measurement equipment 1 6 1 8 1 and return the actual measurement of the fruit to the server 1 80 , And the server with the tool through the network link or network service 16176, using the measurement function to improve the process parameter selection 182 or 16183. She also has

The architectures shown in Figures 11 16 and 11 7 can be combined with multiple weight measurement tools and used. 'The dynamic measurement software is installed on the server and communicates with the measurement tools via the network 1 6 1 94. This network may include an electronic or optical connection via an extranet, an intranet, the Internet, or a VPN. The structure of Fig. 118 shows a method of connecting users 16 184 and clients 1 6185 to a server or temple server group 1 6 1 8 6. The model 16187 is calibrated during each process step of the process flow. In this example, calibrations 16195 and 16196 can be performed in the models of process steps A 16188, B 16190, and C 16193. This calibration process model can be used as part of the method, as shown in Fig. 04, and the server 16186 generates measurement tools a 16189, B 16191, and C 16192 to measure the day. In this structure, you can include all the functions described in Figure 7C, such as

1057-5667-PF (Nl) .ptd

200405184

Use the measured shellfish as feedback for process optimization and dummy filling. e. Application of the method This method can be applied to a wide range of areas for the development of interconnecting materials. The measurement results will be measured in the measurement field in the tangent. This can be particularly pointed to the introduction of warfare technology. The copper trench manufacturing process requires the variation of the area of the mechanical polishing layer and the overall flatness. When more interconnects are added, the thickness of the film can be measured using a contour measurement method (such as multiple measurements). The measurement application structure and manufacturing process, test the structure of the amount of copper and low dielectric copper trench and low measurement to determine frankness. Available for pattern (metal) layer and optical reflection layer. The above-mentioned implementation and introduction of the conversion of low-dielectric measurement results, dielectric constant interconnection, dielectric constant material, electrochemical deposition, and auxiliary deposition will cause this change at most. The difference between quality and chemistry is worse, and the laser

In particular, this method can be used to determine the measurement location and sampling time according to the thickness of the electrochemical deposition (ECD) film and the dishing and erosion of the CMP layer. These wafer stage parameters are combined with electronic models to predict the electrical impact of the wafer to identify areas that may be problematic during measurement.

The electrical characteristics of the interconnect can be used to determine the electrical performance of the circuit, and the interconnect is usually the limiting factor for high-performance designs. This electrical parameter includes the interconnect resistance and capacitance. Circuit characteristics such as signal delay, clock distortion, and crosstalk noise are the parameters of the resistance and capacitance of the interconnect. The interconnect resistance is a function of wiring resistance, metal thickness, interconnect length, and line width. Inner wiring capacitors are metal thickness, inner wiring length, line width, line spacing, and wiring

1057-5667-PF (Nl) .ptd Page 219 200405184 V. Description of the Invention The dielectric constant of the insulator (oxide) between (217). The geometrical distribution of the interconnect structure affects its electrical properties. Therefore, the obvious variation of the geometric structure will affect the electrical measurement, so it is necessary to perform the same room measurement during manufacturing. Figure 119 shows a flowchart of how to apply it to the trench process. Same as shown in figure 丨 〇4, measuring 1 6034 £ 01) 161940%? Remove 16195, 01 ^ endpoint 161 96, and CMP barrier layer removal process 1 6197. Pattern auxiliary model 16033 'and used to generate the whole Wafer thickness, dishing, and erosion 丨 ⑽. Use electrical model 16 198 to generate overall wafer sheet resistance 199. Some of the electrical parameters that can be calculated include capacitance, interconnect delay, voltage drop, current loss, and dielectric constant. Or crosstalk noise variation. This measurement generates elements 丨 6 〇 3 5 Receive the design specifications and conditions, and compare with the overall chip parameters, as described in section c, 'Flags for certain specifications with errors or exceeding design limits are flagged Standardization is used for measurement and location storage. Upload the measurement location and sampling plan directly or via the network to the appropriate measurement tool 1 6 036. The operation method and system of the measurement tool are described in section d and Figures 1 15 to 11 8 The most common measurement tools used to determine flatness are contour measurement and optical methods. The most common tools used to determine electrical parameters are probe-type currents in electronic structures. Measure. This measurement It can also be used as a feedback to a dummy filling tool or process control system 162 〇〇, as shown in Figure 11 5D and section d. Please note that this method can also be used to determine the process shown in step 6333 f For intermittent measurement between steps. Please refer to Figure 丨 丨 8 for the implementation of this measure. Figure 11-9 describes the conditions for forming an interconnect layer in the trench process. Generally, the pattern of the lower interconnect layer Ancillary and film thickness variations will be passed to higher layers. This method can be extended to characterize and confirm wafer or wafer factors

200405184 V. Description of the invention (218) Problem areas formed by the layer pattern effect. As shown in Figure 120, the process flow model can be extended to predict multilayer effects and use this method to determine measurement locations that may violate design specifications. Figure 120 shows that the multi-layered pattern accessory model can be used to capture the effects between metal layer 1 17201, metal layer 2 17202, and some higher layers N 1 720 2. In this example, a pattern auxiliary process flow model 1 72 02 is performed on each layer. This molding can be used to characterize the multilayer effect and confirm the measurement location after the subsequent metal layer is formed. This measurement meter is transferred to the measurement tool 1 16 0 3 6 or a user or operator, and is used to guide the tool 1 6 0 3 9 after the process for wafer measurement 1 6 0 3 8. It is necessary to make the final completion loss to describe this method. "The thinness of the low dielectric constant material during CMP will affect the structural electrical properties of the crystal circuit. There are many problems to overcome when introducing low dielectric constant dielectric into the trench process. It is not easy to manufacture a low dielectric layer, and it is also difficult to maintain the dielectric constant after all integration steps such as etching the barrier cap on the copper and the CMP stop layer. Many low problems are the copper CMP step, which is low Dielectric Reed

Damage, dishing, and softness of 椤 a% to 20% of the shield will cause CMP damage, erosion, and subsequent electrical defects. This method can be combined with process steps to ensure area and overall flatness. '] Quasi-low-dielectric constant material, the instrument and the scanning probe microscope with “敕: f can use the stylus measurement and input. -Figure 1 2 1 in the process of the normal low-dielectric process For the flow chart, in this model, the-process is introduced into the trench process; the problem area formed by the introduction is based on the low-dielectric material and the application, and the thickness of the drawn film must be added to the measurement position of the process. , ~ Of the related electrical and structural effects

200405184 V. Description of invention (219) Process model. The low-dielectric material characteristics and manufacturing steps of the modularized I LD are added to the process by the user and calibrated for specific tools 17207. ~ This ILD layer is patterned using lithography and etching. The dummy filling material is placed in the low-dielectric layer to diagnose the structural characteristics of this layer. When entering the interconnection process, the expected effective dielectric constant is reached, and the spatial capacitance is reduced. A metal or copper layer 1 7209 is electrochemically deposited and the metal layer is polished using CMP. A three-step CMP process is generally used, including bulk lsh, endpoint, and barrier removal. The pattern attached due to the manufacturing process can be changed with the effective electrical characteristics, including characterization (including the use of wafer state models and changes in electrical parameters, 1 圆) to develop an overall wafer model to predict the effective dielectric constant of 208 /, a ' Such as the film thickness flatness, dishing, or aggression as a function, such as thin and thin film 1 and the electrical model of the capacitor 17213 transmission structure characteristics. ^ Γ difference, dishing, and erosion corresponding to the overall chip The electrical voltage drop, current loss, dielectric thunderbolt '= including electric coupling, interconnected delay, and forecast variation are based on the variation of disturbance noise. The methods described are compared with the conditions and conditions, using the sample book directly. The bite wisdom is measured from the position 1 6035. Upload this measurement position and the measurement tool to the appropriate measurement tool 16036. The measurement is in the 118 map. The system is described in the previous section d and 115. Using this method to measure and integrate the active area of the new process in the process of measurement, helps to flatten the thickness of the film. Most of them are familiar with a large amount of copper

Page 222 200405184 V. Description of the invention (220): The filling system uses an electrochemical deposition method to add various chemical mechanisms: 'such as a catalyst, a flattening agent, or an inhibitor to improve the flatness of the metal layer. Adding dummy filling structures to various chemical formula improvements can achieve better ... tank. Equipment manufacturers are also improving flatness mechanically. Nut 〇〇i 5ϊ ΐ A method ‘to rotate the wafer’ and introduce the plating spoon solution as a pad. The advantage of this contact flattening technique is that the copper film can be planarized simultaneously and regionally. Another advantage of this method is that it can reduce the copper content and the amount of copper that needs to be removed for subsequent CMP. This method can also be applied to any electrochemical mechanical deposition (ECMD process). The flow chart shown in Figure 4 can be used to import the calibrated monolithic ENCD model into the process flow. Under the condition that an attached model of the overall wafer pattern can be obtained, the above functions can be achieved in any process. The development model that captures the whole wafer pattern auxiliary model in plasma etching and lithography can be integrated in the process model flow of Figures 丨 丨 〇, 丨 20, [21]. This method is used in Figure 18 to identify problem areas after the process steps. However, this method can also be used in in-room measurement and comprehensive tools with multiple process steps. The same room measurement sensor and comprehensive tools can be used, that is, a combination of several tools and process steps into a large-scale equipment to achieve the functions described. Figure 丨 2 2 shows the similarities between the online measurement tool and the same-room measurement sensing and synthesis tool. For comparison, Figure 1 2 2 A shows the block in Figure 1 18 showing the application of online measurement tools in the process flow. (This process is described in Section d of Figure 118.) Figure 122B shows the similarities between using the same-room measurement sensor and a comprehensive tool. In this application, this method is performed on a computer 17215 that performs calibration on process models A, B, c, D, and E.

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l〇57-5667-PF (Nl) .ptd Page 223 200405184 V. Description of the Invention (221) The pattern attached is used to predict the overall crystal + According to the design specification of the c, that is, the measurement position is carried out, and the position of the fish is measured. Ye Yexi, $ said to use the steps described in the C, and /, the selection of the column I. Connect to the appropriate sensor or tool via the Silk Bus. 7217. / Connect to the same room embedded in the process tool β /,, li "丨 plan to recognise, say, step, say, say, rJ to li measurement sensor 1 7220, in the production of the selected test Obtain data from the location. = When in the same room / manufacturer of 1 722 2 in the comprehensive tool; Shidan also connected to this integrated tool to integrate multiple process steps, $, C1 7223, E1 7225. Online or same room completion volume Here, we can measure 1 72 4 ΛϋΥ on the line, and the gauge 4 is also connected to -lL々 ^ It is part of the comprehensive tool 1 7222. This description can be used any number of times. Wrong attempt to produce a better measurement book. For example, the second 2 s A is used to determine the quality of the materials *; not shown in the second picture, this contains-or multiple sets of locations inside the measurement 1, can be used across wafers One or more sets of crystal measurement are generated. In this application, the process wafer 1 7228 ϋ = coincidence 9. This method is used to measure the measurement of 17231 in the γ test for the security measurement determination system, such as Carry out two pre-wide use mistakes to taste the flow of the copper trench process she drew in Figure 1 1 3Α. Dagger, according to the selected position or position 1 723 1 Carry out the measurement 丨 This application is a measurement displayed on the manufacturing process line, but people who are familiar with this technique directly apply it to the same room measurement. The measurement system can be integrated in the measurement tool 'or communicated through a network or a bus. ', E ^ as shown in Figure 123B' Using this method can generate dynamic measurement of the measuring fixture 2 orders two in this application 'The measurement decision system continues to be based on known: the measurement of the other times to guide the measurement . Load this wafer into 6236

1057-5667-PF (Nl) .ptd Page 224 200405184 V. Description of Invention (222) 1 6 2 3 4 The method executed in the measurement decision system 1 6 2 3 5 generates the prediction 238 and selects the position 1 6 2 3 9 according to the repeated steps defined in the diagrams 3A and 113B. This measuring tool measures 1 6 2 3 4 such positions. Software is part of the tool or measurement decision system, used to determine whether the 1 6 2 4 1 measurement location meets the design specifications. In this example, it is to verify that all copper has been removed or ground removed at the measurement location. If this position does not meet the specifications or is not cleared, the output or copy process steps or scraping are performed. If it meets the specifications, you can predict other similar problem areas 1 6 2 4 2 and select 1 6 2 4 3 for measurement. Measure 1 6 2 4 2 Next selected position or position 1 6 2 4 3 and repeat the process (16245-16248) until the end of the wafer. Output to the next process 249. This application is shown on-line measurement in the manufacturing process, but those who are familiar with this technique can apply the same method directly to the same room measurement. This measurement decision system can be integrated into the measurement tool or connected via a network or bus. Integrated measurement tools allow more automated or shorter-range measurement steps. Using any number of erroneous attempts and this method, the measurement position is generated by the statistics or a series of execution methods shown in Fig. 3A, or the negative division or dynamic execution methods shown in Fig. 3B. Figure 1 24 shows two more effective error-tried ways to generate a dynamic measurement plan. Three sets of prediction blocks are used, P1 1 623 8, P2 1 6242, and P3 1 624 6, as shown in Figure 123B. Figure 124A shows the use of a single model calibrating a specific tool or recipe 1625 to generate an overall wafer prediction across one or more sets of wafers. Based on the largest variation, select a site for measurement 1 6 2 5 2. Use this location and prediction results from the model 1 6 2 5 3 Select another location for measurement

〇57-5667-PF (Nl) .ptd page 225 200405184 V. Description of the invention (223) 1 6254. The measurement model P2 1 65 43 can be the same as pi 1 625 1 or fine-tuned to accommodate the process drift measured at position 1 6 2 5 2 (this point is why the application shows different karyotypes). This model can continue to use position 6252 or 6254 to adjust the model 'and predict the position of the next measurement 62 56. This figure shows a simpler example, using a set of positions or cubes to perform the measurement tool steps one by one in the highest variation order, until the wafer measurement is ended in the wrong attempt. Process drift occurs when part of the manufacturing or measurement process changes as a function of operating hours and recalibration. For CMPs, drift usually results from abrasive pads. In some examples, the padding needs to be easily changed to improve the effective removal rate of the CMP model, but in other examples new calibrations are required. A stable measurement method is based on the prediction and position of multiple models calibrated based on different tool conditions, such as padding or different formulation conditions, such as grinding fluid flow rate. One way to implement this stable measurement method is to calibrate the model based on the data obtained at different points during the operating cycle of the process. In the example shown in Figure 124β, the three sets of calibrations shown, 16257, 1626, and 16263, were completed at 0, 100, and 300 hours on a particular polishing pad. Use this calibration model to generate predictions 1 62 58, 1 626 1, 1 6 264, and measure appropriate locations 1 625 9. The predictions do not match the actual measurements 1 262, 1 626 5 of such locations. This method allows erroneous attempts to be performed on a range of operating parameters to determine that drift has been taken into account. 1 An erroneous attempt is to use a selected measurement of model P1 1 6 258 to determine if a significant drift has occurred (if so, load Another model is P2 1 6261 and measurement is performed until a better model is determined. Figure 1 2 5 shows a more complete description of this stabilization method. The calibration model 16266 is used to generate an overall wafer prediction of one or more sets of cubes 1 626 7 Make use of

200405184 V. Description of the invention (224) Measuring thickness 1 6268 Recommended measuring tool 1 6270 and measuring position 1 6269. Complete measurement 1 627 1 and compare 1 62 73 measured thickness 1 6 272 with predicted thickness 1 62 78. If the error is lower than the critical value, then continue to use the calibration model 6 2 6 6 for direct measurement. If the error is less than the critical value, the measured thickness is compared to the database 16274 at the same position as the predicted thickness 16276, 16278, but a model calibrated by other process states or recipes is used here. 1 62 77. It is determined by least square regression (丨 ⑽ with squares fit) of measurement and prediction data position, or other numerical values or visible viewing methods. This prediction provides an optimal regression of 1 279 to produce a new prediction of 1 628. According to the new predicted chip topology, other maximum variation thicknesses are selected. Ding Cu: other positions that cannot be removed 1 6 282). Use this magic 62 = 3 to guide the inner measurement tool 1 6 2 8 4 to make a new measurement 1 6 2 8 5. Compare this measured thickness 1 6286 with the predicted thickness 1 6281 to determine the feasibility of the model and whether further measurements are needed.

This method ^ can be used in combination with IC-related CAD software elements to fine-tune the design rules based on the physical measurements and electrical properties of the film. The design rules for new κ designs usually self-test wafers and previous product packages. Because new designs do not have previous manufacturing data, the control bands of design parameters are usually naturally conservative (for example, values greater than necessary to accommodate unknown variations). This method can be used to confirm or fine-tune new manufacturing equipment, as shown in Figures 126A and 126B. In this method, the NEXCOM meter 1630 is uploaded to the system, and the layout capture is performed. The captured parameters were input into the calibration process 1 63 08 and the electrical model to obtain the film thickness and electrical 1 6 3 0 6. This characteristic can be used alone or in more extended circuit simulators to predict variations in circuit characteristics 16306. According to circuit design rules

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= 4 Compare this number of revolutions 1631 to the design rule limit τ to determine how much the design will be limited. This can be taken by the user ^. For example, this measurement can be a statistical critical value such as the standard deviation.

Speculation locations and recipes are stored in the system database or file system 1 632 1. The characteristics or locations of the wafers selected under design constraints are measured to confirm the predicted values. This method can use the same formulation where the variation exceeds the set rule, and provides the distribution of one or more parameters (such as thin film resistors). Use the position formula to measure the recipe. Transfer measurement recipes 16314 to online or in-room measurement tools or tools (such as optical reflection, contour measurement, or CD measurement equipment).

The device is physically manufactured (ie manufactured) on a calibration model for tool companion prediction. The actual wafer is installed by the person 1 (^ Layout 16316. In some examples, multiple sets of wafers can be processed to obtain statistical scores of measurement parameters = ,. The measurement recipe 16314 is used to measure the wafer or wafer of the process 1 63 2〇. Transfer the measurement to a component to evaluate whether the predicted physical and electrical parameters are supported by the actual measurement. Use this method to compare 6 324 measurement results 1 6 322 and predicted characteristics 1 6 324. If the amount The measurement results do not meet the prediction. It is recommended to use the process shown in Figures 124 and 125 to find a better measurement model in the system database to further improve the prediction. If the prediction parameters are confirmed, compare the measurement parameters with the design rules and Specification 1 6 3 2 6 ° Use this result to adjust design rules based on prediction and measurement variation to improve device performance and manufacturing possibility 1 63 28. This method can also be used to shake the design parameter control band, providing designers with more Flexible devices measure or further produce similar devices.

1057-5667-PF (Nl) .ptd Page 228 200405184 —— V. Description of the Invention (226) As mentioned in the previous paragraph, you can use the control of Taiji r ▲, especially the trench process: feedback from the group process In 丨 丨 Guangshi ^ i This private picture and pattern will be described in detail in the array control application. This description begins with the method attached to this method to generate CD and film thick sound ^ ° & ^, Λ, π guide film thickness tool measurement formula. This flow ^ The attached plasma of the pattern shown in Figure 104 is not included. Upload the “device layout to the system 1 633〇 .: = 7 to capture the characteristic characteristics accompanying the engraved map ° or model with engraving process The processes are combined and used. Get the whole number = 6 and calculate the accompanying electrical characteristics 1 6334. The design rules of this device "specifications (such as CD conditions) and the wafer upload 1 634, compared with the wafer and wafer conditions . Like forecast day and day film Based on comparison produce measurement formula. Using false attempts and their presence, the value determines the measurement of the selected location. For example, for a type of error, select $ to exceed the design parameters or a number within a preset range of design limits. Such erroneous attempts are shown in Figures 丨 丨 and 丨 丨 ⑺. The other two Θ attempts can also choose where the predictive parameters fall on the design parameters, and can be used to highlight the control band in the design rules. Such erroneous attempts ^: the paragraphs and the figures 126A and 126B. Store the last measurement recipe in the library or file system 1 6 344, and transfer it to a suitable measurement device, such as {膜厚 量 工具 34 6. The same process is used in Figure 1 2 8 A to show how the dynamic generation of the measurement recipe determines the feedback from the process control system. In this application, the method 1 638 2 attached to the money engraved pattern described in paragraph ^ is used to generate ⑶ and film thickness measuring tools.

Page 229 1057-5667-PF (Nl) .ptd 200405184 V. Description of the invention (227) 1 6 3 9 0 Measuring formula 1 6 3 8 4 The plasma etching control system 1 6 3 8 6 supplies recipe settings (such as etching trends) to the etching tool 6 3 8 8. Measurement tool 1 6 3 9 0 Use this method to generate a measurement recipe to measure the wafer and the position on the wafer. This indicates that the measurement results of wafer characteristics (such as aspect ratio) and wafer parameters will be fed into the process control system 1 6 3 8 6. This control feedback 1 6 3 9 2 can be a column measurement or an aggregate statistics or calculation, such as the measurement of the radiation flatness using the array thickness measurement. The control system 1 6 3 8 6 adjusts the recipe settings and uploads the etching process tool 1 6 3 8 8. Similarly, this method can be used to form feedback to control the CMP process, as shown in Figure 128B. In this method, a measurement tool recipe 1 63 54 is generated using a pattern attached CMP model or a model flow 1 E352 containing ECD or HDP and CMP. This CMP process control system generates recipes including pressure, slurry flow rate, or milling time. This CMP process grinds the wafer and measures it with a measuring tool 1 6 3 6 2 using a recipe 16 3 5 4. This measurement tool or tool includes optical reflection or profile measurement. Use this measurement as the control of the control system 丨 6 3 5 6 feedback 1 6 3 62. For example, it is used to adjust the grinding time for better cleaning results. Usually in the CMP process, the wafer center grinding rate will be faster than the periphery, and vice versa. Currently CMP grinding heads can adjust the radiation pressure to compensate for unevenness. This method can also be used to adjust the pressure of the CMP grinding head to compensate for the non-planarity ', and the measuring tool 1636 can be used to measure the residual film thickness on the line or in the same room. Similarly, this method can be used to form feedback for controlling the CMP process, as shown in Figure 1 28C. In this application, a pattern-attached lithography model (such as the model of the effect of specific density on the final mapped line width) is used. 1 6 3 6 6 Profit

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Using this method, the measurement formula 3 6 8 of the speculative tool 1 6 3 7 4 is generated. This lithography process control system changes the exposure control of lithography process 1 6372 and steps 1 63 7 0. Perform shadowing and measure the final wafer using the measurement tool 1 6 3 7 4 6 3 7 4. The measurement of the ray and the feature size are provided as the control feedback 1 637 of the lithography process control system 1 637 〇 to adjust the formula of the lithography process. This method can also be used to design test structures or devices, or to predict the characteristics of topologies and test structures, especially designs that are difficult to obtain. In this application, this method is used to predict the wafer topology. This method determines the largest variation in wafer characteristics from the design specification, as described in the previous section. Use this feature to design a test structure or device or guide a measurement tool to measure the test structure or device present on the wafer. _% As described in 28 26 in Figure 9 ^, this method can be used to select and synthesize recipes and equipment settings or select consumables (such as polishing liquid, polishing pad, gas component process steps or multiple process steps (such as process flow) , Minimize the process = variation and subsequent variation of electrical parameters. Change the model board prediction or prediction element captured at the lower level to meet the specifications of the next higher level, and consider the variation produced by the manufacturing. This method can be used for Device 1 660 8, manufacturing process 16610, and pattern auxiliary 1660 of manufacturing level 16612, and provide manufacturing process 16610 and manufacturing 16612 level for feedback to higher design levels (1 6 602- 1 6608), as shown in Figure 1 2 9 To provide an integrated process flow, a method is provided to predict physics (such as surface topology L and electrical characteristics (such as thin film resistors and capacitors) as a result of the process step range ', especially for specific tools and specific devices to be manufactured. This Advance

Page 231 200405184 V. Description of the invention (229) Testing can be widely used across structural variations, such as separate execution, or comprehensive implementation of 'so the device's manufacturing capabilities can be characterized' and help to develop subsequent processes or process flow Design rules. This method uses the calibration and prediction methods in Figures 109 and 110 to synthesize the integrated circuit pattern in the optimization of the process and the synthesis of the recipe, and generates an overall wafer prediction to compare the process and electrical parameters to the recipe parameters. Or variation of consumables. Such models can be formed at each step and calibrated for specific process tools. This model can also be integrated into the simulation process flow to provide parameter type predictions of the final wafer state, such as film thickness steps, array height, and electrical parameters such as resistance, capacitance, and crosstalk noise. This application can be used to select process settings, tool configurations, tools, etc. Figure 130 provides a simple example of process synthesis. The actual wafer process is within a certain range of tool or recipe settings. Four sets of process steps are considered here (ie ECD 1 6642, overall grinding 1 6 644, final grinding 丨 664 6, and barrier layer removal 1 6648). Consider three sets of tool recipe settings Λ, β, C for each process step. In step 1, the recipe setting a, b, or c is used to perform a process 16642 on the wafer 16666 with the topology. Complete each recipe or tool \ determine A, B, C, and physically and electrically measure the final topological variation, and compare 1 6 6 50. This comparison confirmed the recipe and tool 16658 with the smallest topological difference in the first process step. This wafer uses tool setting a-delay, 1 66 67 to use the second step process 1 6 644. Continue the etching process steps until the sister continues the four sets of process steps (1 66 42 — 1 6648) in this example. “Using this method to modularize and predict the variation of each process step. On the computer in the range of different designs and processes Perform process synthesis instead of actual

1057-5667-PF (Nl) .ptd Page 232 200405184 V. Description of Invention (230) For each circuit design, a lithographic mask and a process (manufacturing) are manufactured according to a process setting. Figure 13 shows how to use the same process synthesis as in Figure 130. Each process step, workmanship, and consumable combination has individual pattern attachments 'so it is necessary to use test or actual product wafer standards' as shown in Figures 107A, 107B, and 109. In this application, front and rear wafer state measurements are used to calibrate the molding of known recipe settings. In this example, there are three process settings, A, B, and C. For each process step (16684, 16686, 16688, 1 6 689), each recipe setting A, B, or C needs to be calibrated to generate a corresponding pattern attached to correspond to each setting. If it is within the set area, a general model of the complete operating area covering the known process steps is obtained. In the simple examples shown in Figures 130 and 131, the area of this single process parameter is defined by three sets of settings A, B, or C. However, this application can be applied to any number of process parameters, individual settings, and consumable groups (such as polishing fluids, polishing pads, gas combinations). Upload the new IC design to the system 1 6 6 8 2 and capture it. As shown in Figures 5a and 105B, a numerical table as shown in Figure 106 is generated. The calibration model of each recipe setting A, B, and C is loaded into 16698 and 16682 is retrieved to generate the physical or electrical topological prediction of the overall chip, as shown in Figure 110. To evaluate electrical variation, use RC acquisition tools or other electrical simulation tools in combination with physical topological predictions of the whole or part of the chip. The complete set of each formula is extended to the next process step 2 by 1 66 86. Until the recipe (16684, 16686, 16688, 16690) of all steps is set to complete the process. Evaluate all recipe combinations (or sequences) using prediction criteria.

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The example shown in Figure 131 has 34 or 81 different settings. When setting the criteria for a sequence in a good process, you can simply add up the average topological variation of each and every sequence, or use the cost function publicly more complexly, and calculate the weighting of multiple targets based on importance. Φ Generally use a certain type of cost function to characterize how to make certain dummy filling configurations meet the desired film thickness and electrical performance specifications. The cost function can be as simple as checking whether a certain film thickness non-uniformity threshold is exceeded, or as complex as a quadratic function. Variables include non-uniformity and unexpected electrical effects that can be minimized in feedback systems. A good dummy filling method will consider the process and electrical effects. The cost function is an example that can be used to minimize the following parameters: • Non-uniformity of thickness = (LW, LS, density) function • Electrical Efficiency = RC || Delay || Twist || Noise • Delay = Function of (R, C, L, Rtr, CL) • Twist = Function of (R, C, L, Rtr, CL) • Noise = ( R, CcoupU / Ctotal, L, Rtr, Tr, 1) where R = interconnect resistance

C = interconnecting capacitance L = interconnecting inductance

Rtr = drive resistance Ί; = signal rise time Q = load capacitance C_Ple = interlayer coupling capacitance

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Ctotal = total capacitance (combine + overlap + edge) 1 = interconnect length This cost is a quadratic error function U based on the weighted sum of process (film thickness) non-uniformity and electrical performance variation, where electrical performance As one or more of the following measurements: RC, delay, twist, noise.

ErrorT = (TtQT_ten-TQ ErrorEP = (EPtarget-EPactural) K2Error

EP U = (Er rorTT · K2 · E r rorT) + (Err ογερί where target = ^ ^ ^ * S'J ^ t

Tactural = vector of actual or predicted film thickness measurement EPtarget = vector of desired electrical performance measurement EPactUral = vector of actual or predicted electrical performance 湏 J vector ErrorT = vector of film thickness error

ErrorEP = row vector of electrical performance error U = quadratic error, a quantity value, minimized I = diagonal matrix, weighted along the diagonal component 1 to q total film thickness measurement wri 0 0 Κι = 0 0 0 0 WT ^ K2 = diagonal matrix, weighted along diagonal components from 1 to p

1057-5667-PF (Nl) .ptd Page 235 200405184 V. Description of the Invention (233) WSPI 0 〇 ^ 2 = 〇 ___ 〇0 0 wspp This cost can include the area of each signal line or chip. Using this method The film thickness vector and weighting matrix can be easily adjusted to provide the correct quadratic error that the overall wafer wants to minimize. Adjust the weighting parameters based on the element $ that needs to be minimized the most. This adjustment can be adjusted automatically or a weighted f case can be performed by the user. The additional parameters that need to be minimized in the cost function are environmental impact and energy parameters. Here, the external error E and the weighting matrix & can be introduced to take environment or energy parameters into account. Calculate 1 66 92 and store 1 6 694 Error for each formula series in Figure 131. Select Formula 1 6696 that produces the most expected results (eg, minimal error). When M receives a new IC design and designs the process flow, layout extraction is performed to characterize key features such as line spacing, line width, and effective density. Predict the pattern variation of the whole wafer, and use the cost function to measure the total variation of the known recipe.

Figure 1 31 shows the use of an exhaustive search to select each recipe selection combination and save the results. This method is not applicable to today's semiconductor manufacturing because the complexity and computational cost of analyzing every possible recipe combination is too high. As shown in Figure 32, the semiconductor manufacturer wants to develop a process flow to produce I c. The individual process of the knowledge base (Q χ mn) is generated by using the device specifications, design rules, and process limitations, where Q represents the number of devices, m is the number of recipe settings for each step, and η is the number of process steps.

1057-5667-PF (Nl) .ptd Page 236 200405184 V. Description of the Invention (234) This knowledge base may be quite large. Suppose a device requires n = 30 steps, and each step has m = 5 different recipe settings. The total number of such smuggling can be 530, and the number of possible processes increases exponentially with the process steps. The fake right wafer manufacturer wants to select a process flow to manufacture one or more devices, then directly multiply Q by the nth power set in the m group recipe setting. Therefore, when using the exhaustive search method in the simple recipe selection shown in Fig. 131, the size and complexity of today's semiconductor process flow need to be optimized using the method to determine the parameter selection, without having to exhaustively examine every possible setting. In multiple process steps, use the best possible method to synthesize the recipe setting or consumable combination, including the following steps: • Visual observation and selection from the map of the corresponding recipe for the mutation • Query form • Simplex (simplex) • Combined gradient method • Simulation training • Approximately linear stylization • Dynamically stylized • Approximately dynamic stylization The randomness and dynamic stylization method, through the cost function to follow the steps of the slave to find the best method, to minimize the pattern attached to one ~. This Taito Ida right from b or xi group

Combined with CMP process steps, etching, ECD known processes, recipes, and consumable combinations. Alien 1 ^ is described as process drift (progressive change) = b V entered eight Chinese 夂) or process shift (instantaneous

200405184 Invention Description (235). You can also use the attached model of the pattern to select recipe settings and consumables based on the process of variation over time. Figure 3 shows how to use the satellite model to characterize the process variation over several hours. The test wafer 16802 is manufactured at a certain time period t using a recipe setting of 1 6680, and is measured from one or more sets of crystal cubes on the wafer. The recipe setting i is used to process the test wafer 6 8 12 during the time period t + 100 hours, and the measurement is performed on one or more sets of crystal cubes on the wafer 6 6 丨4. This process can be repeated for 2 to N total recipe settings or consumable combinations. The test wafer 1 6 803 process uses a recipe setting n at a certain time period t, and measures 1 6 6 1 8 from one or more sets of crystal cubes on the wafer. The process of testing wafer 1 6 8 0 5 at a certain time period (such as t + 100 hours or t + 1 000 wafers) uses a recipe setting of 2 1 6 8 2 2 and one or more wafers from the wafer. The measurement is performed on the group crystal cube 6 6 2 4. Use each 2 xN total data set to calibrate a separate model, as shown in the steps of 107A, 107B, and 109. This type of model shows the operating space of n sets of recipes and the operating space of 1 000 hours of tools 1 6 824. This type of model can be used in the new design of 16 826 to predict the pattern-dependent variation of a 16828 process that exceeds a certain operation hour or a certain number of wafers in the process (such as 100 hours or 100 wafers). This can be regarded as the process synthesis and process drift and displacement selected by the process setting. This method can be used to calculate control and measurement strategies for known process steps or tools. For example, if it is found that the process drift is caused by the specific sidewall effect of plasma etching, you can use the method shown in Figure 10 to schedule the next plasma chamber cleaning operation. The interaction between design and manufacturing companies is shown in Figure 34. Process and tools

〇57-5667-PF (Nl) .ptd Page 238 200405184 V. Description of the invention (236) Material 16902 is uploaded to the system 16906, and the calibration model is established as shown in the steps of 107A, 107B, and 109 to establish the calibration process. Program database 16 9 08. This data can come from multiple tool settings, tools, consumable combinations, process flows, or production lines. Semiconductor companies can upload designs 1 6904 and use systems and models to predict or simulate the physical and electrical behavior of this design. Generate design prediction database 1 6 9 1 0. Semiconductor company 1 6 9 1 8 can use internet connection and internet to watch the results 1 6 9 1 4. The equipment or consumable supplier 1 6 9 1 6 can use Internet connection and web browser to view the result 169 12. This result can be provided to equipment and consumable suppliers and semiconductor design and manufacturing companies to analyze and diagnose tools or consumables 1 6 9 2 0. Additional diagnostic methods can be used in conjunction with the system and the server to improve remote diagnosis. This is especially helpful for long-distance analysis and diagnosis. This method can be used to compare semiconductor design and manufacturing company consumable combinations, equipment, or tool settings. In this use, the tool or consumable $ supplier 1 695 2 provides the manufacturing resources of the consumable set 1 69 54, 1, 69 56, 1 6958 ^ to calibrate the process model or process in the system 1 6 95 0, such as 107A , 107B, 1 () 9 as shown in the figure. Companies 1 694 0 can upload designs 1 694 8 and generate forecasts for different tool or consumable combinations, and compare the results 1 946. Companies 1 694 〇, 彳 1 6942, 1 6944 can use this result to select or purchase a specific combination of consumables or tools. This method can be used in the shallow trench isolation (STi) process flow. The STI is made of a dielectric material to fill the trench, and provides less insulation between adjacent devices. The ST I process includes the following steps: 1. Forming a pad oxide layer-usually using a thermal oxidation process to form a pad oxide

200405184 V. Description of invention (237) layer. 2. Deposition of a nitride layer-Use CVD to deposit a nitride layer on top of the pad oxide layer. 3 lithography mapping groove geometry _ Use the lithography process on the wafer to say: i 3 shot groove size. The photoresist mask makes the feature size indicate the position of the engraved mark. Bech L Etching Trenches—Using nitride layer etching and silicon etching to form deep trenches (such as 5000 angstroms) in the lithographic trench area. Repeatedly 5. Fill the trench—Remove the mask and fill the trench with the oxide layer of the CVD process. The deposited oxide layer forms a thick: south region on the nitride layer). #Thin groove 6. Remove oxide layer-Use CMP to remove all oxide materials on the nitride layer. The purpose is to form a gradation that combines the materials of the oxide layer and the nitride layer. One increase 7 · Remove the nitride layer and pad oxide layer-remove the nitride layer and pad hydrogen: = layer trench and exposed silicon layer. In a subsequent step, a transistor will be formed in a clean area between the grooves. The purpose of the oxide layer trench 1 6 962 in the f f layer 1 696 0 is integrated in the figure and figure. The pattern attachment of the CMP step usually causes oxide layers, removal or dishing 1 69 66, as shown in Figure 136B. Oxidation in the trench: It will significantly affect subsequent process steps, such as defining the active area of the device " spot isolation bar and electrical effects after forming the device. The physical sag in the trench region of the milk and k ion & oxide layer will affect the formation of interpolar features between the subsequent layer and the polycrystalline stone, leading to unexpected

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Page 240 200405184 V. Description of the invention (238) characteristics, such as changes in threshold voltage, increase in leakage current, or polycrystalline silicon bridges, reduce the performance and stability of manufacturing equipment. In these examples, the dishing caused by the pattern attachment of the CMP will form a corner rounding phenomenon at the interface between the active device and the isolation area. This method can also be used in the ST I process flow, including the prediction of pattern attachment when a ST I trench is formed on a wafer when a new dielectric material is introduced into the process. In the application shown in Fig. 137, the calibration pattern shown in Figs. 107A, 107B, and 109 is used to form a prediction pattern attached to the I model. This calibration process can utilize STI-characterized wafers designed to obtain such features. Upload this STI design to the system 1 6982, and execute the numerical table about the pattern sensing of the STI design as shown in Figures 105A and 105B. Use this model or model to predict the final groove geometry 1 6986. This model C: type = or lithography. Then use this final trench geometry * electrical im ”i 699〇 to influence the electrical characteristics, such as leakage current, = benefit: connection phenomenon, and the performance of the overall device to add an oxide trench to form a dummy fill It is specially measured and adjusted in the salt solution to reduce or minimize the dishing, and adjust the correction pattern, so various types of dummy filling techniques shown in Figures 16-25 can be used. This application can use the 4th Anyone who is familiar with this technique can make changes and retouches without departing. Therefore, the scope of the patent application for the spirit and scope of the present invention shall prevail. The scope of protection shall be attached as attached.

200405184 Schematic description of the flow 2 2 shows the general design and development of integrated circuit devices. 图 1 y shows that the design process is not improved by using one of the methods of the present invention; Section 2A: shows the use of the present invention One method is to improve the manufacturing process; the round surface wheel ΐ f is not used in the copper trench manufacturing process, and the ideal perimeter oxidation area of the CMP process is generated =: = dishing occurs on the line and the plastic opening: field area · 'contains copper wire ... There is a large 2D picture showing the addition of metal dummy filling to increase the effective density of the metal 'and obtain a better flatness of the film thickness after CMP; Figure 3 A shows a large metal field area; Figure 3 B shows Oxidation dummy filling is added to the metal area; Figure 4A shows a symmetrical dummy filling pattern; Figure 4B shows an asymmetric dummy filling pattern in a single direction; Figure 4C shows an asymmetric dummy filling pattern in two directions Figure 5A shows the use of ECD to fill a trench in the oxide layer; Figure 5B shows the initial state of depositing copper in the trench using e CD; Figure 6A shows the deposition in the trench The most copper Status; Figure 6B shows the copper deposition that was exceeded by CMP polishing; Figure 7 shows the calculation flow of the complete dummy filling method; Figure 8A shows the variation of KD deposition thickness, such as the result of a pattern attached, such as the width With narrow wires

〇57-5667-PF (Nl) .ptd Page 242 200405184 Brief description of the diagram Figure 8B shows the use of oxide dummy filling to achieve a flat ECD film thickness; Figure 9A shows the relevant steps for layout extraction; Figure 9B shows the continuous steps of layout extraction; Figure 10 A shows the adjacent structure of the target A; Figure 10 B shows the distance between the target A and B; Figure 10 C shows the closer and farther The distance between the targets; Figure 10D shows how the grid boundary is adjacent to the target; Figure 11 shows the relationship between the two spatial regions on the chip and the layout extraction table, and Figure 12A shows the use of product crystals. Circle to a specific recipe to calibrate a tool; Figure 12B shows how to calibrate a tool to a specific recipe using test wafers; Figure 13A shows how to use calibration to map layout characteristics to film thickness variations; Figure 1B Figure 1 shows the use of calibration to predict the film thickness variation of the new IC design. Figure 1C shows how to use wafer state parameters, such as film thickness variation, to predict electrical parameters. Figure 14 shows the calibration process steps and generates a Model steps Cheng; of FIG. 15 show the use of a calibration line model generates a prediction of the flow step;

1057-5667-PF (Nl) .ptd Page 243 200405184 Brief description of the diagram Figure 16 shows the flow of steps for generating dummy filling rules and forms; Figure 17 shows a sampling dummy rule table, the maximum dummy filling The input line width is a function of the inner line width and line spacing. Figure 18 shows the process of measuring the size and configuring the dummy filling. Figure 19 shows the configuration of the dummy filling target in a block. Detailed steps and procedures; Figure 20A shows an example of measurement dummy filling rule; Figure 20B shows an example of dummy filling pattern generation rule; Figure 2A shows a symmetrical dummy filling pattern Figure 21B shows another dummy filling pattern with the same density, but using a different filling target size; Figure 22A shows the use of 1x2 units to generate 2x4 units; Figure 22B shows the use of 1x2 units to generate 4x4 units; Figure 23 shows how to represent 4x4 units with 8 sets of targets; Figure 24 shows the process of forming a unit hierarchy; Figure 25 shows the use of a dummy filling method with a low dielectric layer to adjust and modify Figure 7 Dummy filling method Figure 26 shows the calculation structure of the dummy filling method, which can also be used as a dummy filling system. Figure 2 7A shows one of the dummy filling systems installed in a single computer. _ Independent execution method; Figure 27B Figure 1 shows a client-server implementation method of a dummy filling system; Figure 28 shows an extension of the client-server implementation method, including

1057-5667-PF (Nl) .ptd Page 244 200405184 The diagram briefly illustrates the external components on a network; Figure 29 is used to show the general client_server virtual filling of the internal network, external network, or the Internet Network; Figure 30 shows the second client_server architecture of a better calculation of the surname network service that is filled into the system in a virtual way; Figure α shows how to use the network service with Figure 31 Dynamically created as a virtual filling network service; Figure 32, shows the system of the virtual filling system: before the bureau to the virtual filling system ™ component force: Figure 33 shows the virtual filling system Analyze and configure dummy fills when adding elements; ..., use, * in the layout Figure 3 4 shows the need to take the day and time to manage the messenger ^ 蛊 bureau manager GUI screen operation section 35A Figure A: Cloth and layout capture; Fruit, fruit, fruit, fruit, fruit, fruit, fruit, fruit, fruit, fruit, fruit, fruit, fruit, fruit, fruit, fruit, fruit, fruit, fruit, fruit, fruit, fruit, fruit, fruit, fruit, fruit, fruit, fruit, fruit, fruit, fruit, fruit, fruit, fruit, fruit, fruit, fruit, fruit, fruit, fruit, fruit, fruit, fruit, fruit, fruit, fruit, fruit, fruit, fruit. Figure 36A shows the dummy; the knots filled in by the metal before, before, and the figure 3 6 β are shown. Set 7;, 糸 ,,,,,,,,,,,,,,,,,,,,,,-succeeded, oxide-filled knots Figure 37 shows the use of μμ to grab / result, where μ @ @ 卢 真 糸 糸 is configured with metal dummy-filled, and thus from The system selects the size and pattern to minimize the electrical impact;

200405184 Brief description of the drawings. Figures 3 and 8 are screen shots showing the tool type information that can be used under the manufacturing elements of the dummy filling system. Figure 39 is a screen shot of the comparison tool GUI showing the overall chip image. Figure 40 is a comparison tool GU I which provides a comparison tool that displays the overall wafer statistics. Day 41 is shown in Figure 41. Figure 41 shows how to perform the lithography process. Figure 42 shows the use of c design and pattern manufacturing. Lithography mask process; Figure 43 shows the proper focus distance of the alignment key, but the wafer level _ variation exceeds the depth of focus limit; Figure 44 shows the lithography process suitable for the trench process; f 45 shows Pattern attached to the electroplated copper deposition (ECD); Figure 46A shows the CMP film thickness variation due to oxidation; '% 双 々 二 Figure 46B shows the use of shallow trench insulation π 乂 电 II Zuoli, L, One by one ^ w ^ ^ ^ 1 1; m = invasion, dishing, and corner rounding effect of producing Λ; Figure 46c shows the copper dishing accompanying the use of shallow trench insulation (sn) borrowing steps , Jie Lei quality: "" W of CMP 47All # Ss Electricity and residual copper effect; f47A is a full-scale pavilion with different density characteristics in the area showing no squares; Figure 47B is a display area and a picture of 'Chu 4 »Gangzhan Mud-Dark Emulsion The thickness of the layer changes. Back, ... How does the surface topology affect 〆, Figure 49 shows how the characteristic density affects the size; Figure 50A shows the high-level method of the method ㈣ special break size;

200405184 Brief description of the drawings 1 Figure 5 0B is a high-level flowchart showing how to change the design; Figure 5 0C is a high-level flowchart showing how to correct the reticle; Figure 51 shows how to adjust the design to match the expected mapping Figure 52A shows the application without adjusting the design to match the expected mapping or etching feature size. Figure 53A shows the steps typically used for layout generation.

Figure 53B shows the general steps for layout generation when design changes are added to the design flow; X Figure 5 4 A shows the relevant steps for layout extraction; Figure 5 4 B shows the relevant steps for layout extraction Continuous steps; Figure 54C shows the relevant continuous steps of layout extraction; Take the table; Figure 55 shows the relationship between the two spatial regions on the chip and the formation of the layout Figure 5 6 shows the process model elements · Figure 5 7 A The display shows the use of square tools; the product wafers are used to calibrate a specific recipe; the fifth display shows the use of test crystal κ pairs-a specific recipe calibration process Figure 58 shows how to produce variation; 7Using the right to map the layout features to the thickness of the film. Figure 5 9 A shows the use > ^ ^ s. Uses the technical correspondence to predict the thickness of the thin film of the new IC design. Round state parameters such as film thickness

1057-5667-PF (Nl) .ptd Page 247 200405184 The diagram briefly explains the variation and predicts the electrical properties. 11 Picture 60 shows' 1-2 Picture 61 A Picture _ The steps of the cadaver and the correct schedule; page 6 1 Figure B shows the steps to predict the overall wafer topology. Figure 6C shows the steps to predict the wafer topology. Figure 61D shows the continuous steps to predict the wafer topology. Figure 62A shows the predicted wafer topologies. The continuous steps; The characteristic dimensions (such as line width) are not predictable due to the lithographic process steps or processes. Figure 62B is shown_ > Figure 63 is shown ^ —the corresponding situation of the predicted elements; Figure 64 is Xianhe lithography predicts the corresponding situation of the elements; the measurement steps; the feature size variation based on the wafer topological variation is shown in Fig. 65; the X Ba film feature density is generated in the feature size variation is shown in Fig. 66A _ _ Fang Lithography model; test wafer calibration is not used for specific tools and matching 66B image system _ ^ difference; calibrating lithography model is not used to predict feature size changes. Figure 67 system display + α button &steps; The quasi-lithographic model predicts the variation of feature size in Figure 68. Display-Confirmation and Calibration Oct-membered, image transmission, an acknowledgment option A ': _ a confirmation of the alarm system of option B;:; _ based on FIG. 69C shows the confirmation step c options;

1057-5667-PF (Nl) .ptd Page 248 Brief description of the drawing No. 6 9D picture display confirmation No. 7. The diagram shows two steps of correction; = 7. The diagram shows the calculation layout. The 72th diagram shows the use of test steps. The calculation of the layout adjustment and correction of the 73A diagram shows the feature size prediction surface of the surface topology component. The relationship #; pull-type prediction and the use of lithography mode to improve the mapping error and the expected size. Adjust the layout. Γ Off 4A: The τ program shows the calculation of the feature width. ㈣ The 74β picture shows the surface width and features. The relationship between the distance m and the ten parameters, such as the characteristic ^ 7ΛΓ m〆 and the density before turning into the lithography model; the special η palace V hand shows how to use the test wafer to calculate the known height or thickness: the width The mathematical relationship between the feature distance and density; Figure 75 shows how to use the process to repeatedly perform multi-level and weight correction; Figure J76A shows the steps for testing wafers using lithography; Figure 76B shows the correlation of test wafer parameters An example of a form; = 77A shows a stack of lithographic test wafers; f77B® # 'shows the metal layer 1 of the lithographic test wafer Figure 77C shows the plug layer 1 of the lithographic test metal Figure 77D Strict Shadow test wafer metal layer 2; Figure 78 shows a cross-section with varying line width and line spacing in metal layer 1

Page 249 1057-5667-PF (Nl) .ptd 200405184 The diagram is a simple explanatory diagram, and Figures 7 and 9 are sectional views showing the fixed line width and line spacing in metal layer 1. Figure 80 is shown in the metal layer. The secondary cross-sectional view of changing the line width and line spacing in Figure 2; Figure 81A shows the pattern of metal layer 1 and metal layer 2; Figure 81B shows the metal layer 2 overlying metal layer 1; Figure 8 2 The array structure in metal layer 1 is shown changed. Figure 83 shows the large-sized plug array in plug layer 1. Figure 84A shows the patterns in metal layer 1 and unplug layer 1. Figure 84B shows the overlay. The plug layer 1 pattern on the metal layer 1 pattern; Figure 85A shows the slit structure of the three regions in metal layer 1; Figure 85B shows the slit pattern of the three regions in metal layer 1; Figure 85C shows The plug pattern in the plug layer 1 covering the slit structure of the metal layer 1; Figure 85D shows the metal layer 2 pattern covering the plug layer 1 and the metal layer 1 pattern; Figure 86A shows the surface topology Application of the method; Figure 86B shows the effect of the method when surface topology occurs; Figure 87A shows the feature density Application of the method; FIG. 87B based on the display method when the impact occurs when the feature density; 88 FIG display system using a stepper mechanism to resolve the surface of the wafer level variability;

1057-5667-PF (Nl) .ptd Page 250 200405184 Simple description of type 1 __ Figure 89 shows the use of a stepper to move away, and includes the focus depth, external alignment, and better focus distance. Figure 90 shows Wafer layer = map of stepper domain; Figure 91 shows the method of using computer hardware and software; Method of operation; Application of body and network equipment Figure 92A shows the installation of client software and integration in Execution method in a single computer · J service or other 92B picture shows the method of connecting via the Internet; each house, and the server implementation 9 2 C picture shows the client connection and feeding services Method of implementation; Gen Yi and Figure 93 show the electronic design automatically through the Internet); G's yoke method (EDA tool Figure 94A shows the application using the EDA tool. Figure 9 4B shows via the network Road connection EDA Industrial Beans _ Figure 95 shows the implementation of the manufacturing system design: Use "仃 application" Figure 9 6 shows the beginning of the manufacturing system's rhetoric * Shadow related tool settings, recipes, or;: Use ... to select the micro-picture 97 to show the layout capture without management from multiple designs gui. Figure 98A shows the chip width extraction agency showing the layout of the chip: Figure 98B shows the last name extracted according to the width of the chip. Figure 9 9 Α shows ... the first design of the G υ micro-system Entered into the design of the manufacturing system; Figure 99B shows the management tool and 1057-5667-PF (Nl) .ptd in the design of the manufacturing system or lithography. Page 251 200405184 Schematic illustration of the tool recipe; --- Fig. 100A shows how to use the method to generate a three-dimensional characteristic. Test 4 He-shaped drive. Fig. 100B shows a circuit that uses a 10mm wiring input and a wheel-out actuator. 单一 The first single Figure 0 0 C shows the circuit using the convergence buffer. · Figure 1 0 0 D shows the circuit without the convergence buffer. Figure 1 0 A shows the measurement of the lack of information on the problem area on the chip. This problem occurs when testing the specifications of the whole helmet a 7 3 of the key helmet method; the problematic structure of the mouth, the sun, the moon and the moon. Figure 1 0 1 B shows the specifications of the dynamic measurement meter during the day. ^; Of 'it can be confirmed that the picture 102A shows the thin film caused by the oxidation of CMP and the picture 102B shows Using shallow trench insulation, the CMP step i 02C accompanying the invasion of silver, dishing, and corner rounding process in step i 02C shows the copper dishing, dielectric erosion, With the residual copper effect, the 10th 2D map showing the flattened long sound II; the top view of the degree feature; the different dense 02E maps in the X-shaped area are shown in the flattening change; the degree of special desire The thickness of the oxide layer is changed. The 1 0 3 A picture shows the trench. The 1 0 3 B picture shows an unexpected increase in the resistance of the two wires. The ideal result of copper CMP during the process. The copper residue on the metal wire leads to gold.

200405184 Brief description of the diagram. Figure 1 03C shows the formation of a copper dishing on the two metal wires, which leads to an unexpected increase in the resistance of the metal wire. Figure 104 shows a high-level flowchart; f 105A shows the layout. Relevant steps taken; f 105B / shows successive steps related to layout extraction; Fig. 106 shows the relationship between the pitch areas in the wafer and the formation of the layout. Fig. 07A shows the use of product wafer pairs. A specific recipe calibrates a tool 苐 10 7 B shows the calibration process of a specific g alley using a test wafer

Corresponds the layout characteristics to the thin family to predict the film thickness of the new IC design. Figure 1 08A shows how to use the calibration thickness variation; Figure 1 08B shows how to use the calibration to change the variation of the integrity; ~ Figure 1 0 8C shows How to calculate the variation and predict the electrical parameters; B indicates the circular state parameters, such as the thickness of the thin film. Figure 10 shows the calibration process. Figure 11 shows the steps to know the steps and generate a model. Figure 110 shows the use of calibration. The variation of the electrical parameters and performance variation of shadow / fork type prediction process and the subsequent Figure 111A shows how to make the gripper private, and Figure 111B shows how to predict 31-type prediction; the measurement position; using prediction and design specifications to Select chip

1057-5667-PF (Nl) .ptd Page 253 200405184 The diagram is briefly explained. Figure 111 C shows the display screen of the measuring meter day. Figure 11 2 shows how to generate an overall wafer measurement check. ^ The detailed steps 113A and 113B show a mistaken attempt form, and measure the day; to produce an error. Figure 11 A shows a linear diagram used to characterize the thickness variation of the overall wafer or crystal film; daily changes, thin Figure 11 4B shows how much of the wafer-level variation on the wafer is selected and characterized. Shows the relationship between the crystal square variation linear graph and the crystal: special linear pattern; /, 9 111 level variation 橹 The 11 4C graph shows the selection and characterization of the polymorphic wafer-to-wafer variation on the wafer. This method is performed on the wafer in the process cycle. Figure 5A shows the application of the measurement tool. Figure 115B shows the application of the measurement tool. Adjust or re-calibrate the process model; “彳 Tool 11th 5C shows the use of the amount to adjust or recalibrate the process model; The application is deleted from the tool 11th 5D Figure shows the use of the measurement tool to provide feedback to Process optimization or formulation: human thread, process control, 7, non-verbal system, and a dummy fill in the project ^ Figure 11 6 shows the pole &t; -Server operation ^ Only network operation of this method;

1057-5667-PF (Nl) .ptd Page 254 200405184 Simple explanation of the diagram Figure 11 8 shows the use of multiple weight measurement tools in the process flow; Figure 11 9 shows the use of the trench process flow Operation method; Figure 1 2 0 shows the operation method of the multi-level process flow; Figure 1 2 1 shows the operation method of introducing the low-level power station in the trench manufacturing process; μ Figure 1 2 A The operation method of the online measurement tool; Figure 1 2 2 B shows the operation method of the same room measurement tool; Figure 1 2 3 A shows the loading method / method of the measurement formula before measuring the wafer; < Operation Figure 1 23B shows the operation of repeatedly adjusting the measuring position when the measurement is started; 〃 Figure 1 2 4 A shows the operation method of repeated or dynamic measurement of multiple processes based on previous or wrong attempts to predict parameters ; Figure 1 24B shows the operation method of repeated or dynamic measurement of multiple processes when displaying multiple types representing different process states; Figure 125 shows the use of actual measurement from the data selection type to generate the measurement formula. Method of operation Method of operation Figure 126A shows the operation of generating a measurement recipe to adjust the design rules. Figure 1 26B shows the operation method of using the measurement recipe and the design rules or specifications. Γ The operation method of using electropolymerization to produce the speculative formula of ⑶ and film thickness tools;

200405184 Brief description of the diagram. Figure 1 2 8 A shows the operation method that provides feedback to adjust the plasma etching recipe or control settings. Figure 128B shows the operation method that provides feedback to adjust the CMP recipe or control settings. Figure 28C shows how to provide feedback to adjust the lithographic formula or control settings. Figure 1 29 shows the process integration. Figure 130 shows an example of process integration. Figure 1 31 shows the integration. The application method of Φ to model-based prediction. Figure 1 32 shows the calculation conditions with integration. Figure 1 3 3 shows the application method combining process drift and displacement. Figure 1 34 shows the promotion equipment and consumable suppliers. Application method for interaction with semiconductor design and manufacturing users; Figure 1 3 5 shows the application method of comparing equipment or consumables; Figure 1 3 A shows the result of expected shallow trench isolation; Figure 13 6 B The figure shows the isolation trench dishing phenomenon caused by grinding; and Figure 137 shows the application method of the STI process flow. Explanation of symbols: 1, 2, 10, 15, 17 ~ copper; 3, 5 ~ was expected wafer surface after CMP; 4, 9, 1, 3, 24, 29 ~ oxide layer (or field oxide layer);

200405184 The diagram briefly illustrates the actual wafer surface after 6 ~ CMP; 7 ~ dish sinking; 8 ~ extravagance; 11, 16 ~ dummy filling area; 1 4 ~ metal dummy filling; 1 8 ~ oxidation dummy filling ; 19, 23, 27, 28 ~ trench; 21, 22 ~ key bond layer; 40, 42, 46, 47 ~ deposited copper thickness; 41, 48, 1 2 0 7 2 ~ narrow line width; 43, 12086 ~ Wide line width; 4 4 ^ emulsified dummy pillars, 45 to 46 trench thickness 46 equal to thickness 47; 50-63 to standard; 1 7 6 to dummy filled structures in the oxidation zone; 177, 179, 182, 183, 188 ~ metal wire; 1 7 8, 1 8 1 ~ dummy filling structure of oxide in metal wire; 1 8 4, 1 8 7 ~ asymmetric metal dummy filling structure in oxidation zone; 1 2 0 1 0 ~ light source or Laser; 12 012 ~ light and energy; 1 2 0 1 4 ~ condenser lens; 12016 ~ photomask; 1 2 0 1 8 ~ shrink lens; 1 2 0 2 0 ~ crystal cube;

1057-5667-PF (Nl) .ptd Page 257 200405184 Brief description of the drawing 1 2 0 2 2 ~ wafer; 1 2 0 2 4 ~ focal distance; 1 2 0 2 6 ~ test or alignment key; 1 2 028 ~ Focus Depth (D0F); 1 2 0 3 0 ~ Surface variation of the wafer; 1 2 0 3 2 ~ Area on the wafer where the line width does not match the design line width 1 2 1 0 2 ~ Full non-flatness; 1 2 1 0 4 ~ region step height; 12106 ~ low density metal line; 12108 ~ high density metal line; 12110 ~ protruded oxide layer area; 1 2 111 ~ silicon; 12112, 12120 ~ silicon dioxide; 1 2 11 4 ~ silicon nitride Erosion; 1 2 11 6 ~ corner rounding; 1 2 11 8 ~ oxide layer dish; 12122, 121 26 ~ copper; 1 2 1 2 4 ~ copper dish; i 12128 ~ dielectric dish; 1 2 1 3 0 ~ Residue of copper; 1 2 1 3 2 ~ Flattening length; 1 2 1 3 3 ~ Lower characteristic density; 121 34 ~ Raised oxide layer area; 12135 ~ Lower oxide layer density;

1057-5667-PF (Nl) .ptd Page 258 200405184 Brief description of the drawing 1 30 5 0 ~ Metal 2; 1 3 0 5 1 ~ Plug 1; 1 30 52 ~ Metal 1; 1 30 54 ~ ILD; 1 3 0 5 5 ~ silicon wafer; 1 3 1 0 0 ~ change line width and line spacing; 1 3 1 1 0 ~ line array with change line width and line spacing; 13124, 13210 ~ metal layer 1; 13126 ~ metal Layer 2; 1 3 2 0 0 ~ change the array size structure; 1 3 2 11 ~ large array structure; 1 3 2 5 0 ~ change the slit structure; 1 329 9 ~ ILD layer; 1 3 3 0 0 ~ overlapping line width And line spacing; 1 3 4 0 0 ~ fixed size / space plug array; 1 340 1 ~ overlapping line width and line spacing; 13410 ~ plug layer 1; 1 3 4 1 2 ~ large plug array; 13500 ~ fixed Dimension / space plug chain; 1 3 5 0 1 ~ overlapping line width and line spacing; 1 4 2 0 0, 1 4 20 1 ~ wafer; 1 4208 ~ wafer surface A; 1 4209 ~ wafer surface B; 1 4 2 1 0 ~ wafer level variation;

1057-5667-PF (Nl) .ptd Page 259 200405184 Brief description of the drawings 14212, 142 14, 1 42 22 ~ Align or test the photomask; 1 4 2 1 6 ~ adjustment; 14218, 1 42 2 1 ~ focal length (F); 14220, 14223 ~ photomask with 1C pattern; 1 4 224 ~ wafer (or crystal) level variation; 1 4 226 ~ D0F limit; 1 4 228 ~ feature exceeds CD variation specifications; 1 6 0 0 3 ~ Comprehensive non-flatness; 16 0 4 ~ area step height; 16 50 0 1 ~ low density metal wire; 16 50 2 ~ high density metal wire; 16503 ~ raised oxide layer area; 16005, 16960 ~ Shi Xi; 16001, 16010, 16006, 16017, 16018, 16021 ~ silicon dioxide; 16 0 7 ~ silicon nitride erosion; 16 0 8 ~ corner rounding; 16009 ~ oxide layer dishing; 16011, 16012 ~ copper; 16013 ~ copper dish sink; 16014 ~ dielectric dish sink; 1 6 0 1 5 ~ copper remnant; 1 6 0 1 9 ~ copper remnant caused protrusion or short circuit; 1 6 5 2 1 ~ flattened length;

1057-5667-PF (Nl) .ptd Page 260 200405184 Brief description of the drawing 1 6 522 ~ Characteristic density of the lower layer = 50%; 16523 ~ Area of raised oxide layer, density >50%; 1 6 524 ~ Lower oxidation Layer Density <50%; 16 0 9 5 ~ Metal Wire 1; 16 0 96 ~ Metal Wire 2; 1 6 11 2, 1 6 1 1 6 ~ Wafer; 1 6 11 3 ~ Cube Cube; 16962, 16964 ~ Oxidite; 16966 ~ Dish sinking.

1057-5667-PF (Nl) .ptd Page 261

Claims (1)

200405184 VI. Scope of Patent Application1. A method including: generating a dummy filling configuration strategy in the chemical mechanical polishing process based on an electrical impact analysis of a chemical mechanical polishing process and a pattern attachment model; and using the pattern Ancillary models and the electrical impact analysis to evaluate the expected results of placing the dummy fill; the use of the model and the electrical impact analysis is included in the strategy for generating dummy fill configurations. 2 · A method 'includes: a strategy for generating a dummy filling configuration in the chemical mechanical polishing process according to an electrical impact analysis of a chemical mechanical polishing process and a pattern auxiliary model; and using the pattern auxiliary model and the electrical process Sexual impact analysis to evaluate the expected results of placing the dummy filling; the manufacturing process to which the generated strategy applies includes manufacturing processes other than the chemical mechanical polishing process. 3. A method 'includes a strategy of generating a dummy filling configuration in the chemical mechanical polishing process according to a pattern auxiliary model of a chemical mechanical polishing process; and using the pattern auxiliary mold to evaluate the placement of the dummy filling Expected results of investment; The manufacturing process to which the generated strategy applies includes one or more manufacturing stages. 4 · One method, burden: I 1057-5667-PF (Nl) .ptd Page 262 200405184 VI. Patent application scope According to a pattern attached model of a chemical mechanical polishing process' create a dummy filling configuration in the chemical mechanical polishing process; and use the strategy The auxiliary model of the pattern is used to evaluate the expected result of placing the dummy filling. The manufacturing process to which the generated strategy is applicable includes a grinding or planarization process in which more than one material can be removed. 5 · The method as described in item 1, 2, or 3 of the scope of patent application, further comprising: operating a server, providing a function for generating a dummy entry for a semiconductor design, and a user viewing through a network The server develops the strategy of the dummy filling configuration on the client (c 1 i en t). 6. The method according to item 5 of the scope of patent application, wherein the server is located near the user. 7 The method according to item 6 of the scope of patent application, wherein the user can remotely control the server. 8 · The method described in item 1, 2 or 3 of the scope of patent application 'which further includes: analyzing a design to which the dummy filling strategy has been applied' adjusting the design based on the analysis, repeating the analysis and the adjustment steps; and It is confirmed that the manufactured / integrated circuit according to the adjusted design meets the physical electrical parameters of the plurality of devices. 1057-5667-PF (Nl) .ptd Page 263 200405184 6. Scope of Patent Application-1 Including two or more sets of processes. I 0 · The method as described in item 3 of the patent application scope, wherein the two stages include two or more sets of steps in a single process. II. The method according to item 3 of the scope of the patent application, wherein the two stages include deposition and chemical meteorological deposition. 1 2 · The method as described in item g of the scope of patent application ', wherein the generation of the strategy includes the rule of generating a complex array of dummy entries. 1 3 · The method described in item 1, 2, 3, or 4 of the scope of patent application, further comprising: defining a group of plural gradation units for dummy filling (hierarchical ceU placements); The configuration adds a dummy fill to reduce the size of an electronic layout file. 1 4 · The method described in item 1, 2, 3, or 4 of the scope of patent application ', wherein a user executes the service via a network, Liu Lan, and a network temple. Haixu assumes filling in and generating operations. -I, Gan Φ The temple suit 1 5. According to the method described in item 14 of the scope of patent application, the middleware is located near the user. 16 should be used. The method described in item 14 of the scope of patent application, "&quot; can remotely control the server. Method, which 1 7 · If the scope of patent application is 1, 2, 3 or 4 In the method, the process includes a trench process (damascene process) method. 〇57-5667-PF (Nl) .ptd 18 · As described in the patent application scope No. 1, 2, 3 or 4 in the position and configuration of the configuration of the dummy filling strategy includes determining the dummy filling ’ Page 264 200405184 VI. The method of patent application scope description, 1 9. As described in the patent application scope No. 丨, 2, 3 or 4, the manufacturing process includes forming a dielectric chamber with a low dielectric value. (Layer rinterlayer) 〇20 · The method described in item 3 of the scope of patent application, wherein the manufacturing process includes chemical vapor deposition or spin-on dielectric materials with a low dielectric value. 21 · The method as described in claims 1, 2, 3, or 4 of the scope of patent application, wherein the generation of the dummy filling strategy includes dividing a semiconductor design into a plurality of grids. Among them, the dummy 22 · The generation of the method filling strategy as described in item 21 of the patent application scope includes the density of each domain pattern of a semiconductor design. · The method hole as described in the item 21 scope of patent application The generation of the fill-in strategy includes capturing the line width of the area in each grid of a semiconductor design. The method as described in item 2 of the Shenjing patent scope, wherein the generation of the dummy filling strategy includes extracting the area line spacing in each of the cells of a semiconductor design. 25. The method as described in item 21 of the scope of patent application, wherein the generation of the dummy filling strategy includes calculating an effective pattern density for each cell. 2 6 · The method described in item 22 of the scope of patent application, which also includes the use of a complex model to generate a dummy filling strategy for a semiconductor design, and calculate the non-uniformity of the film thickness. 1057-5667-PF (Nl) .ptd Page 265 200405184 6. Scope of Patent Application 27 • If the method described in item 26 of the patent application scope is included, it also includes calculating the variation in film thickness. 28. The method described in item 2 of the scope of patent application, which also includes obtaining the ladders of all the objects in each of the cells. 2 9 · The method described in item 28 of the scope of patent application, which also includes generating at least one set of line width, line spacing, length, and bounding box for each of these objects. 3 0 · If the method described in item 21 of the scope of patent application ’is used,‘ where 5 Hai ’s dummy fill strategy includes multiple empty areas in each of these grids. 31. The method as described in item 28 of the scope of patent application, wherein the dummy fills in plural slots included in a plurality of objects ° 32. The method as described in item 30 of the scope of patent application, including Recalculate an area density after filling in the dummy. 33. The method described in item 30 of the scope of the patent application, which also includes &gt; including recalculation of the effective pattern male and female in each grid after adding dummy filling. 34. The method of speedboat as described in the scope of application for patent No. 1, 2, 3 or 4 'wherein the dummy filling strategy is based on the following rules: "tolerance · capacitance And the value of the voltage / ^ # μ #Current loss, dielectric constant output delay, skew, voltage drop, driving strategy, or crosstalk noise The method described in item 3 3 ^ 'Production. The effective pattern density is calculated by the flattening length of a grinding process. 1057-5667-PF (Nl) .ptd Page 266 200405184 VI. Patent Application Range 3 6 · The method as described in Item 33 of the Patent Application Range, which is based on elliptically weighted window or other filtering The calculator calculates the effective pattern density. 37. The method as described in item 12 of the scope of patent application, wherein the plural dummy filling rules according to the electronic design policy are dynamically generated with technical or plural design parameters. 38. The method as described in item 35 of the scope of patent application, wherein an effective pattern male degree and degree dynamically change with the flattening length of a process. 39. The method according to item 1, 2, 3, or 4 of the scope of patent application, wherein the manufacturing process includes a lithography process. 40. The method as set forth in claim 1, 2, 3, or 4, wherein the manufacturing process includes electrochemical deposition. 41. The method as set forth in claim 1, 2, 3, or 4, wherein the manufacturing process includes copper chemical mechanical honing. 4 2 · The method described in the scope of patent application No. 丨, 2, 3 or 4, which also includes extracting a plurality of pattern attachments from a semiconductor layout. 4 3 · The method as described in item 42 of the patent application park, wherein the layout attachments include corresponding line spacing, line width ^, and line density. 44 · The method described in item i, 2, 3 or 4 of the scope of patent application, which also includes: using a patterned clam test wafer or testing multiple semiconductor devices, corresponding to a pre-selected tool or process recipe for calibration A pattern auxiliary model; and a configuration in a process of generating a pattern auxiliary model according to a semiconductor process 1057-5667-PF (Nl) .ptd Page 267 200405184 VI. Scope of Patent Application This strategy is filled in by default. # 4 5 · As described in the scope of the patent application for item 1, 2, 3, or 4, it also includes: P Use a calibrated attached model of the pattern to compare the pattern attached, 彳, thin (features ) And multiple wafer stage parameters, such as final film thickness, film thickness variation, dishing, erosion, and multiple electrical parameters, such as resistance, resistance, capacitance, crosstalk noise, voltage drop, drive power / ;, L, power dissipation, dielectric constant, and effective dielectric constant; and * Si strategy to configure the settings in the manufacturing process based on the auxiliary model of the pattern, fill in the details 0 4 6 · If the scope of patent applications 1, 2, 3 or The method described in item 4 also includes: the strategy filled in by the configuration settings in the production process according to the pattern attachment model; and the use of a cost function to evaluate the manufacturing and electrical parameters at the wafer stage The effect of mutation and implementation of dummy filling adjustment. 4 7 · The method described in item 1, 2, 3, or 4 of the scope of the patent application, which also includes: generating a strategy based on the combination of multiple sets of pattern sub-models generated in the manufacturing process to configure dummy filling; and predicting The effect of this dummy filling by strategy on cake making variation. 4 8 · The method described in the scope of patent application No. 1, 2, 3, or 4 ’, which also includes generating in a process according to the combination of multiple sets of pattern auxiliary models 1057-5667-PF (Nl) .ptd Page 268 200405184 VI. Scope of patent application: One of the strategies of filling both segments and electrical parameters to optimize the crystal number of the overall wafer. The method described above, 49. If the scope of patent application is 1, 2, 3 or \ ^^ household and electrical parameters, the production also includes based on the predicted or simulated wafer level ^ dummy process in the second process A plurality of dummy filling rules are used for the configuration of a competing conductor system. , 7+, where the dummy 5 0 · As stated in item 49 of the scope of the patent application / e-filling rules include dummy filling dimensions. The real products 5 1 · The method as described in item 49 of the scope of patent application. The filling rules include the configuration of dummy filling. , Of which the false 52 · The method / reason described in item 49 of the scope of patent application. / Filling rules include the formation of dummy filling grade units and methods. 53. The method described in item 丨, 2, 3, or 4 of the scope of patent application, which also includes: ^ Provide multiple dummy filling functions to generate the A dummy fill strategy and the use of these functions to automatically adjust a plurality of GDS electronic layout files of a semiconductor device. 54. The method described in claim 1, 2, 3, or 4 of the method, which also includes: receiving a layout file transmitted from a client to a semiconductor device on a network server; The device generates a plurality of dummy fill-in adjustments for the layout file; and returns the adjusted dummy fill-in layout files to the client. 1057-5667-PF (Nl) .ptd Buy 269,200,405,184 6. Apply for a patent scope 5 5 · The method described in item 1, 2, 3 or 4 of the patent scope, which also includes: Provided on the server A service that enables a user to perform a vertical configuration with a dummy fill application executing on the server; and the user can use the dummy fill application to generate dummy fill information. 5 6. The method described in item 1, 2, 3, or 4 of the scope of patent application, which also includes: A user can confirm on a network the dummy filling information corresponding to a semiconductor design and a manufacturing process. 5 7 · The method described in item 56 of the scope of patent application ', wherein the confirmed dummy filling information includes at least a dummy filling pattern, a dummy filling strategy, or a dummy filling performance ^ ° 5 8 · The method described in item 56 of the scope of patent application 'wherein the confirmed dummy filling information is a separate interconnect layer corresponding to one of the semiconductor designs. 5 9 · The method described in item 56 of the scope of patent application ', wherein the confirmed dummy filling information is a plurality of separate interconnecting layers corresponding to the semiconductor design. 60 · As described in Item 56 of the scope of the patent application, the method 'also includes comparing the dimensions of a plurality of dummy filling in the subject, which is based on the single or plural interconnecting layers of the semiconductor design. Set the fill pattern. 6 1 · The method described in item 56 of the scope of patent application ', wherein the dummy filling information includes plural dummy filling rules. , 6 2 · The method as described in item 60 of the scope of patent application, wherein the pattern —I —1 1057-5667-PF (Nl) .ptd Page 270 200405184 6. Scope of patent application Including multiple oxidation or metal dummy filling in the subject. , F φ # + 63 · The method described in item 60 of the scope of the patent application, ‘Copper Film’, is used to fill in the pattern of the target system to minimize the variation of the full chip4 and drought. ▲ 64. The method as described in item 60 of the scope of the patent application, wherein the target system configuration is filled with dummy patterns to minimize the whole chip; 7 the variation of electrical parameters. 6 5 · The method as described in item 64 of the scope of patent application, in which the fourth-level electrical parameters include at least the film resistance value, electrical densities, capacitance values, crosstalk noise, voltage drop, driving current loss, dielectric Constant and valid; 丨 one of the number of electric cranes. η η I rfa ^ Xigu Jie, in which the GDS slot 6 6 · The formula as described in item 53 of the patent application scope is adjusted to improve the flatness and electrical performance of the semiconductor device. 67. The method according to item 66 of the scope of patent application, wherein the loading process includes a trench manufacturing process. 68 · The method described in the scope of patent application No. 1, 2, 3, or 4 ', which also includes: A user can use a network f application containing a plurality of network services on a network to confirm that a semiconductor design and / Fill in information for the manufacturing process. 6 9. The method according to item 1, 2, 3, or 4 of the scope of the patent application, wherein the dummy filling configuration strategy includes using a plurality of dummy filling targets to improve the structural integrity of the dielectric structure with a low dielectric constant ( structure integrity). 1057-5667-PF (Nl) .ptd Page 271 200405184 VI. Application for Patent Scope 70. For the patent application scope No. 1, the dummy fill configuration strategy includes the use of complex ^ ^ settings to improve the dielectric with low dielectric constant. The dielectric constant of the electrical structure. 71. The method as described in the patent application scope No. 60 or 70. The effective dielectric constant is maintained in all steps of a trench manufacturing process, which is 如 72. As described in the patent application scope 1, 2, 3 or; the method described in the above paragraphs. The dummy fill configuration strategy is included in a trench manufacturing process. Stream in the make. The method of filling in the target to promote the product of a plurality of low-dielectric-constant dielectric materials is set, which is maintained by one of the four items mentioned above, or the method of which is 7 3. As in the scope of patent application No. 1, 2, 3 or 4 The household description also includes: &gt;; maintaining a database of semiconductor dummy filling information (; linking the database and used to generate multiple dummy filling ages and changing dummy filling information to update the database, 3 Or the method described in item 4 above 7 4 · If included in the scope of patent application No. 1, it also includes: β stores calibration information according to at least one of the following: a complex number table formula, and a complex process; and the equal age square updates the calibration The information reflects these process tools and the changes in these processes. Tool re-or, &gt; Zhong Ye Bao La 7 5 · The method described in the scope of patent application No. 74 uses the calibration information to generate a dummy fill Strategy., 6, 6, 7 · As mentioned in item 74 of the scope of the patent application, & square / set / select multiple to fill in the calibration data of the characteristic according to the desired complex number, which is also included. 1057-5667-PF (Nl) .ptd No. 272 Tribute 200405184 VI. Scope of patent application Process tools, multiple recipes, and multiple processes. 77. The method described in item 1, 2, 3, or 4 of the scope of patent application, which also includes: A user can use a user interface of a user interface device to use a single click (sing 1 ec 1 ick ) Operation to obtain a dummy fill strategy required for a semiconductor design. 78. The method described in item 1, 2, 3, or 4 of the scope of patent application, which also includes: A user can use a plurality of network services on the network to obtain one of the dummy filling strategies required by the semiconductor design. 7 9. A method comprising the following steps: A strategy for generating a dummy fill is used to compensate for the attachment of plural patterns in an electrochemical deposition or electrochemical mechanical deposition manufacturing process. 8 0. A method including the following steps: generating a strategy of disposing dummy filling based on an electrical impact analysis of an electrochemical deposition or electrochemical mechanical deposition manufacturing process and a pattern auxiliary model; using the pattern auxiliary model and the The electrical impact analysis evaluates the expected results of the configured dummy filling; and the use of the pattern auxiliary model and the electrical impact analysis as part of the strategy for generating the dummy filling configuration. 8 1. A method including the following steps: According to the electrical impact analysis of an electrochemical deposition or electrochemical mechanical deposition manufacturing process and a pattern attachment model, a strategy of generating a dummy filling is provided. 1057-5667-PF (Nl) .ptd Page 273 200405184 6. The scope of the patent application is omitted; and the attached model of the pattern and the electrical impact analysis are used to evaluate the expected results of the configured dummy filling. 8 2. A method, comprising the following steps: generating a strategy of configuring dummy filling based on an electrical impact analysis of an electrochemical deposition or electrochemical mechanical deposition manufacturing process and a pattern auxiliary model; and using the pattern auxiliary model and This electrical impact analysis evaluates the expected results filled in by the configured dummy. 8 3. The method described in item 7, 9, 80, 81, or 82 in the scope of patent application, which further includes: operating a server to provide a semiconductor design with a function of generating a dummy entry; and a user The strategy of the virtual filling configuration can be developed on a client (c 1 ient) via a web browser. 84. The method as described in claim 83, wherein the server is located near the user. 85. The method according to item 84 of the scope of patent application, wherein the user can remotely control the server. 86. The method according to item 7, 9, 80, 81, or 82 in the scope of patent application, further comprising: analyzing a design to which the dummy filling strategy has been applied; adjusting the design according to the analysis; repeating the Analysis and adjustment steps; and 1057-5667-PF (Nl) .ptd Page 274 200405184 6. Scope of patent application Confirm the pre-existing physical and electrical parameters manufactured according to the adjusted design. 8 7. The method paragraph described in item 82 of the scope of patent application includes two or more sets of processes. 8 8 The method paragraph described in item 82 of the scope of patent application includes two or more sets of dream steps in a single process. 89. The method section as described in item 82 of the scope of patent application includes deposition and chemical vapor deposition. 90. The generation of the method as described in item 82 of the scope of the patent application includes the rule of generating a dummy array of complex arrays. 91 · As in the scope of the patent application No. 7, 9, 80, 81 or 82, it also includes: defining a group of plural hierarchical cell placements for dummy filling, and using these classifications The unit configuration is added with dummy filling to reduce the size of the bureau file. 92. According to the law described in item 79, 80, 81, or 82 of the scope of patent application, a user performs the dummy filling operation through an internet browser and an internet temple. 9 3 · The device described in item 92 of the scope of patent application is located near the user. 94 · The method described in item 92 of the scope of patent application can remotely control the server integrated circuit to comply with a plurality of the two steps, the two steps, # of the two steps, and the strategy described by $ Φ electronic layout Among which, this service is 9 5 · As described in the scope of application for patent No. γ 9, 80, 81 or 82 1057-5667-PF (Nl) .ptd Page 275 200405184 6. Scope of patent application The method described in item 81, 82, or 82. The method of determining the size of the dummy filling, wherein the manufacturing n-on Method, wherein the process includes an electrochemical machine 9 6 · Such as the patent application scope Nos. 7 9 and 80 method, in which the configuration is filled in with a strategy package and configuration. 97. The method as described in Chinese Patent Application No. 79, 80, 81, or 82, wherein the manufacturing process includes forming a dielectric interlayer with a low dielectric value. 98. The process as described in the scope of patent application No. 82 includes chemical vapor deposition or spin coating (sP i dielectric material. 99. The method as described in the scope of patent application 79, 80, 81 or 82, wherein The generation of the dummy filling strategy involves dividing a semiconductor design into a plurality of grids. 1 0 0 · The method as described in item 99 of the patent application scope, wherein the generation of the dummy filling strategy includes extracting a Density of the area pattern in each grid of a semiconductor design. 1 0 1. The method as described in item 99 of the scope of the patent application, wherein the generation of the dummy filling strategy includes extracting a region line width in each of the cells of a semiconductor design. 1 0 2 · The method as described in item 99 of the scope of the patent application, wherein the generation of the dummy filling strategy includes retrieving the area line spacing in each of the cells of a semiconductor design. 1 0 3 · The method as described in item 99 of the scope of patent application, wherein the generation of the dummy filling strategy includes calculating an effective pattern density for each cell. 1057-5667-PF (Nl) .ptd p. 276 200405184 104. The method as described in item 100 of the scope of patent application, which also includes the use of a multiple model needle library product &amp; Kao Bao1 to generate a dummy a and fill in one of the semiconductor design strategies. Flatness (non ~ uniformity). ^ 5 The method as described in item 104 of the scope of patent application, which also includes variations in the thickness of the true film. 1 ^ 0 6 · The method as described in item 99 of the scope of patent application, which also includes taking the coordinates of all the objects in the grid of the mother-of-one. 10 7. The method according to item 106 of the scope of patent application, further comprising generating at least one set of line width, line spacing, length, and bounding box for each of these objects. 108. The method as described in item 99 of the scope of patent application, wherein the dummy filling strategy includes adding dummy filling to a plurality of empty areas in each of the grids. I 0 9 · The method as described in item 108 of the scope of patent application, wherein the dummy is filled in a plurality of grooves (s 1 0 t s) included in a plurality of objects. II 0. The method as described in item 108 of the scope of patent application, which includes recalculating a region density after adding dummy filling. 11 1 · The method as described in item No. 108 of the scope of patent application, which also includes recalculating a valid pattern density in each of the cells after adding dummy filling. 112. The method according to item 79, 80, 81, or 82 of the scope of the patent application, wherein the dummy filling strategy is based on at least 'type electrical parameter variation tolerance in the following rules: capacitance value and resistance Value, sheet resistance, output delay, skew, voltage drop, drive current loss, 1057-5667-PF (Nl) .ptd Page 277 200405184 6. Scope of patent application Dielectric constant or crosstalk noise (crosstalk noise) 11 3 The method as described in item 1 of the patent application scope, wherein the effective pattern density is calculated according to a flattening length of a grinding process. / 11 4 · The method according to item 1 of the scope of patent application, wherein the effective pattern density is calculated according to an elliptically weighted window or other wavelet. % 5 · The method as described in item 90 of the scope of patent application, wherein the plural dummy filling rules according to the electronic: accounting policy are dynamically generated with technical or plural design parameters. ^ 11 6. The method as described in item 11 of the scope of patent application, wherein one of the &gt; pattern progress dynamically changes with the flattening length of a process. 11) The method according to item 79, 80, 81, or 82 of the scope of patent application, wherein the manufacturing process includes a lithography process. 18. The method described in item 79, 80, 81, or 82 of the scope of the patent application. The manufacturing process includes electrochemical deposition. 119. The method according to item 79, 80, 81, or 82 of the scope of patent application, wherein the manufacturing process includes copper chemical mechanical grinding. ", 120" The method described in item 79, 80, 81, or 82 of the scope of patent application "$ also includes extracting a plurality of pattern attachments from a semiconductor layout. ^ The method as described in item 120 of the scope of the patent application, wherein the attached &lt; includes a corresponding line spacing, line width, or line density. &quot;, 122 · The method as described in item 79, 80, 81, or 82 of the scope of patent application, which also includes: using a patterned test wafer or testing a plurality of semiconductor devices Page 278 200405184 VI. The scope of application for patents corresponds to a preliminary and one half filled in according to the 1 2 3 · If applied, it also includes the selection of tools or process recipes to calibrate a pattern attached to the congratulations; ) Film thickness variation, resistance value, resistance value loss, and dielectric constant are abbreviated according to the figure. 0 1 2 4 · As applied to the method, which also includes a strategy based on a combination of filling and prediction according to the 12 5. As applied to the method, where also Configure dummy charging parameters in the package. 1 2 6 · If applied, it also includes the strategy of conductor process. The patent scope includes: calibration pattern and multiple wafer dishing, erosion, capacitance value, and effective case attached model-pattern attached model production system attached to the party described in item 79, 80, 81, or 82 The model compares the auxiliary characteristics of the pattern with the phase parameters, such as the final film friction, thinness, and complex electrical parameters, such as thin-plate electrical crosstalk noise, voltage drop, and dielectric constant of the drive current loss; The scope of patents included in May includes: multiple sets of patterns attached to the pattern are generated in a process to configure the party described in item 79, 80, 81, or 82; and the scope of patents generated by the strategy include A strategy invites the scope of the patent to include the production of the auxiliary model of the multi-pattern design &amp; Wafer stage &amp; / # of the integrated wafer and electrical test or simulated wafer stage 〃 Item 79, 80, 81 or 82 1057-5667-PF (Nl) .ptd Page 279 200405184 VI. The number of patent applications applied, generating a plurality of dummy filling assignments 12 7. Filling in the rules for filling out the rules 12 8. Filling in the rules for filling out the rules 1 2 9 · If the application is false, fill in the rule 130. If the application is legal, it also includes the use of multiple sub layout files. 1 3 1 · Fill in the rules as they are applied and use them in the integrated manufacturing process. Please refer to the method described in item 126 of the patent scope, where these include the dimensions of the dummy filling. Please refer to the method described in item 126 of the patent scope, where these include the configuration of dummy filling. Please refer to the method described in the scope of patent No. 126, which includes the formation and management of dummy filling in the classification unit. Please include all the items described in the scope of the patent 79, 80, 81 or 82: the dummy fill function to generate the dummy fill strategy, the function automatically adjusts the complex GDS of a semiconductor device: , 80, 81, or 82, which also includes: Received from a client / server / semiconductor / case on the server; • Generate a plurality of dummy for the layout broadcast case and fill in the adjustment in A network layout file is transferred to the server and the adjusted 1 2 2 · If applied, it also includes the layout file filled in the server settings and returns it to the client. Please refer to the items described in item 79, 80, 81, or 82 of the patent scope: On the device, k provides a service, so that a user can interact with the setting device that is filled in by the virtual filling application. Page 280 200405184 6. Patent application scope (configure): And the user can use the dummy filling application to generate dummy filling information. 13 3. The method of claim 132, wherein the server includes a network server. 13 4. The method according to item 132 of the scope of patent application, wherein the user is located at a position remotely controlling the network server. 135. The method described in item 79, 80, 81, or 82 of the scope of patent application, which also includes: A user can confirm on a network the dummy filling information corresponding to a semiconductor design and a manufacturing process. 1 36. The method as described in item 1 35 of the scope of patent application, wherein the confirmed dummy filling information includes at least a dummy filling pattern, a dummy filling strategy, or a dummy filling performance. One. 13 7. The method as described in item 135 of the scope of patent application, wherein the confirmed dummy filling information is a separate interconnect layer corresponding to one of the semiconductor designs. 13 8. The method according to item 135 of the scope of patent application, wherein the confirmed dummy filling information is a plurality of separate internal interconnections corresponding to the semiconductor design Floor. 1 3 9. The method as described in item No. 135 of the scope of patent application, which also includes comparing the dimensions of a plurality of dummy filling in the target, and generating one of the targets for a single or multiple interconnecting layer of the semiconductor design. Dummy fill pattern. 1 40. The method as described in item 135 of the scope of patent application, wherein the dummy filling information includes a plurality of dummy filling rules. 1057-5667-PF (Nl) .ptd Page 281 200405184 VI. Scope of patent application 141. If the application includes a plural number 142. If there is a variation in the filling pattern. 14 3. If the variation of the filled-in pattern parameters is set 144. Such as the electrical parameter to the signal, the voltage drop, or one of them. The method described in the application of Patent No. 140, Housou, +,, and Miscellaneous, wherein the drawing is emulsified or the metal is falsely filled into the beam of the beam. The target system is configured to minimize the thickness of the full-chip thin film. The method described in item 140 of the patent application range, wherein the target systems are configured to minimize the full-chip thickness in the complex electronics. The method described above, wherein these include a thin film resistance value, a resistance value, a capacitance value, a crosstalk driving current loss, a dielectric constant, and an effective dielectric constant. 145. The method described in item 130 of the scope of patent application, wherein The gds broadcast is rectified to improve the flatness and electrical performance of the semiconductor device. 1 4 6 · The method according to item 79, 80, 81, 82, or 145 of the scope of patent application ', wherein the process includes a trench process. 1 4 9 · As described in item 7, 9, 80, 81 or 82 Page 282 1 4 7 · The method described in item 79, 80, 81, or 82 of the scope of patent application, which also includes: 2 A user can use one of the network applications with multiple network services on the network 3 applications 'Confirm correspondence—Semiconductor design and a dummy input information of a manufacturing process 0 4, 1 4 8 · The method described in item No. 147 of the scope of patent application, wherein the path is an internal network, an external network, Or an internet. Fang 200405184 VI. Application Patent Scope # λ π λα method, in which the dummy filling configuration strategy package includes multiple dummy filling in private to improve the structural integrity of the dielectric structure with low dielectric constant (s trUC1: 11 re integrity). 1 5 0 · The method as described in item 7, 9, 80, 81, or 82 in the scope of patent application, wherein the dummy filling configuration strategy includes using a plurality of dummy = filling in the target to maintain or improve the low dielectric constant. Constant dielectric constant of the dielectric structure. 1 5 1 The method as described in item 150 of the scope of patent application, wherein the effective dielectric constant is maintained in all steps of a trench process flow. 1 5 2 · The method described in claim 7, 7, 80, 81 or 82, wherein the dummy filling configuration strategy includes using a plurality of dummy filling targets in a trench manufacturing process to facilitate plural numbers Integration of low-k dielectric materials. , And 153. If the scope of patent application No. 79, 80, 81, or 82 also includes: a database to maintain a semiconductor dummy fill-in information (Ubrar links to the database and is used to generate a plurality of dummy fill-in configuration specifications; to change Fill in the information to update the database by dummy. 154. According to the 79th, 80th, 81st, or 82nd patent law of the scope of patent application, which also includes: The calibration information is stored according to at least one of the following: multiple process engineering and counting formulas, Plural processes; and / ,, plural Update the calibration information to reflect changes in the process tools and processes. Those formulas, or 1057-5667-PF (Nl) .ptd Page 283 200405184 VI. Scope of Patent Application 15 5. The method described in the scope of Patent Application No. 丨 54, which also includes using the calibration information to generate a dummy filling strategy. 1 5 6. The method as described in item 54 of the scope of patent application, which also includes selecting a plurality of process tools, a plurality of recipes, and a plurality of processes from a calibration database of the plurality of dummy filling characteristics. 15 7 · The method described in the scope of application for patent 79, 80, 81 or 82, which also includes: The user can use one of the user interface of a user interface device, click (sinSle ci 丨) Operation obtains a dummy fill strategy required for a semiconductor design. 1 5 8 · A method, which includes the following steps: • A strategy of generating a dummy filling configuration in the system, and a model of the genus and the electrical impact analysis to evaluate the expectations of filling in the dummy a As a result, the model and the electrical properties are incorporated into the strategy configured. … The use of analysis is included in the generation of dummy fills. 159. A method includes the following steps: According to the model with one or more + _ &gt; @ ^ and-patterns, the electrical impact analysis of the second pass is omitted; and One of the strategic impact analysis of the dummy fill configuration in the red to evaluate the placement of the Expected results of using the pattern attached model and the dummy filling; Page 284 200405184 VI. Scope of patent application The manufacturing process to which the generated strategy applies includes manufacturing processes other than the chemical mechanical polishing process. 1 6 0 · A method to cover: According to a pattern auxiliary model of a manufacturing process flow including one or more steps, a strategy of generating a dummy filling configuration in the process is generated; and using the pattern auxiliary pattern to evaluate Insert the expected result of the dummy entry; the manufacturing process to which the generated strategy applies includes one or more manufacturing stages. 161 · A method comprising: generating a strategy of a dummy filling configuration in the process according to a pattern auxiliary model of a manufacturing process flow including one or more steps; and using the pattern auxiliary model to evaluate the placement of the dummy filling Expected results of the input; The manufacturing process to which the generated strategy applies includes a grinding or planarization process in which more than one material can be removed. 1 6 2. The method described in the scope of patent application No. 158, 159, 160 or 161, further including: Operate a server to provide a dummy fill function for a semiconductor design; and (client) where the user can develop a strategy for the dummy fill configuration on a client via a web browser. 16 3. According to the method described in # 162, # 162 of the patent application scope, the server is located near the user. 〇57-5667-PF (Nl) .ptd 285 stomach 200405184 6. Scope of patent application 164 • The method described in item 163 of the scope of patent application, in which the user can remotely control the server. In order to make 165, as described in the scope of application for patent No. 1 58, 丨 59, 160 or 161. The method further includes: analyzing a design that has been applied to the dummy filling strategy; Adjust the design according to the analysis; repeat the analysis and the adjustment steps; and confirm that one integrated circuit manufactured according to the adjusted design meets a plurality of preset physical and electrical parameters. 16 6. The method according to item 160 of the scope of patent application, wherein the two stages include two or more sets of processes. 16 7. The method as described in claim 16 of the patent application scope, wherein the two stages include two or more sets of steps in a single process. 168 · The method as described in the patent application No. 丨 60, wherein the two stages include deposition and chemical vapor deposition. 1 6 9 · The method as described in item No. 丨 60 of the scope of patent application, wherein the generation of the strategy includes the rule of generating a dummy array of complex arrays. 1 7 0 · The method described in the scope of application for patents No. 158, 159, 160, or 161, further including: defining a group of plural hierarchical unit configurations for dummy filling (hierarchical cel 1 Placements); and use these graded unit configurations to add dummy fills to reduce the size of an electronic bureau file. 1 7 1 · As described in the scope of patent application No. 1 5 8, 1 5 9, 1 6 0 or 16 1 1057-5667-PF (Nl) .ptd p.286 200405184 6. Patent application method, in which a user executes the dummy filling to generate a chapter through a web browser and a web server. 1 7 2. The method according to item 7J of the scope of patent application, wherein the server is located near the user. Λ 17 3. The method described in item ηΐ of the scope of patent application, wherein the user can remotely control the server. 17 4. The method of claim 158, 159, 160 or 161, wherein the process includes an electrochemical mechanical deposition process. 175. The method of applying for patent No. 158, 159, 160, or 161, wherein the strategy of configuring the dummy filling includes determining the dummy filling position and configuration. Rule 17 6. The method according to item 158, 159, 16 or 161 of the scope of the patent application, wherein the manufacturing process includes forming a dielectric layer with a low dielectric value, and wherein the device has a low dielectric. Value 177. The method described in item 160 of the scope of patent application includes a dielectric material of chemical vapor deposition or spin coating (spin_Qn). The term 159, 160, or 161 includes dividing a semiconductor design 1 7 8 · If the method of patent application scope No. 158, the output of the dummy filling strategy is cut into a plurality of cells (g r i d s). 17 = The method according to item 178 of the scope of patent application, wherein the generation of the fill-in scrolling includes the density of capturing a semiconductor virtual region pattern. 18 0 · The method described in the scope of patent application No. 178, wherein the virtual 1057-5667-PF (Nl) .ptd p. 287 200405184 Set the area line width of the fill strategy. 1 8 1 · If you set the line spacing of the filling strategy. 1 8 2 · If applying the filling strategy 1 8 3 · If claiming to calculate the film thickness using a complex modulus 184 · If claiming to calculate the film thickness to generate a patent including the extraction of a semiconductor design in each of the cases The method according to item 178, wherein the dummy generation includes extracting each of the cells in a semiconductor design. The method described in item No. 178 of the patent scope, wherein the dummy generation includes calculating a valid pattern for each cell. density. Please refer to the method described in the scope of patent No. 178, wherein the package also corresponds to a non-flatness (nON ~ Unifomrmity) of a semiconductor design that generates a dummy filling strategy. Please refer to the method described in item 183 of the patent scope, which also includes variation in degree. 185. The method described in item 178 of the scope of the patent application, which also includes obtaining the coordinates of all objects in each of the cells. 186. The method described in item 185 of the scope of patent application, which also includes generating at least one set of line width, line spacing, length, and bounding box for each of these objects. 187. The method as described in item 178 of the scope of patent application, wherein the dummy filling strategy includes adding dummy filling to a plurality of empty areas in each of the grids. 188. The method according to item 185 of the scope of patent application, wherein the dummy is filled in a plurality of grooves (s 1 0 t s) included in a plurality of objects. 18 9. The method according to item 187 of the scope of patent application, which includes recalculating a region density after adding a dummy fill. 1057-5667-PF (Nl) .ptd Page 288 200405184 VI. Application for Patent Scope 1 9 0 · The method described in Item 187 of the Patent Application Scope, which also includes recalculating each An effective pattern density in the grid is 0 1 9 1 · As described in the scope of patent application No. 丨 5 8, 丨 5 9,16 〇 or 丨 1 1 'where the dummy filling strategy is based on the following rules Tolerance of at least one type of electrical parameters: capacitance value and resistance value, film resistance value, wheel-out delay, skew, voltage drop, driving current loss 7 丨 electric hanging number, or crosstalk noise (Crosstalk noise). 19 2. The method according to item 19 of the scope of patent application, wherein the effective pattern density is calculated based on a planarization length of a grinding process. 19 3 // The method as described in item 19 of the scope of the patent application, wherein the effective pattern density is calculated according to an expansion circle &gt; / ellipticaHy weighted window or other wave pattern. ^ The method as described in item No. 168 of the scope of patent application, wherein the plural dummy filling rules according to the electronic design policy are dynamically generated with technical or plural design parameters. ^ 19 52. The method described in item 192 of the scope of patent application, wherein an effective pattern bifurcation dynamically changes with the flattening length of a process. , 1 9 6 · The method as described in the scope of application for patents No. 5-8, 5-9, 1660 or 61, wherein the manufacturing process includes a lithography process. 1 197. The method as described in the scope of the patent application No. 158, 159, 160 or 161, wherein the manufacturing process includes electrochemical deposition. 198 · The method as described in the scope of patent application No. 158, 159, 160 or 161, wherein the manufacturing process includes copper chemical mechanical grinding. 1057-5667-PF (Nl) .ptd Page 289 200405184 VI. Application scope of patents '' ^^ _____ 199 · If the scope of application for patent scope No. 158, 159, 160 or 161, ten, methods, including self- Extract the genus of the plural figure in the semiconductor layout. M is attached with the method according to item 199 of the patent application park, wherein the 附属 layout attachment includes corresponding line spacing, line width, or line density. ^ Special 201. If the method of applying for patent No. 158, 159, 160 or 161, also includes: π 24 method using patterned test wafers or testing multiple semiconductor devices, corresponding to a pre-selected tool or process recipe To calibrate a pattern auxiliary mold and, according to one of the semiconductor process, the pattern auxiliary pattern generation process reads the dummy fill in the strategy. 20 2 · The method as described in the scope of patent application No. 158, 159, 160 or 161, which also includes: using a calibrated pattern accessory model to compare pattern features with multiple wafer stage parameters, such as Final film thickness, film thickness variation, dishing, encroachment, and complex electrical parameters such as film resistance, resistance, capacitance, crosstalk noise, voltage drop, drive current loss, dielectric constant, and effective dielectric Constant; and the strategy of dummy filling in the production process according to the pattern auxiliary model generation 0 20 3. The method as described in item 158, 159, 160 or 161 of the patent application scope, which also includes: generating according to the pattern auxiliary model The strategy of configuring dummy filling in the manufacturing process 1057-5667-PF (Nl) .ptd Page 290 200405184 VI. The scope of patent application is omitted; and a cost function is used to evaluate the variation of the process and electrical parameters at the wafer stage and perform a dummy filling in the adjustment The impact. 204. The method according to item 158, 159, 160, or 161 of the scope of patent application, further comprising: generating a strategy of configuring a dummy filling in a process according to a combination of a plurality of pattern auxiliary models; and predicting the The effect of this dummy filling generated by the strategy on process variation. 20 5. The method described in item 158, 159, 160, or 161 of the scope of patent application, which also includes a strategy of generating dummy filling in a process based on combining multiple sets of pattern auxiliary models to optimize the overall Wafer stage and electrical parameters of the wafer. 206. The method described in item 158, 159, 160, or 161 of the scope of patent application, which also includes generating multiple dummy filling rules based on predicted or simulated wafer stages and electrical parameters, and used in a semiconductor manufacturing Configurations filled in during the manufacturing process. 20 7. The method described in item 20 of the scope of patent application, wherein the dummy filling rules include the size of the dummy filling. 20 8. The method according to item 206 of the scope of patent application, wherein the dummy filling rules include the configuration of dummy filling. 209. The method as described in item 206 of the scope of patent application, wherein the dummy filling rules include the formation and management of dummy filling grade units. 2 1 0 · As described in the scope of patent application No. 1 5.8, 159, 1 6 0 or 16 1 1057-5667-PF (Nl) .ptd p. 291 200405184 Method, which also includes: k for plural dummy fill functions Use these functions to automatically adjust the layout file. To generate the dummy filling strategy; to use the plural number of a whole semiconductor device 讣 3 ^ 21 1 · If the scope of the patent application] 5 8 method, which also includes: receiving a layout file from a network on a network server ; 159, 160, or 161 household descriptions ^ The client passed to a semiconductor semiconductor to generate a plurality of dummy files of the distribution and bureau files on the server. Fill in the adjustments to describe them. The layout file filled with the adjusted dummy is returned to the client. 21 2 · If the method of the patent application scope No. 158, 159, 160 or 161, also includes ... T mouth to provide services on the = server, so that a user can execute One of the dummy filling applications is configured interactively (conf igure); and the user can use the dummy filling applications to generate dummy filling information. 21 3. The method as described in item 158, 159, 160 or 161 of the scope of patent application, which also includes ... A user can confirm the dummy filling information corresponding to a semiconductor design and a manufacturing process on a network. 214. The method described in the scope of patent application No. 213), wherein the confirmed dummy filling information includes at least one dummy filling pattern, a dummy filling strategy, or a dummy filling performance. 1057-5667-PF (Nl) .ptd Page 292 200405184 VI. Scope of Patent Application 2 1 5 · The method described in item 21 of the scope of patent application, in which the confirmed dummy information is a separate interconnect layer corresponding to one of the semiconductor designs. 2 1 6. The method as described in item 21 of the scope of patent application, wherein the confirmed dummy information is a plurality of separate interconnect layers corresponding to the semiconductor design. 217. The method as described in item 213 of the scope of patent application, which also includes comparing the dimensions of a plurality of dummy fill in targets and generating a dummy fill pattern of one of the targets for a single or multiple interconnect layer of the semiconductor design. . 218. The method according to item 214 of the scope of patent application, wherein the dummy entry &gt; message includes plural dummy entry rules. 2 1 9 · The method as described in item No. 21 of the scope of patent application, wherein the pattern includes multiple oxidation or metal dummy filling in the subject. 220. The method as described in item 217 of the scope of patent application, wherein the target systems of the dummy fill pattern are configured to minimize variation in thickness of the film. Wang Yueyue 221. The method as described in item 217 of the scope of patent application, wherein the target system configuration of the dummy filling pattern is to minimize the variation of the whole crystal in complex electrical parameters. aa, 22 2 · As described in the patent application No. 221, the electrical parameters include at least the thin film resistance value and resistance method, among which the voltage, voltage drop, driving current loss, dielectric constant, capacitance value, and string # slave among them One. And the effective dielectric constant 2 2 3 Escaped method, wherein the G D S 〇57-5667-PF (Nl) .ptd 200405184 VI. Scope of patent application The file system was adjusted to improve the flatness and electrical performance of the A &amp; A. 224. Taxi U Lee Wai Wai's 223th process includes the trench manufacturing process.决 „22 5. The method according to item 213 of the scope of patent application, wherein the network is-an internal network, an external network, or an Internet. , 160 or the method described in the item, further including: ^ providing a service on the server, so that a user can communicate with the server A dummy fill application running on the device is configured interactively (configure); and the user can use the dummy fill application to generate dummy fill information. 227. The method according to item 158, 159, 160, or 161 of the scope of patent application, wherein the dummy filling configuration strategy includes the use of a plurality of dummy fillings to improve the structural integrity of a low-dielectric constant dielectric structure ( structure integrity) 〇228 · As described in the scope of patent application No. 158, 159, 160 or 161 f -1: ¾ Method, wherein the dummy fill configuration strategy includes using a plurality of dummy fills to maintain or improve a dielectric constant of a dielectric structure having a low dielectric constant. 22 9. The method according to item 217 of the patent application scope, wherein the effective dielectric constant is maintained in all steps of the 〆 trench process flow. Party 2 3 0 · The ice method as described in the scope of application for patents 158, 159, 160, or 161, wherein the dummy filling configuration strategy includes a plurality of dummy dummy for private accumulation in a trench process flow Fill in the subject to promote the complex low-k dielectric material &amp; physical properties. 1057-5667-PF (Nl) .ptd Page 294 200405184 VI. Application for patents g '&quot;-Fang, &gt; 3 ^; The method described in the scope of the patent application 158, 159, 160 or 161' It also includes: a database of semiconductor dummy filling information (Hbrary) ;, &quot; The database is also used to generate a plurality of dummy filling configuration specifications; to change the dummy filling information to update the database. Fangban 3 ^ Store the calibration information according to the data described in item 158, 159, 160 or 161 of the scope of the patent application to one of the following: complex process tools, complex recipes, and complex processes; and The calibration information reflects changes in the process tools, the recipes, or the temple process. M3. The method described in item 229 of the scope of patent application, which also includes generating a dummy filling strategy using the calibration information. 23 4. The method as described in item 229 of the scope of patent application, which also includes ^ ^ ^ a plurality of dummy filling process, a calibration database of characteristics to be selected, a plurality of clothes process tools, a plurality of formulas, and a plurality of processes. 23 5. If the method of applying for patent No. 158, 159, 160, or ΐ6ΐ, also includes: ^ one, the user can use a user interface of a user interface device, 1: Early CliCk operation One of the dummy fill strategies required to obtain a semiconductor design. T M and method 23 6 benefits as described in item 158, 159, 160 or 161 200405184 6. Scope of Patent Application A user can use a plurality of network services on the network to obtain a dummy filling strategy required for a semiconductor design; and the manufacturing process to which the generated strategy is applicable includes one or more manufacturing stages . 2 3 7. A method including the following steps: When using electrochemical mechanical deposition or chemical vapor deposition of a low dielectric constant dielectric interlayer, or applying a low dielectric constant dielectric interlayer, a pattern attachment model and prediction. 2 3 8. A method including the following steps: a strategy for generating a dummy fill configuration in a semiconductor manufacturing process based on an electrical impact analysis of a chemical mechanical polishing process and a pattern attachment model; and using the pattern attachment model And the electrical impact analysis to evaluate the expected results of placing the dummy fill; the use of the model and the electrical impact analysis is included in the strategy for generating the dummy fill configuration. 2 3 9. A method including the following steps: a strategy for generating a dummy fill configuration in a semiconductor manufacturing process based on an electrical impact analysis of a chemical mechanical polishing process and a pattern attachment model; and using the pattern attachment model And the electrical impact analysis to evaluate the expected results of placing the dummy fill; the manufacturing process to which the generated strategy applies includes manufacturing processes other than the CMP process. 1057-5667-PF (Nl) .ptd Page 296 200405184 VI. Scope of Patent Application 1 1 2 4 0 · A method including the following steps: Molding according to a diagram of a chemical mechanical polishing process and manufacturing it in a semiconductor The second strategy of generating a dummy filling configuration in the manufacturing process; and using the pattern auxiliary model to evaluate the manufacturing system or multiple manufacturing stages to which the expected filling of the dummy filling is applied to the generated strategy. 241. The method as described in claim 24 in the scope of patent application, wherein each stage includes a process recipe. 24 2. The method according to item 24 of the scope of patent application, wherein each stage includes a process pattern. 24 3. The method according to item 24 of the scope of patent application, wherein each stage includes a process flow. 2 4 4. A method including the following steps: a strategy for generating a dummy fill configuration in a semiconductor manufacturing process according to a pattern attachment mold of a chemical mechanical polishing process; and using the pattern attachment model to evaluate placement The expected result of the false entry; The manufacturing process to which the resulting strategy applies includes a grinding or planarization process in which more than one material can be removed. 24 5. The method described in item 244 of the scope of patent application, which also includes multiple electrical analysis. 2 4 6 · A method including the following steps: Operating a server to provide multiple dummy fills as a semiconductor design l〇57-5667-PF (Nl) .ptd Page 297 200405184 VI. Patent application scope generation function; a user fills in the dummy 2 4 7 · If the application server is located in the messenger 2 4 8. If the applicant can remotely control 24 9. If the application is virtual Fill in the configuration of mechanical deposition, deposition, and chemistry 2 50 · If you apply to fill in the configuration 251. If you want to fill in the configuration 2 5 2 ·-a kind of use of a map and can be operated on a client through a web browser Using the method described in item 246, wherein the method described in item 226, wherein the method described in item 226, which is equal to at least one of the following processes : The method described in item 246 of electrochemical deposition, coating process, lithography, and electrochemical deposition, wherein this is equal to shallow trench isolation. The method according to item 246, wherein the oxidizing dielectric layer. The following steps: Analyze an integrated circuit design; fill in the strategy; enter the design of the strategy; adjust the strategy based on the analysis; repeat the analysis and adjust the plural steps; and% # confirm an integrated circuit manufactured based on the adjusted design The circuit sub-port pre-use configuration function should be near the user of the patent scope. The scope of patent is to make the server. The scope of patent is to use chemical vapor deposition and mechanical polishing. Please apply the scope of the patent. Use the scope of the patent. Use the method, including the model attached to the case. Apply a dummy to the design. Analyze the physical and electrical parameters of the dummy fill. &amp; &lt; ΦThe two 25 3. The method as described in the 240th scope of the patent application 'long τ 1057-5667-PF (Nl) .ptd Page 298 200405184 A phase consists of two or more sets of processes. Wherein the rain 2 54. The method as described in item 24 of the scope of application for patents // The stage includes two or more groups in a single process with less complexity. The rain 2 5 5. The method described in item 24 of the scope of patent application, the stage includes two or more sets of steps in a single process type. Among them, the rain 25 6. The method according to item 24 of the scope of application for patent &apos; phase includes two or more groups in a process flow. The rain 25 7 · The method as described in item 240 of the scope of the applied patent '/' stage includes deposition and chemical meteorological deposition. Li Zhongzhong's policy f 25 8 · The method described in item 24 of the scope of application for patent application '/, the generation of the strategy includes the rule of generating a complex array of dummy entries. 2 5 9. A method, including the following steps: defining a group of plural hierarchical cell placements for dummy filling; and using the dummy hierarchical configuration to add dummy filling to reduce the size of the electrical office file . ° '260. The method according to item 238, 239, 240, or 244 of the scope of patent application, wherein a user performs the dummy filling generation operation through a web browser and a web server. 261. The method according to item 260 of the scope of patent application, wherein the server is located near the user. 2 6 2 · The method as described in item 260 of the scope of patent application, wherein the user can remotely control the server. 26 3. The method according to item 260 of the scope of patent application, wherein the virtual 1057-5667-PF (Nl) .ptd Page 299 200405184 VI. Patent Application Scope The fields not filled in are the network services provided on a server. 2 6 4. The method described in the scope of application for a patent No. 238, 23 9, 240 or 244 ', wherein the process includes a pad chemical mechanical deposition process. 26 5. The method according to item 238, 23, 9, 240 or 244 of the scope of the patent application, wherein the strategy of configuring the dummy filling includes determining the size and configuration of the dummy filling. 266 · The method as described in the scope of patent application No. 238, 239, 240 or 244, wherein the manufacturing process includes forming a dielectric interlayer with a low dielectric value ° 2 6 7 · If the scope of patent application The method according to item 24, wherein the manufacturing process includes a chemical vapor deposition or spin coating (spin — 0Γ1) dielectric material having a low dielectric value. 26 8. The method according to item 238, 23 9, 240, or 244 of the scope of patent application, wherein the generation of the dummy filling strategy includes dividing a semiconductor design into a plurality of cells (g r d s). 269. The method as described in claim 238, 239, 240, or 244, wherein the generation of the dummy filling strategy includes retrieving the density of the area pattern in each grid of a semiconductor design. 2 7 0. The method as described in the scope of patent application No. 238, 23 9, 240, or 244, wherein the generation of the dummy filling strategy includes extracting a line width of a region in each grid of a semiconductor design. 271. The method according to item 238, 239, 240, or 244 of the scope of the patent application, wherein the generation of the dummy filling strategy includes extracting an area line spacing in each grid of a semiconductor design. 1057-5667-PF (Nl) .ptd Page 300 ι〇 ^ ι〇 ^ VI. Patent application scope 2 7 2. If the setting is filled in, the 27 will be omitted. 3. If applying, calculate the film thickness by using the complex modulus. 2 7 4 · If claiming, calculate the thickness of the film 27 5 · If claiming, obtain each of the 27 27. If claiming, corresponding to each of these and joining the block 27 7 · If claiming, fill in the strategy package) Add the dummy filling 278 · Such as Filling in the application is included in 27 9 · Rushen is joining the dummy filling 28 0 · If the claim is being joined in the dummy degree. 281. The method as claimed, in which the patented scope produces non-flat patented scopes including the corresponding degree of patented scope. Please create all the items in the patent range, etc. (bounding sunny patent range is included in each of the multiple objects in the patent range, please recalculate after the patent range is entered, please fill in the patent range, and then re-invent the patent range.) In the method described in item 2 71, the method described in Yongbu Bei, where one of the virtual grids has an effective pattern density. In the method described in item 2, 72, 斤, +, and angle, it also includes the method of filling in the strategy. A semiconductor design degree (n〇n ~ Uniformit). Item 273 ~, +, &gt;, the method described, which also includes the method described in 268%, +, and the method, which also includes objects The method described in item 275, which also includes at least one set of line width, line spacing, length, Box) The method described in item 276, wherein the virtual area has a plurality of empty areas (empty areas The method according to item 277, wherein the imaginary and complex slots are described. The method according to item 278, wherein a region density is calculated. The method according to item 279, which also includes calculating each A valid pattern in a grid 3 Slightly referred to in item 9, 240 or 244 200405184 VI. Patent application scope Parameter variation tolerance (tolerance): capacitance value and resistance value, film resistance value, output delay, skew, voltage drop, drive current loss, dielectric constant, or crosstalk noise (cr 〇Sstalkrl〇ise). 28 2. The method according to item 280 of the scope of patent application, wherein the effective pattern density is calculated based on a flattening length of a grinding process. 28 3. The method according to item 280 of the scope of patent application, wherein the effective pattern density is calculated based on an elliptically weighted window or other filter. 28 4. The method as described in the scope of patent application No. 238, 239, 24 or 244 'wherein the non-flatness of a film thickness is determined according to a plurality of physical parameters 0 285 The method of item 'wherein the physical parameters include density, line width, and / or line spacing. 28 6. The method described in item 238, 23, 9, 240 or 244 of the scope of patent application, which also includes using the dummy filling strategy to reduce the variation of electroplated copper deposition before or after CMP. 28 7. The method according to the scope of application for patents No. 238, 23 9, 240 or 244, wherein the dummy filling strategy is automatically completed. 28 8. The method according to item 258 of the scope of patent application, wherein the plural dummy filling rules according to the electronic design policy are dynamically generated with technical or plural design parameters. 28 9. The method according to item 258 of the scope of patent application, wherein an effective pattern density dynamically changes with the flattening length of a process. 1057-5667-PF (Nl) .ptd p. 302 200405184 290. The method as described in claim 238, 239, 240, or 244, wherein the manufacturing process includes a lithography process. 291. The method as described in claim 238, 23, 9, 240, or 244, wherein the manufacturing process includes electrochemical deposition. 292. The method as described in claim 238, 239, 240 or 244, wherein the manufacturing process includes copper chemical mechanical grinding. 29 3. The method as described in claim 238, 23, 9, 240 or 244, wherein the manufacturing process includes electrochemical mechanical deposition. 29 4. The method according to item 238, 23, 9, 240, or 244 of the patent application scope, wherein the manufacturing process includes a dielectric material with a low dielectric constant. 295. The method of claim 238, 239, 240, or 244, wherein the manufacturing process includes a dielectric material process with a low dielectric constant. 296. The method described in the scope of patent application No. 238, 239, 240 or 244, which also includes extracting a plurality of pattern attachments from a semiconductor layout. 297 · The method as described in item 296 of the patent application scope, wherein the layout attachments include corresponding line spacing, line width, or line density. 2 9 8 · A method comprising the following steps: a method of using a patterned test wafer or a plurality of semiconductor devices to test a pre-selected tool or process recipe to calibrate a pattern accessory model; and a pattern according to a semiconductor process The strategy is configured by filling in dummy models in the auxiliary model generation process. 2 9 9-A method including the following steps: 1057-5667-PF (Nl) .ptd Page 303 200405184 VI. The scope of patent application uses the following types: electrochemical shadow, shallow trench dielectric layer, according to this slightly 30 0.- using a (features film thickness variation resistance Values, electrical resistance, and dielectric constants are generally based on this strategy. 301.- Based on this strategy; and the use of a process and electrical sound. The at least one process produces deposition, electrochemical machine insulation, chemical mechanical research, and spin-coated low dielectric constant patterns. Additional model production methods, including the calibration pattern attached below) and multiple wafer levels, dishing, backlash, value, capacitance value, number of strings, and effective medium pattern auxiliary model production methods, including the following pattern auxiliary model production The cost function (cost) is based on the variation of the ten-parameter parameters = the deposition of a plurality of overall wafer patterns, the deposition of steel mechanical mechanical polishing, the micro-chemical chemical vapor deposition of a low dielectric constant number of dielectric layers; and the production process # Μ α罝 Fill in the steps of this strategy: Compare the pattern with many additional features, such as the final film thickness, thinness, and multiple electrical inflammations, ^ I no parameters, such as film noise, M drop, drive power Loss of electricity constants, and the steps of the strategy to configure the dummy filling in the production process: Function of the strategy + the configuration of the dummy filling in the strategy function) To evaluate the effect of the dummy filling adjustment during the wafer stage 3 〇 2 The method includes the following steps: generating a strategy of configuring dummy filling in a process according to a combination of a plurality of pattern auxiliary models; and predicting the effect of the dummy filling generated by the strategy on process variation. 200405184 VI. Scope of patent application 3 〇3 · A method, including the following steps: According to the combination of multiple sets of patterns attached model is generated in a process to configure dummy filling-to optimize the wafer stage and power of the overall wafer Sexual parameters. 3 0 4. A method including the following steps: generating a plurality of dummy filling rules based on predicted or simulated wafer stages and electrical parameters, and applying them to a dummy filling configuration in a semiconductor manufacturing process. ， 30 5. As mentioned in Item 30 of the scope of patent application, where these dummy filling rules include the size of dummy filling. 〆 30 6 · As described in item 304 of the scope of patent application, where the dummy filling rules include the configuration of dummy filling. Jie '307. As described in item 304 of the scope of patent application, where these dummy filling rules include the formation and management of dummy filling grading units. 3 0 8-A method including the following steps: ^ for a plurality of dummy filling functions to generate the setting filling strategy; and a sub-layout file. Multiple Needles for Naaman + Conductor Device 30 9. A method including the following steps · page 305 Received from one of the ## conductor device layout files on the two network servers; Guangyao Deyu generated the layout file t λ on the δH server, etc .; Work, the adjusted dummy-filled cloth 31. If the scope of the patent application is 309 °, the client service is returned to the client and the client uses the Internet method. 'Where the server 1057-5667-PF (Nl) .ptd 6. Scope of patent application 3 1 1 · If the server and the client 3 1 2 · If the towel server and the client 3 1 3 · If the server and the client network, VPN 3 1 4. If the server and the client secure communication protocol 3 1 5 · If the server and the client layer, SSL) 31 6. If the server and the client network, VPN 31 7 One of the server's implementation (configure) the user 3 1 8. If the applicant is located in phase 319, please apply for the patent scope, use the patent scope, use the patent scope, and use the virtual connection. The patent scope is based on security. The patent scope is based on security communications. The patent scope is based on virtual security communications methods, including providing a dummy fill-in response on the device. A remote location method of the server includes the following steps: The method described in item 309 is connected to the network. The method described in item 309 is connected to the network. The method described in item 309 is a virtual private network (the method described in item 309, wherein the secure shel 1, SSH) is the method described in item 309, wherein the The full packet layer (secure socket method described in item 309), in which the server proposes a virtual private protocol (virtual private protocol). The following steps: service, so that a user can interact with the server to configure settings The filling application generates a dummy filling information. The method described in item 3 1 7, wherein 1057-5667-PF (Nl) .ptd Page 306 200405184 6. Scope of Patent Application Semiconductor Design and One System A user can confirm the dummy input information of the oblique manufacturing process on a network. ~ Among which is a dummy filling 3 2 0 · As described in item 3 119 of the scope of patent application, the confirmed dummy filling information includes at least a dummy filling method entry strategy, or a dummy filling performance one or a pattern 3 2 1 · As described in item 3 119 of the scope of the patent application, it is assumed that the dummy filling information corresponds to the semiconductor method, and it is confirmed that the embryo is a separate interconnect layer. 322 .: Application: The method described in item 319 of the patent scope, in which the confirmed dummy is filled in the body information corresponding to the plurality of separate interconnect layers of the semiconductor design. 0 32 3 · As described in item 319 of the scope of patent application The method also includes comparing the dimensions of a plurality of dummy underfill targets and generating a dummy fill pattern of one of the targets for a single or complex interconnect layer of the semiconductor design. 3 2 4 · The method as described in item 319 of the scope of patent application, wherein the dummy filling includes a plurality of dummy filling rules. 3 2 5 · The method as described in item 3 119 of Shenyan's patent scope, wherein the pattern includes multiple oxidation or metal filling in the subject. 32 6. The method as described in item 319 of the scope of patent application, wherein the target configuration of the dummy fill pattern is configured to minimize variations in the thickness of the full wafer film. 32 7. The method as described in item 319 of the scope of patent application, wherein the target system configuration of the dummy fill pattern is to minimize the variation of the whole chip in complex electrical parameters. 1057-5667-PF (Nl) .ptd Page 307 200405184 6. Application for Patent Scope 32 8. The method described in Item 327 of the Patent Application Scope, where the electrical parameters include at least the film resistance value, resistance value, and capacitance Value, crosstalk noise, voltage drop, drive current loss, dielectric constant, and effective dielectric constant. 32 9. The method according to item 308 of the scope of patent application, wherein the GDS slot is adjusted to improve the flatness and electrical performance of the semiconductor device. 3 3 0 · The method as described in item 3 27 of the patent application scope, wherein the process includes a trench process. 331. The method described in the Chinese Patent Application No. 238, 239, 240, or 244, wherein the dummy filling configuration strategy includes the use of a plurality of dummy filling structure j to improve the structure of the dielectric structure of low dielectric constant to improve the dielectric structure Structural integrity. 332 · The method as described in the scope of application for patents No. 238, 23, 9, 240 or 244, wherein the dummy filling configuration strategy includes using a plurality of dummy filling targets to maintain or improve the dielectric structure of the dielectric structure with a low dielectric constant. Electrical constant. 33 3. The method according to item 332 of the scope of patent application, wherein the effective dielectric constant is maintained in all steps of a trench process flow. 334. The method as described in claim 23, 2, 39, or 240, wherein the dummy filling configuration strategy includes using a plurality of dummy filling targets in a trench manufacturing process to facilitate a plurality of low-k dielectric materials Product 335. —A kind of media, the loader can search and obtain the multiple size information included in the multiple target. Flood, and set up a device to make use of 200405184 VI. Scope of Patent Application 3 3 6. —A kind of media, which can load information, and set up the device so that the user can search and obtain the information of the rehabilitation database that contains the dummy or filled in the target or pattern. 3 3 7 · — a kind of media, which can load information, and set up a device so that water users can search and obtain the plural database contained in the plural dummy entry rules. Beacon 0003 3 8 — a method, including the following step: Maintain a database of semiconductor dummy fill information (library &gt; link the database and use it to generate multiple dummy fill configuration specifications and &quot;, change dummy fill information to update the database. 3 3 9 ·-One method, It includes the following steps: 1. Store calibration information according to at least one of the following: multiple process tools, multiple recipes, and multiple processes; and update the calibration information to reflect changes in the manufacturing process, the recipes, or the processes. 34. The method described in item 339 of the scope of patent application, which also includes generating a dummy filling strategy using the calibration information. 341. The method as described in item 339 of the scope of patent application, which also includes selecting a plurality of process tools, a plurality of formulas, and a plurality of processes from a calibration database of a plurality of dummy filling characteristics. 342 · A method, including the following steps: The user can obtain a semiconductor design institute through a one-click (s i ng 1 e c 1 i ck) operation through a user interface command of a user interface device. Page 309 200405184 VI. One of the scope of patent application is a dummy filling strategy. 343 · As described in the scope of application for patents No. 238, 2 3 9, 240 or 244, the process of “Fuzhongzhong Haihai process including the trench process (damascene process) 344 The method described in item 244, which also includes: A user can use a plurality of network services on the network to obtain a dummy filling strategy required for a semiconductor design. 3 4 5 · A method, including the following steps: The variation of the dimensions of the complex elements of the integrated circuit, according to the change in the topological pattern generated in the two-body circuit (t〇p〇graphica ^ I, sigh meter to make Integrated circuit, in which the variation in the size of these components is due to the variation in the topological pattern. The 346 of the part size is the method described in item 345 of the scope of patent application, basing the topological pattern: the process includes electroplated copper deposition or or Chemical-mechanical grinding. • As described in item 345 of the scope of the patent application, the beans are continuously produced. The method described in item 347 of the patent application scope of the invention, "The one-time manufacturing process includes a plasma etching process." A method includes the following steps: A pattern auxiliary model is used to change the topology pattern, and the circuit is accumulated. Variations in the size of multiple components or electrical characteristics are based on one of the two processes that produce topological variation: “Heiji electric: the surface of the heart” is produced; and Such history of the preset size or electrical characteristics of elements in weight. 1057-5667-PF (Nl) .ptd Page 310 200405184 VI. Patent Application Range 3 5 0 · —Parties use topological diagram circuits based on the inclusion of lithography or change these pre-feature packages 3 5 1 · If the application process includes plasma etching or trench depth. 3 5 2. If the feature is required, please include the plural number 3 5 3 • If the application feature includes the plural I 3 5 4 • If the application process includes the electric and mining steel Shen 3 5 5 Including component width 3 5 7 · If the application feature is related to the household catties 3 5 8. If the Chinese language youth feature is related to the household catties 3 5 9 A plurality of patents are included in the yuan, and the size of the patents and the patents are the features of the patents. Patent Fan Grinding. Patent scope. Patented patented patented patented patented patented patented patented patented patented patented patented patented patented patented patented patented patented patented patented patented patented patented patented patented patented patented patented patented patented patented patented patented patented patented patented patented patented patented patented patented patented patented patented patented patented patented patented patented patented patented patented patented patented patented patented patented patented patented patented patented patent for patented patented patented patented patented patented patented patented patented patented patented patented patented patented patented patented patented patented patented patented patented patented patented patented patented patented patented patented patented patented patented patented patented patented patented patented patented patent, patented patented patented patented patent. The characteristics are in accordance with the dimensions of the element or the plurality of electrical characteristics. The method described in item 35 of this system 'its media, and other characteristics include the angle of the side wall' # the method described in item 3 50 And the design;, of which. , Of which the method described in item 350 above is used. , Where the method described in item 350 is described in the method, /, wherein the method described in item 350 is described in the method, /, wherein the method described in item 350 is described in, The party / circuitry described in item 350. , Of which the parties described in Item 350 /, which change within the circuit. Method described in item 3 50 〇57-5667-PF (Nl) .ptd Page 311 200405184 VI. Scope of Patent Application These predictive features include changing the width of plural components. ^ * 36 0. The method as described in item 35 of the scope of patent application, wherein changing the predicted characteristics also includes changing the topological variation. 36 1. The method according to item 35 of the scope of patent application, wherein changing the predictive characteristics of the child includes changing complex physical and electrical parameters due to changes in size and width. 36 2. According to the prediction or change from a network as described in the scope of patent application No. 3 50 method, which is based on a response (reSpOnse) to complete the ground connection 36 3. A network server 364. Topological pattern The number of different parts of the process 3 6 5. Process characteristics 36 6. Process formula 36 7. Process formula 36 8 · Process formula 36 9. If the scope of the patent application is provided, the forecast or the pattern of the patent scope will be changed. Or characteristics. If the application includes the plural, if the application includes the job, if the application includes the plural, if the application includes the plural, if the application includes the plural, if the application includes the plural, if the application includes the plurality, if the application includes the plural, if the application includes the plural, the power distribution range, the mutual benefit range, and the power supply profit range # 刻 时 利 范围 item 3 50 The method described is based on this change. The method described in item 350. The attached model, pre-cooking / useful characteristic steps include 舻 | complex of the circuit L 栝 according to at least two interactions Item 364. Method described in item 365. Different tool settings. / Method described in item 3 6 5. Method described in item 365.方法 Method described in item 365 Which among which among which among which among which among which 1057-5667-PF (Nl) .ptd Page 312 200405184 VI. Patent application process recipe includes 37 0 · If application process recipe includes, 3 7 1 · If application process recipe includes 37 2 · If application process features include 37 3 · Russian tools are composed of two 37 4 · Russian process features include 37 5 · Russian consumables include multiple 3 7 6 · If the claim is based on these pre-377. If the application step is for multiple grinding, please patent When the range is deposited, please apply the range pressure. Please patent range plural tools. Request patent scope Different suppliers Please patent scope Multiple consumables Please patent scope Digital photoresistor or patent scope Measured in these systems Please patent scope is a service room in a network. Method described in item 365. The method described in item 365 The method described in item 3 6.4 Provided by the method described in item 3 7.2 c The method described in item 364 0 The method described in item 374 Several photomask types. Choose from the method features described in item 3 6.4. The method described in item 3 4 5 of which among them among others of which among others among which also includes among others of this special The method of combining patent scope steps, including the case attached model road includes an internal levy based on the complex 3 7 9. As stated in the claim and the characterization 38 0.-using a method network described in item 377 of a figure, Or an Internet, and it is provided on request. The method described in item 3 45, which also includes an electronic design automation (EDA). The following steps · Prediction of the complex component size of an integrated circuit 1057-5667-PF (Nl) .ptd Page 313 200405184 VI. Variation of patent application scope 'The integrated circuit is based on one of the manufacturing processes including the topological change of the integrated circuit (i mpar t) Made by design. 3 8 1 · The method as described in item 38 of the scope of patent application, wherein the process includes electroplated copper deposition (ECD). 3 8 2 · The method as described in claim 380, wherein the process includes chemical mechanical polishing (CMP). 3 8 3 · The method described in item 380 of the scope of patent application, wherein the model prediction variations in component dimensions are due to the interaction between the process step and a lithography or surname engraving process. 3 8 4. The method according to item 38 of the scope of patent application, wherein the characterizing step serves as one of a network. 385. The method as described in item 384 of the scope of patent application, wherein the network includes an internal network, an external network, or an Internet, and the characterization is based on a plurality of user requests. provide. 38 6. The method described in item 38 of the scope of patent application, which also includes an electronic design automation (EDA) in combination with the characterization step. 3 8 7 · A method that includes the following steps: A pattern accessory model is used to predict the one-level integrated circuit size feature of the integrated circuit, which is manufactured according to a design; and confirm that the predicted component size characteristics meet the requirements of the design. 3 8 8 · The method described in item 38 of the scope of patent application, which also includes adding a circuit element to the design after predicting the size characteristics of the net element, and confirming after adding the element to the design The predetermined component size characteristics meet the design specifications. 1057-5667-PF (Nl) .ptd Page 314 200405184 VI. Scope of Patent Application 1 3 8 9 • The method described in item 387 of the patent application scope, wherein these features include component width. 3 9 0 · The method described in the scope of patent application No. 387, wherein the prediction and the confirmation are provided by an Internet service. 3 9 1 · The method as described in item 390 of the scope of patent application 'where the network includes an internal network, an external network, or the Internet, and the prediction and confirmation are based on multiple user requests While offering. 3 9 2 · The method described in μ 7 of the scope of patent application, which also includes an electronic design automation (Eda) ° 3 9 3 ·-a method, including the following steps: A pattern attachment model predicts the complex characteristics of an integrated circuit, which is based on a process that includes (a) subimposing (imPart) a topological change of the integrated circuit, a manufacturing process, and (b) a lithography Or a design that is one of the etching processes; and confirming that the predicted features meet the plural specifications of the design. 3 9 4 · A method including the following steps: Predicting the complex characteristics of an integrated circuit using a pattern attachment model, the integrated circuit is based on a production process that includes (a) the topological change of the integrated circuit A process, and (b) a design of one of the shadow or etching processes of the high-speed string; and confirm that the predicted characteristics of the process resulting from the lithography or etching process meet the plural specifications of the design. 3 9 5 · A method, including the following steps: 1057-5667-PF (Nl) .ptd Page 315 200405184 6. Scope of patent application In a test, a plurality of components produced from the lithography information. 3 9 6 · — Use the relative change of a figure or the time-cut tool or select these body circuits. 3 9 7. As mentioned in S.1 Internet service 3 9 8. If Shenlu includes an internal levy, it is based on the complex 3 9 9. As described in Zhongbao and the characterization 4 0 · As described in the method, ultra- perform a lithography or etching process on a violet projection lithography process wafer; obtain characteristic information of dimensional variations due to the lithography or etching process on a private test wafer; or use the pattern in an attached model of the pattern in one of the etching processes The characteristic method includes the following steps: a subsidiary model predicts that the dimensions of a plurality of integrated circuits of an integrated circuit are different, and the integrated circuit is manufactured according to one of a plurality of manufacturing processes including different lithography 1 consumables; and the manufacturing process The method described in item 396 of the patent claim is manufactured based on the relative predicted variation together, and it is provided for the prediction. Please refer to the method described in item 397 of the patent scope, wherein the network, an external network, or the Internet is provided by the special user upon request. Please refer to the method described in item 396 of the patent scope, which also includes a combination of electronic design automation (EDA). Please claim No. 3 50, 39 3, 394, 39 5 or 396. The lithography process includes DUV (deep), EUV (extremely short UV), or ion (IPL). 401 · The method described in the scope of application for patent No. 35, 393, 394, 395 or 396 ’, wherein the measurement of the size of these components is by scanning electronics 1057-5667-PF (Nl) .ptd Page 316 200405184 VI. Patent application scope Microscope SEM (SCa ηη Ί · 1 Measuring and scanning seedling type probe display ectrón microscopy), scattering volume needle microscope, drafting The line edge is shown in FP r, roughness, or ^ LER (line edge 乂 one degree and two places). 40. A method, including the following steps: Use a pattern attached model to confirm a product # 斗 & gt Zhao Zao. Focused on the complex limitation of the lithography tool-net = = =; the method described in item 402 'where is * ^ ^ ^ ^ ^ outside 4 networks, or an Internet And this specialization is provided according to the request of multiple users. It includes the method described in item 402 of the patent application scope, which also includes an electronic design automation (εμ) that combines two steps. 6. A method including the following steps: Predicting a design of a level of an integrated circuit using a pattern attachment model 疋 = can be imaged lithographically based on the design; right no, withering the design or complex process parameters to Achieve imaging. 4 0 7 · If the scope of patent application is the fourth The method according to item 6, wherein the step of correcting γ includes selecting a plurality of optimal tool settings for a lithography tool. 4 0 8. The method according to item 4 of the patent scope of claim 4, wherein the adjusting step includes Select a plurality of the best photoresist materials. 4 0 9 · The method as described in Shen Jing Patent Scope No. 4 06, wherein the adjusting step includes selecting a plurality of optimal photoresist deposition formulas. 1057-5667-PF (Nl). ptd Page 317 200405184 VI. Application scope of patent 4 1 0. If the middle step includes the adjustment 4 1 1. If the middle step includes the adjustment 4 1 2. If the middle step includes the adjustment 4 1 3 · If the middle step includes the adjustment 41 4 · eg The application process includes adjusting 4 1 5 · If the application process includes adjusting the δ month, the patent scope, the entire tool, the patent scope, the power source, the patent scope, the patent scope, the etching, the patent scope, the patent scope, the patent scope, and the patent scope, An integral and plural pressure method, including a case-attached model according to (a) a production process and one process, manufactured by design; using the plural setting described in item 406 of the lithography or prediction feature and the corresponding module The method, wherein the method described in the tune right item is set. The method described in item 406, in which time 416 types are carved by lithography or # 417 using a picture integrated circuit system. A method described in item 406 when tuned in a tone, 1 time . Item 406. Time. The method of the method, in which the fourth step of the tuning is described in the following step of the tuning, wherein the tuning is: the complex characteristics of the ir integrated circuit, the sum of the topological changes of the cutlery and the integrated circuit (b) — One of the two processes of photolithography or etching process is to generate a photomask to perform the photolithography or post-etching process; ^ ^ Table 'interaction makes these designs different from each other; The photomask is trimmed to reduce the effect of the phase J w interaction between the process and the production process. The method includes the following steps. The tool has not been smashed during production—n places are less than one grade of the tool 1057-5667-PF (Nl) .ptd p. 318 200405184 Use a pattern attached) to conform to the tool (degree) without being able to generate a suitable component size, the model predicts a position (focus limit of a location of an integrated circuit); and = at least the mask or the design obtained So that the lithography tool can generate a suitable component size at these positions. 41 8 · The method as described in item 41 of the patent application scope, wherein the focus limit includes the depth of focus. 41 9 · as the patent application scope 41 The method according to item 7, wherein the tool includes a lithography stepper. 42 0 · The method according to item 41 of the scope of patent application, which also includes using an electronic design automation (EDA) tool combined with at least The prediction or one of the decisions. 4 2 1 · The method as described in item 41 of the patent application scope, wherein the pattern auxiliary model receives at least one of the following as input: a complex layout or design specification of an integrated circuit, The plural parameters and plural settings of the lithography tool, and the information of the plurality of test wafers produced by the lithography tool. 4 2 2 · As described in item 41 of the scope of patent application Method, wherein the step of using the pattern accessory model includes determining whether an integrated circuit can be manufactured based on the use of the lithography tool. 4 2 3 · The method as described in item 4 17 of the scope of patent application, wherein the Not counting or the photomask also generates a suitable electrical property. 4 2 4 · The method as described in item 41 of the patent application scope, wherein the position is in an area of the design and the lithography is not adjusted during production tool. 1057-5667-PF (Nl) .ptd Page 319 200405184 VI. Patent Application Range 42 5. The method described in Patent Application Range Item 4 17, where the design includes a plurality of other integrated circuits, and during production The lithography tool is adjusted between the complex product circuits to meet the focus limit. 4 2 6. The method according to item 417 of the scope of patent application, wherein the design or the mask is changed so that the lithographic tool can generate a suitable element size at those positions. 4 2 7. The method of claim 417, wherein the element size includes a line size. 42 8. The method as described in claim 417, wherein the element size includes line spacing. 42 9. The method as described in item 41 of the scope of patent application, wherein the element size includes linear density. 43 0. The method as described in item 41 of the scope of patent application, wherein changing the design or mask includes changing the dimensions of the plurality of elements in the design or mask. 43 1. The method according to item 41 of the scope of patent application, wherein one of the prediction or the change is provided by an Internet service. 43 2. The method according to item 431 of the scope of patent application, wherein the network includes an internal network, an external network, or an Internet, and the prediction or change is provided according to a plurality of user requests. 4 3 3. A method including the following steps: Performing a virtual adjustment of a lithography tool and a distance from a position in a region of a wafer, and predicting one of the mask layouts generated by a pattern attached model The mask performs the virtual adjustment, the position in the area of the wafer 1057-5667-PF (Nl) .ptd Page 320 Because of this lithography tool-focus limit 434, such as the size of the upper part of the main shot. · Declaration of the depth of the square basin described in item 4 of the patent scope No. 4 3 (1 == enclosed: 435 ^ The method described in item 433 of the patent scope &gt; method ^ which also includes physically Wafer _ t $ 工程 &gt; Adjust the imaging tool in one of the areas: Γίί—distance 'to comply with the focus limit. Change the method described in Item 433 of the original jealous range, Among them is the revision of the original original mask layout: part to generate the layout. A '™ 4 ^ 7 is connected to the method described in item 433 of the t * sf patent scope, which includes a * single integrated circuit. 43 8 The method according to item 433 of the patent application scope, wherein the area of the wafer has a size smaller than one of the preset dimensions. 43 9 The method according to item 433 of the patent application scope, wherein A mark on the wafer physically adjusts the distance of the lithography tool from the area. 44 0. The method described in item 433 of the patent application scope, which also includes: Virtual adjustments to other plural positions are performed in this area of the wafer. 441. The method described in item 433 of the scope of patent application, which also includes: performing virtual adjustments to other plural positions outside the area of the wafer. 4 4 2 · The method as described in item 4 33 of the patent application scope, wherein the element size includes a line size. 1057-5667-PF (Nl) .ptd Page 321 200405184 VI. Patent Application Range 44 3. If the size of the item includes 444. If the size of the item includes 44 5. Adjust the one-to-one integrated circuit to conform to the extension 44 6 • Such as a network service 4 4 7 • Rulu includes an internal test or change system 448.-Using a test wafer; according to the route due to the lithography 44 9. Such as the hood design includes 4 5 0 • Such as the hood design Including applying for special line spacing, applying for special line density methods, and attaching the pattern, and using it for the flapping change application to provide the application department network based on the multiple methods of lithography or profit margins. . Lee Fan Park forecast or profit range, a number of uses' including the characteristics of etching patterned wafers, the use or etching process production patent range of various types of lines and spacing patent range of multiple levels of the method described in item 433 , Wherein the method described in item 433 of this element, wherein the element has the following steps: predicting the complex number; M jhm bitopological mutation, which occurs in a pre-lithographic lithography process step; and the complex number of the complex mask in the process step is designed to The method according to item 4 3 3, wherein one of the changes is made. The method according to item 446, wherein the network, the road, or an Internet is provided by the request. The following steps: process generation—the mask design uses a pattern to measure the process; and a pattern attached model predicts the complex characteristics of the complex product. The method according to item 448, wherein the light size. The method according to item 448, wherein the light-weighted masks' include each type of Hi 1057-5667-PF (Nl) .ptd page 322 200405184 6. Scope of patent application Line and pitch size. 451. The process described in item 448 of the scope of patent application includes a preset lithography or etching tool, or the method of lithography, wherein the system 45 2. The &amp; or etching formula as described in field 448 of the scope of patent application. The process includes multiple preset power settings. 45. The method includes the preset etching time as described in item 448 of the patent application scope. Method 'wherein these 454. As described in item 448 of the scope of patent application, the process includes a plurality of preset grinding times. ’’ Which 45 5. The process according to the scope of patent application No. 448 includes a plurality of preset deposition times. '' The methods described in Item 448 of the Eighth Middle School and the Second Force System 457 · Such as: The method described in Item 448 of the Patent Scope, which includes the generation: step, the characterization step, and the prediction At least one of the steps is a step of a Electronic Design Automation (EDA). 45 8. The method according to item 448 of the patent application, wherein the method according to item 448 of the patent application, wherein the generating step, the At least one of the levitation step and the prediction step is provided as a service along the way. 45. The method according to item 449 of the scope of patent application, wherein the network includes an internal network, an external network, or an Internet, and the generation step, the characterization step, and the prediction step It is based on the use of plural numbers to provide two. 1057-5667-PF (Nl) .ptd Page 323 200405184 VI. Patent Application Range 4 60 0 If the formula includes a 461.-Using an application-specific preset light method, pattern attachment circuit, production profit scope, resistance. , Including the genus model, is based on a process that is manufactured by mutation, one of the integrated circuits; and determines the effect of the integrated circuit. 4 6 2. — A method using a pattern difference, the integrated circuit is one of the circuit manufacturing processes; and determining the effect. 4 6 3 · If applying for the prediction of the complex element of the integrated circuit 464 · If applying for the special law, where the electrical integration, power distribution, (timing closure 4 6 5 · If applying for the special, including the model According to the package's and the integrated circuit's multiple range of the size range, the range of profit includes thinness and examination.) Analysis of the range of profit ---------- Item 4 4 8 of the method, where the following steps _: Forecast — 穑 _ + h Dimensions of complex elements of integrated circuits and (b) One minute topology change to the integrated lithography or etching process and waiting for 70 pieces of dimensions to mutate into complex electrical properties — The following steps: Predict an integrated The complex number of the circuit contains ") the number of topological changes to the flapping change (b)-and Dan, the dagger to the integrated alkali shirt or the etching process and other components are dimensional variations in one of the 462 The method described above, one or two caused by the multiple changes in the size of the component, including the multiple changes in the package, determine the film resistance, capacitance, and drive electronics of the item 461, 46 2 or 463, considering multiple levels of interconnects.拄 ^ 、 Signal. Also closed in time sequence 4 6 1, 4 6 2 or 4 6 3 items 1057-5667-PF (Nl) .ptd Page 324 200405184 VI. Patent Application Law, which also includes changing the design to meet preset specifications. 466. The method described in item 461, 462, or 463 of the scope of patent application ', which also includes adjusting a plurality of photomasks for the lithography or etching process according to the influence of the decision. 46 7. The method described in the scope of application for patents No. 461, 46 2 or 463, which also includes adjusting the design to improve the process capability of the bulk circuit according to the impact of the decision. Λ, 46 8 · The method described in item 461, 46 2 or 463 of the scope of patent application, which also includes adjusting the design to improve the circuit performance of the body circuit according to the influence of the decision. ~ $ 46 9. The method according to item 461, 46 2 or 463 of the scope of patent application, wherein the prediction is performed based on an interconnect level of one of the integrated circuits. 47 0 · The method described in the scope of application for patent No. 461, 46 2 or 463. The method 'performs the prediction based on the multiple levels of the integrated circuit. 471. The method described in item 461, 462, or 463 of the scope of patent application ', wherein the decision of the dummy filling groove structure is determined according to the influence of the decision. ， 4 Hard number groove 472 · As described in the patent application scope No. 461, 46 2 or 463, wherein the decision is based on the influence to determine the configuration of the integrated electronic components. Plural 473. According to the method described in item 461, 46 2 or 463 of the scope of patent application, which is based on the decision of the influence to determine the loop (roututi) of the complex interconnected area between the pieces of the product and the square electrons ^) The plural number 474 is as described in the scope of patent application No. 461, 46 2 or 463. Office 〇57-5667-PF (Nl) .ptd page 325 200405184 6. The patent application method, in which the integrated circuit includes a system SyStem-On-chip), and the method also includes a number of internally connected circuits. The chip in the QC device (SOC, including the determination of this §, 47. If the scope of the patent application is 461, 46 2 or 463, so, and law, which is based on the impact of the decision to determine the integration described Square electronic components, plural interconnects, or plugs (via), several complex numbers A η η;, ^ U, structure. B • As the method of the patent application scope 461, 46 2 or 463. 'It also includes the combination of the prediction and confirmation steps-Fang Automation (EDA). Kuanko Design 47 7 · The method described in the patent application No. 46ι, 46 2 or 463', where the decision step and the At least one of the prediction steps is provided on a network as a service. 47. The method according to item 477 of the patent application scope, wherein the network includes an internal network, an external network, or a The Internet, and the prediction step or the decision step is provided according to a plurality of user requests. 4 7 9 · A method including the following steps: using a pattern-affiliated model to predict a complex lifting variation of an integrated circuit, The integrated circuit is based on the topology including (a) Change to one of the integrated circuit production processes, and (b)-a lithography or etching process is made; Determine the effect of the topological variation of the integrated circuit on one of the complex electrical properties; and use an RC extraction tool to combine the use of the model with the determination of the effect. 1057-5667-PF (Nl) .ptd p.326 200405184 48〇 · A method, including the following steps: a pattern attached model predicts a complex topological variation of an integrated circuit ... and a complex variation of a complex component size, the integrated circuit is based on the A manufacturing process of the integrated circuit is manufactured according to 7b) a lithography or etching process; determining the topological variation of the integrated circuit is a complex electrical one; and ~ using an RC capture (Extract ion) tool combines the use of the model with the determination of the impact. 481. The method according to item 479 or 480 of the scope of application, wherein the step of using the circuit is performed on a plurality of secondary areas of the circuit. * 48 2. The method as described in the 46th or 48th scope of the patent application, wherein the size of the elements includes at least one of the following: lithographic element width, etched trench width, etched trench depth, etched sidewall Total angle, dishing, or copper consumption. "48, as described in item 461, 46 2, 479, or 48 0 of the scope of patent application, where the electrical properties include thin film resistors, capacitors, drive currents, signal integration, power distribution, and timing closure ( timing cl〇sure) analysis. On 484. The method described in the scope of patent application No. 479 or 48, in which at least one of the 4 determination step and the prediction step is provided on a network as a service. 48 5 The method according to item 484 of the scope of patent application, wherein the network includes an internal network, an external network, or an Internet, and the pre- 1057-5667-PF (Nl) .ptd Page 327 200405184 VI. Scope of Patent Application The measurement step or the determination step is provided according to the request of multiple users. 48 6. A method, including the following steps: generating an electronic design of an integrated circuit, the integrated circuit is produced according to the design, and the topological distribution is performed by using the variation in the size of the components introduced into the integrated circuit A process; wherein the generating step includes adjusting the electronic design based on a complex prediction of a topological expression of a pattern subsidiary model and a complex number variation of the topologically-related component size. 4 8 7. The method according to item 486 of the patent application scope, wherein the generating also includes using optical proximity correction due to the complex optical interference effect to adjust the design. 4 8 8. The method according to item 486 of the scope of patent application, wherein the electrical properties of the electronic design include thin film resistors, capacitors, drive currents, signal integration, power distribution, and timing c 1 sure analysis . 4 8 9. The method according to item 486 of the scope of patent application, wherein the variation in the dimensions of the elements includes at least one of the following: lithographic element width, etched trench width, etched trench depth, and etched sidewall angle , Dish sinks, or total copper consumption. 490. The method as described in item 486 of the patent application scope, which also includes generating the electronic design using a configuration and loop tool. 491. The method described in claim 486 of the scope of patent application, which further includes adjusting the electronic design by connecting a resistor and capacitor (RC) capture tool. 1057-5667-PF (Nl) .ptd p. 328 200405184 Yi Bao Yi Bao Yi also includes 49. 2. The method as described in the patent scope of item 486, which includes the use of an electronic design automatic simulation tool to generate the electronic design. 49 The method described above includes using a physical verification tool to verify the electronic design. 49 6. The method described in claim 486 of the scope of patent application, which also includes guaranteeing the manufacturing capability of the electronic design. 49 7. The method according to item 486 of the scope of patent application, which also includes improving the electrical performance of the integrated circuit. 49 8. The method described in the scope of patent application No. 486, which also includes 494. The method described in the scope of patent application No. 486, including using an optical approximation correction (0pc) tool to adjust the electronic design 49 5 The method as described in claim 486, which includes using a signal integration tool to confirm the electronic design. Including improving the electrical performance of an electronic design layout of the integrated circuit. 499. The method as described in item 486 of the scope of patent application, further comprising adjusting a formatted file according to the adjustment of the electronic design, the format of the file conforming to an EDA file format. / 50 0. The method according to item 499 of the scope of patent application, wherein the file format includes a graphic data stream (GDS) format. 50 1. The method according to item 486 of the scope of patent application, wherein adjusting the electronic design step includes improving the manufacturing capability of the integrated circuit. 50 2 · The method according to item 486 of the scope of patent application, wherein adjustment Page 329 200405184 VI. Scope of Patent Application The electronic design step includes adjusting the design and improving circuit performance. 5 0 3. ^ The method of item No. 486 of the patent scope, wherein the electronic design step includes slanting; S — &amp; $ corresponds to the complex topological expression of the interconnection level prediction. 504. The method according to item 486 of the scope of patent application, wherein generating the electronic design step includes predicting multiple variations corresponding to multiple interconnect levels, and electronically characterizing or simulating multiple interconnect levels. '50 5 • The method described in the scope of patent application No. 486, which includes determining the configuration of the dummy fill or plural trench structures based on the decision of the influence. 5 0 6 · The method as described in item No. 486 of Shen Jing's patent scope, which includes determining the configuration of the plurality of electronic components in the integrated circuit. 50 7 · The method described in the scope of application for the patent No. 486, which includes determining the routing of the plurality of interconnecting areas between the plurality of electronic components in the integrated circuit ° 50 8 · The method described above, wherein the integrated circuit includes a system-on-chip (SoC), and the method also includes determining a plurality of interconnected circuits in the SoC device. 50 9. The method according to item 486 of the scope of patent application, which includes determining the geometric structure of the plurality of electronic components, the plurality of interconnections, or the plugs (v i a) in the integrated circuit. 510. The method as described in claim 486, which also includes an electronic design automation (E D A 1057-5667-PF (Nl) .ptd Page 330 200405184 VI. Patent Application Range 5U. If the patent application scope item 48β is at least one of the order and the prediction step, the method, in which the decision serves as a service. The v step is provided on a network 512. If item 5n of the patent application scope includes an internal network, an external network, and the method, the network test steps or steps, i — total score of the trace, A 4 ~ Internet, and this pre-determined step is provided based on multiple user requests. A method, including the following steps: design: an integrated circuit t-electronic design, the integrated circuit is based on the; in topology 1 and using "variation of the component size of the integrated circuit into one of the lamp topology distribution Manufacturing process; spot & iI, the generating step includes adjusting the electric power to the Han inch according to the complex number prediction of the topological formula of a pattern attached model ^ μ 41 related component size; and 15 using an RC capture tool to generate And adjust the electronic design. 4 · A method, which includes the following steps: μ-an electronic design of an integrated circuit, the integrated circuit is based on the &quot; product 'and uses the size variation of components introduced into the integrated circuit to One of the processes of topological distribution; Ganzhong &quot; 'The generation step includes the complex prediction and adjustment of the complex variation of the size of X-related components based on the topological formula of a pattern attached model 俾 jcrr 4 # -1? |… ^ The electronic design; and 〃, using an RC capture tool to generate and adjust the electronic design. 5 ^ 5 · The method described in the scope of application for the patent No. 51 3 or 514, In Ito; "performing the step of using a plurality of secondary circuits area. 1057-5667-PF (Nl) .ptd Page 331 200405184 / 、 Applicable Patent Fanyuan 5 1 6 · As mentioned in the scope of patent application No. 5 1 4, the table, the component size includes at least one of the following- Item: Micro / person V, such as windbreaker 7C Miyazaki, 4 groove width, groove depth in the remaining time, side wall in danger and the total consumption. Angle, dish, or steel 5 1 7 · As described in item 5 1 4 of the scope of patent application, electrical properties include thin film resistors, capacitors, and drive currents, among which the cloth, and timing closur integration, The power supply is divided into two steps: step 513 or 5U on the road as described in Section 513 or 5U. At least one of these steps is step 519. For example: J Yuan. Steps are provided in a network including an internal target. 5] The test steps described in item 8 or the external network, &lt; H, where the network 52 0.-kinds; the system is based on the plural number of the 3 network 'and the pre-production, including the T ^ &Lt; The integrated circuit includes the following steps: · Design and production of the 7-side design using the sub-elements, the integrated circuit is based on the &amp; complex component size variation to the integrated The manufacturing process of the circuit uses the sign. The Γ integrated circuit is a model prediction-one of the complex special circuits of the integrated circuit. ▲ Manufacturing process 521 According to the complex number of a person's collar, it is divided into a (&amp;) points. Topological change to the product (b)-lithography or etching process and seeding method A subsidiary pattern comprising the steps of i: an integrated circuit-based drink &amp; 7 genus wedge Chu, Japan, manufactured by Shi ~ light based prediction wherein a plurality of integrated circuits of the - King - Design and manufacture; and 1057-5667-PF (Nl) .ptd Page 332 200405184 VI. Scope of Patent Application Based on these predictive features, determine the number-allocation attribute. 2. The number of complex components of the circuit 5 2 2. As in the scope of application for patent No. 52 !? The set attributes include the design-in-configuration and 'method, in which the internal buffer plug and the complex buffering step of the multiple wires determine the complex , 52 3. If the scope of the application for the 52nd item-the plural attributes. Predictive features include width variation or topological variation, among which methods include the configuration locations of electronic active components. And, such configuration attribute packages, 52, such as the scope of application for patent No. 521, the prediction of special policies include width variation or graphical variation; ^ method, where these include a plurality of interconnected lines across the integrated circuit Yuan ^ = such configuration attribute package 52 5. As described in item 521 of the scope of patent application-loop. Predictive features include the provision of dummy fills or multiple trench structures, of which 52 6 · as described in item 521 of the scope of patent application. Predictive features include the geometric structure of λ-fighting buckets, * batches, prostitutes L <10,000 ′ sets, of which Πί or plural groove structures. 5 2 7 · A method, including the following steps: Geometry = a ^ accessory model predicts the complex electronic component structure of an integrated circuit, the integrated circuit is manufactured according to a design of a process, the: = child element geometry The prediction is based on a complex width variation or a complex topological variation produced by the process. ) 52 8. The method as described in item 527 of the scope of patent application, which includes adjusting the design to improve the circuit performance of the electronic components. ^ 52 9 · The method described in the scope of patent application No. 527, including adjusting the design to improve the plural structural or reliability characteristics of these electronic components Page 333 200405184 Six. Patent application scope. 5 3 0. A method including the following steps: Based on one of one or more steps of one of the production processes, an electrical impact analysis and a pattern attachment model, a strategy is generated for complex buffers or buffers A repeater to determine the size and configuration; and to use the electrical impact analysis and the pattern attached model to evaluate the expected results of configuring the buffers or repeaters; wherein the model and the electrical impact analysis Usage is integrated into the buffer or repeater strategy generation part. 5 3 1. A method including the following steps: determining the number of buffers or repeaters in the plurality of interconnects based on an electrical impact analysis of a production process in one or more steps and a pattern attachment model; And using the electrical impact analysis and the pattern accessory model to evaluate the expected results of configuring the buffers or repeaters; wherein the use of the model and the electrical impact analysis is integrated into the buffers or repeaters Part of strategy generation. 5 3 2. A method including the following steps: Predicting or simulating the complex transfer delay of a single or multiple interconnected levels based on an electrical impact analysis of a production process in one or more steps and a pattern attachment model. 53 3. The method according to item 532 of the patent application scope, wherein the use of the model and the electrical impact analysis is integrated into a part of the buffer or repeater strategy generation to reduce the complex transfer delay. 1057-5667-PF (Nl) .ptd p. 334 200405184 53 4. If the scope of application for patent No. 532 and the method of the electrical impact analysis Α Λ, 迩 method, among them Rong Mo 53 5.-a method, but also a part of I private. But Liqi ’includes the following steps: According to one or more steps — &mp; — m ^ m Μ ^ 1 one of the production processes, the electrical environment impact analysis and volume consumption. The ability of j to be one or more levels of interconnections 53 6 · The method described in item 535 of the scope of the patent application, which also includes: The use of sexual impact analysis is integrated into the buffer or relay Generate a part for strategy to reduce energy consumption. 5 3 7 · The method described in item 535 of the scope of patent application, which also includes the 钂 model and the electrical impact analysis as part of the design change process. 5 3 8 · The method described in item 5 35 of the scope of patent application, which also includes the model and the electrical impact analysis as part of an energy and timing analysis process. 53 9. The method described in the scope of application for patent No. 535, which also includes the model and the electrical impact analysis using energy, signal integration, and timing analysis tools. . 5 4 0 · The method described in item 5 35 of the scope of patent application, which also includes the model and the electrical impact analysis using a design rule checker (DRC) or a layout verification tool (LVS) Layout verification schematic) 〇5 41. The method described in the scope of application for item 535, which also includes the model and the electrical impact analysis using resistance and capacitance acquisition tools. 54 2. The method according to item 535 of the scope of patent application, wherein the system 1057-5667-PF (Nl) .ptd p.335 200405184 6. Scope of patent application Process flow includes CMP 54 3. The method described in item 535 of the scope of patent application, wherein the process flow includes steps such as plasma etching, lithography, or deposition process. / 5 4 4 · A method including the following steps: According to one of the one or more steps of one of the production processes, the electrical impact analysis of a pattern attached model predicts the width of the element in a single layer of the complex interconnected geometry ^ With thickness. "5 4 5" The method as described in Item 5 31 of the scope of patent application, wherein the size of the elements includes at least one of the following: lithographic element width, engraved groove width, remaining groove Depth, etched sidewall angle, dishing, or total copper consumption. &lt; '° 5 4 6 · A method including the following steps: According to one or more steps, one of the production processes electrically affects a pattern attached branch type, and generates a strategy to configure a dummy entry in the process? and °, '' Use the electrical impact analysis and the dummy of the pattern auxiliary mold to fill in the pre-size of the buffer size and configuration. ^ The model and the electrical impact analysis use the puncher strategy to generate the size and configuration strategy. a part. Zheng Cheng 547. One ΐ: Law 'includes the following steps: Use a pattern attached to the cat, ai ^ The plural j occurring in an integrated circuit is interconnected by a predetermined interconnect level The structure of ί ;; 异; and to comply with such variations. Dimension adjustment and configuration processing of% punch 苐 Page 336 200405184 6. Scope of patent application 5 4 8. If the application procedure is the same as the service. 54 9. Rushen Road includes an internal test step or the decision 5 5 0. — A kind of auxiliary mold 55 according to a pattern or a pattern 55 — a kind of auxiliary mold 55 according to a pattern or a pattern 2. If applied, return 5 5 3 · — Use the fruit according to one or a pattern accessory mold. 5 5 4. The result of the claim is in the plural 5 5 5 · The result of the claim is in the plural 55 6. At least one of the steps described in step 547 of the scope of the patent application is fortuned, where the adjustment is provided on a network The method described in item 548 of the patent scope, wherein the network, an external network, &amp; an Internet, and the predetermined step is provided according to a plurality of user requests. The method includes the following steps: One of the multiple steps, one of the production processes, and one of the electrical impact analysis and modeling, determining the configuration of the complex integrated circuit components. The method includes the following steps: One of the multiple steps, one of the production processes, and an electrical impact analysis and type 'determine the circuit of the complex integrated circuit wiring. The method described in the patent scope No. 531, 53 2 or 535 is required to give feedback to the method of configuration and loop system reduction, including the following steps: Eight analysis and multiple steps One of the production process One of the electric ring sound type It is decided that: ^ ^ Sexual impact analysis and the attached model of the pattern take the right to the method described in item 553 of the patent scope, in which all or part of the image of the wafer is displayed. Please refer to the method described in Item No. 5 53 of the patent, in which the type of the statistical bar graph is displayed. Please refer to the method described in the scope of patent No. 554, wherein these 1057-5667-PF (Nl) .ptd Page 337 200405184 6. Scope of Patent Application ff image includes thickness, total copper consumption, and film information. , Resistance, dishing, and erosion 55 7 · If the scope of the patent application No. 5 55 households, the bar graph includes the method of thickness 胄, copper consumption total 1 kg ^, among which I insect information. Seek film resistance, dishing, and invasion 5 5 8 · If the scope of patent application is No. 553, compare two or more levels of design. The method by the staff, which is based on 55 9 · If the patent application for the 3 items of the technical design is the same as the &amp; + evening, the method of making only W fans, which is based on 56 0 or more process recipes or tool setting room Compare. The method described in item 553 of the same ft patent scope, in which the comparison is performed between the two process steps of the heart leaf. Cake, such as the patent application scope of 553, 554, 555, 556, 557 or DD u Bu, a method, where the results are displayed through a web browser or ^ 5 6 intranet, an external network, and an Internet. 2. If the scope of patent applications 553, 55 4 , 555, 55 6, 55 7 or 5 5 8 in which a result is used to select a design for manufacturing. 5 6 3 · A method including the following steps: Selecting a plurality of positions on a device for For measurement, the device is manufactured using at least one production process, where 'these locations are selected according to a pattern auxiliary model of the process. 5 6 4 · A method including the following steps: Selecting a plurality of positions on a device to measure It is estimated that the device is manufactured using at least one production process, 1057-5667-PF (Nl) .ptd Page 338 200405184 6. Scope of Patent Application Among them, these locations are selected based on the electrical impact analysis of one of the processes. 5 6 5 The method described in item 563 of the scope of patent application, which also includes selecting the locations according to an electrical impact analysis of one of the processes. Where the system is based on which of which the system of which the system of which system of which system of which system of which of which system of which is 5 6 6. The method described in the scope of the application for patents 5 63 includes chemical machinery Grinding. 5 6 7. The method described in item 5 63 of the scope of patent application. A measurement strategy selects these positions. 5 6 8. According to the method described in Item 5 63 of the scope of patent application, the selected position is part of a measurement formula. 5 6 9. According to the method described in Item 563 of the scope of patent application, the selected position corresponds to a measurement strategy. 5 70. The method according to item 563 of the scope of patent application includes electrochemical deposition. 5 7 1. The method described in item 56 of the scope of patent application includes two or more stages. 5 7 2. The method described in item 5 71 of the scope of patent application includes two or more processes. 5 7 3. The method described in item 57.1 of the scope of patent application includes two or more steps of a single process. 5 7 4. The method described in item 5 71 of the scope of patent application. The two stages include deposition and chemical mechanical polishing. 5 7 5. According to the method described in the scope of patent application No. 5 71, the positions selected include the positions in the plurality of crystal cubes and the plurality of wafers (crystal cubes to crystal cubes). 1057-5667-PF (Nl) .ptd Page 339 200405184 6. Scope of Patent Application 5 7 6 • One of the two phases of the package 5 7 7. One of the two phases of the package 5 7 8 One image, one pre-selection tool or 57. 9. If the attached model of the application has at least parameters such as difference, trap, or 5800. · If the attached model of the application, please include lithography in item 57.1 of the patent scope. The method described above, among which the method of patent scope No. 5 71, +, ^ including the method of the name of the electric carcass engraving 34, of which the method described in the scope of patent scope 563, which also includes 3 A test wafer or a plurality of test semiconductor devices are produced according to the clothing &amp; recipe to generate the pattern accessory model. The method described in the May patent scope item No. 563, wherein the figure should be the state of the plurality of wafers generated by the auxiliary features of the plurality of patterns. One of the following: · The final film thickness, film thickness becomes invaded. Please refer to the method described in Item 563 of the patent scope, wherein the figure shall include at least one of the following electrical parameters generated by the auxiliary features of the plural pattern: · film resistance value, resistance value, capacitance value, crosstalk noise, voltage Drop, drive current loss, dielectric constant, and effective dielectric constant. 581 · The method described in the scope of patent application No. 563 or 564 'which also includes: The use of a cost function to determine the measured complex digit f °, 58 2 · The method described in the scope of patent application No. 563 or 564 ', Based on one selected by $. On the attached model of the pattern, I ^ ^ ^ 5 8 3 · As applied .. L method ’which also includes the π described in the scope of patent 581 1057-5667-PF (Nl) .ptd P.340 200405184 The cost function selects a plurality of positions to measure the dummy fill. The method also includes: Deploying on a network in one of the methods described in item 563 or 56 4 of the patent application scope, where end 58 5. As also includes : Located in a user's selection. 5 8 6 • According to the device 5 8 7 • According to the device 5 8 8 • If the device includes at least 5 8 9 • If the location selects the dielectric constant element 5 9 0 • As received from the server A client sends to a semiconductor package and multiple design specifications; the server selects these positions; and the selected position information is returned from the server to the client's patent application scope 5 6 3 or 5 6 4 The method described in item 1, in which a messenger on the network can use a service that allows the semiconductor design, a manufacturing process, and the location of a device to apply for a patent range of a single interconnected range of benefits. The scope of a semiconductor crystal profit includes the structure of the profit structure, the application of multiple applications, the application of one of the steps, and the method described in item 563, which selects these positions hierarchically. The method according to item 56 is to generate the measurement plan hierarchically. The method according to item 56 is to round or a semiconductor wafer on a wafer. The method according to item 563 or 564, wherein the subject improvement complex number is filled with a dummy number to fill in the object. The method according to item 563 or 564, wherein the root is the root 1057-5667-PF (Nl) .ptd Page 341 200405184 VI. One of the constant elements selected at this position in the scope of patent application 591. Russ groove process 5 9 2. Russ process 5 9 3 Russ The improved low-dielectric step of selecting the ladder at this location includes filling in an effective dielectric constant of eight using a plurality of dummy values. Please refer to the square constant in the patent scope No. 589. To maintain the effective referral in all steps, one of which is described in item 5 90 of the patent application, and to maintain the effective referral in all steps of the patent scope, please refer to item 563 or 56 of the patent range. A Yulian 'eight steps include the use of multiple dummy filling of eight birch 6' slot manufacturing process with low dielectric constant material structure method, in which a complex one, 5 9 are formed in a process 4. As the scope of patent application No. 5 6 3 or 5 6 4 The method described in the item above also includes: maintaining a database of plural positions; the database can be connected with generating a complex measurement strategy; and updating the database according to new or improved tools. 59 5. The method according to item 563 or 564 of the scope of patent application, further comprising: storing measurement information according to at least one of the following: a plurality of process tools, a plurality of recipes, and a plurality of processes; and according to these process tools, recipes , Or process changes to update the measurement information. 5 9 6 The method according to item 5 6 3 or 5 64 of the scope of patent application, further comprising: a user can click through a single click of a user interface device with a user interface as A device selects plural positions. 1057-5667-PF (Nl) .ptd Page 342 200405184 Application for Patent Scope 59 7. If the scope of patent application for 563 or 564 also includes: Wan Qu, soldier equipment: obtained through ―multiple Internet services on the Internet, It also includes 98. The method as described in item 563 or 564 of the patent scope, in which a user can confirm a plurality of positions according to the production process or process through a service on a network. M device, 々59 9. The method described in item 563 or 564 of the patent application scope, wherein the dedicated position is selected to characterize the variation of the plurality of electrical parameters. The method described in item 599 of the electrical patent scope, wherein these quotations include one of the following: film resistance value, resistance value, electricity :: two crosstalk noise, voltage drop, drive current loss, Dielectric effective dielectric constant. Shuang Yi spoon 2 1 · The method as described in the May patent scope No. M3 or M4, wherein a plurality of pattern attachments are extracted from one layout of the device. The pattern belongs to the method described in item 601 of the patent scope, wherein the β /,, and the corresponding line spacing, line width, or line density. 6 〇 3 · As described in the application of the scope of the patent 563 or 564 method, 1 ′, dagger using these selected positions to provide feedback to one or a formula synthesis. Market system • As the method described in claim 5 6.3 or 564, the system selects these positions for a semiconductor wafer. Eight 200405184 VI. Scope of patent application ^ 6 0 5 · The method as described in item 563 or 564 of the scope of patent application, wherein these positions are selected for one or more sets of semiconductor crystals in a wafer. /, 6 〇 6 · The method as described in item 563 or 564 of the scope of patent application, wherein these positions are selected for one or more groups of wafers. 6 〇 7. The method described in the scope of patent application No. 563 or 564, wherein these positions are selected for one or more batches of wafers produced by a product. y 6 0 8. The method according to item 5 6 3 or 5 64 of the scope of patent application, wherein a tool is used to select the positions. 6 0 9 · The method as described in Item 563 or 564 of the scope of patent application, wherein the positions are selected using a process control or advanced process control system. 6 1 0 · The method as described in the scope of patent application No. 563 or 564, wherein the selected locations are via an external network, an internal network, the Internet, or a virtual private network. Connected electronically or optically to a process or tool. 6 1 1 · The method according to item 5 6 3 or 5 64 of the scope of patent application, wherein the selected positions are based on at least one type of electrical parameter variation tolerance in the following rules: capacitance value and resistance value , Film resistance value, output delay, skew, voltage drop, drive current loss, dielectric constant, or crosstalk noise. 612. The method according to item 563 or 564 of the scope of patent application, wherein the selected positions are based on at least one type of wafer parameter variation tolerance in the following rules: film thickness, dishing, and erosion. 613 · A method including selecting a plurality of measurement positions for an entire semiconductor wafer, and the positions are selected according to a single interconnect layer of the wafer 〇57-5667-PF (Nl) .ptd Page 344 200405184 VI. One of the scope of the patent application. A pattern attached model. 14 · Methods, including identifying the position of a whole semiconductor, the selection of positions such as 1H is based on the wafer :: selecting a pattern auxiliary model of the complex f amount. θ eve heavy interconnecting level 6 1 5 ·-a method, including the following steps · · In production, according to the wow $ 闰 ^ Measure a "f production of a pattern attached model measurement plan to measure Testing a device; and 'changing the state of the multiple wafer parameters during production. The changes in the construction of the complex number have been predicted 6 1 6 · As described in item 6 丨 5 of the scope of patent application, it is included in the change of multiple electrical parameters during production Plural has been /, which also includes 6 &quot;. A method, including the following steps: the predicted variation. According to a chemical mechanical polishing process, a day is measured to measure a device; a quantity attached to the model Measure and identify the multiple areas of the device to completely remove the substance in the chemical machine. After mechanical grinding, there are still 6 1 8 · ~ methods, including the following steps: According to one of the patterns attached to the production-Dan Semiconductor Semiconductor Xiao Yi identified the heart after the manufacturing process: measurement-characteristics in the daytime; and the complex number of residual copper on the X device uses the measured complex number as the feedback value system. A process control system was obtained 6 1 9 · — A way, It includes the following steps: According to the design of one of the auxiliary models of the pattern, the measurement plan is set to measure one 200405184 62 3. Equipment includes electricity 624. Equipment includes the same as 62 5. Including feedback system 62 6. Quality and plurality. 62 7 · Position system to 62 8 · Process including the department = the method described in the scope of patent application No. 62, wherein the device is a probe device. = The method described in item 62 of the scope of patent application, wherein the device is in situ or in-Hne. κA asks for the method described in item 624 of the patent scope, which also includes the control of Bao Cheng. A method including using a plurality of test structures and a plurality of reference material pattern auxiliary models to connect the cutting line measurement with the plurality of wafers, and the method described in item 5 of the patent application, wherein the v are online, in the same room, or offline One of the states is measured. The method as described in the scope of application for patent No. 563, wherein the component trench process flow. l〇57-5667-PF (Nl) .ptd Page 346 200405184 VI. Application for Patent Range 62 9 · If requested, the scope of patent No. 563 includes the method of importing multiple low dielectric constant materials to ~~, of which 63 0 · As in the patent application No. 563 ~ trench process flow. The process includes a method of introducing a plurality of low dielectric constant interlayer dielectrics, wherein the trench process flow. Said (1 LI)) material to ^ 631. The process of applying for patent No. 563 includes the use of dummy filling to improve the low-dielectric constant of the method: the method of the system) structural properties. Intermediate dielectric layer (I LD 63 2. Sexual impact analysis as described in the scope of patent application No. 564 includes evaluation of effective dielectric constant. Method, where the electricity 63 3. The method described in scope of patent application No. 563 The position is selected to characterize a plasma etcher among them. &Gt;, of the plural pattern attached 63 4. The position is selected to characterize a lithography or Plural number of tools ^ 'Among them 6 3 5 · As shown in the method described in the scope of patent application No. 563, the drawings are attached. The position is selected to characterize a chemical mechanical polishing process in which the 1C patterns are attached. Plurality of tools 63 6 · As described in the method of patent application No. 563, the position a is selected to characterize the formation of a plurality of interconnected structures /, etc. Set 1C pattern 6 3 7 ·-One method , Including the following steps: Select a plurality of positions to measure one of the semiconductor devices that have been produced; measure these positions; '1057-5667-PF (Nl) .ptd page 347 200405184 6. Apply for a patent if the amount of the position Tests show that the device does not meet If required, remove the device; select other plural locations to measure the semiconductor device; measure the other locations; and if the measurements at the other locations show that the device does not meet a requirement, remove the device. 6 3 8 The method as described in item 6 37 of the scope of patent application, which also includes repeating the selection, measurement and removal steps. 6 3 9. The method as described in item 6 37 of scope of patent application, wherein the amount The measurement system is executed online corresponding to a process step. 6 4 0. The method described in item 637 of the scope of patent application, wherein the measurement system is executed in the same room corresponding to a process step. 6 41. As the scope of patent application area 637 The method described above, wherein the measurement is performed offline corresponding to a process step. 64 2. The method according to item 637 of the scope of patent application, wherein the selection is performed using a software tool. 64 3. As a patent application The method described in item 637 of the scope, wherein the selection is attached according to a pattern corresponding to one of the processes of the device. 6 4 4. The method described in item 643 of the scope of patent application, wherein the model is corresponding to the method A specific tool is used for measurement. 6 4 5. The method according to item 643 of the scope of patent application, wherein the model incorporates the variation of the process throughout, and the selection is based on the model when the measurement has been performed. 6 4 6. The method as described in claim 563 of the patent application scope, wherein 1057-5667-PF (Nl) .ptd Page 348 200405184 6. Scope of Patent Application The position is selected at a crystal level. 64 7 · The method as described in item 563 of the patent application scope, wherein the positions are selected at a wafer level 648 · —a method including selecting a plurality of positions for measurement on a device 'the device uses at least one Production process and production, the process includes removing material from a surface of the device, wherein the positions selected according to a pattern auxiliary model of the process will be tested regardless of whether the removal falls within an acceptable tolerance . 64 9 · The method according to the scope of patent application No. 648, wherein the process includes grinding 'and the acceptable tolerance includes the removal treatment without excessive grinding> 65 0 · The method according to the scope of patent application No. 563, which also includes Control a tool to correspond to the selection. I. 2 丨. The method according to the scope of patent application No. 650, wherein the tool includes an optical reflection device, a CD, a contouring tool, a sound field or an eddy current 65. The method according to the scope of patent application No. 563, wherein It also includes the use of these measurements of the owner w μ to characterize the overall Japanese wafer or wafer level yield. Where: The method described in the scope of application for patent No. 563, where the loss b is the maximum or minimum characteristic of the complex design specification of the device, and the method of the patent scope No. 648 of Shishen π is also selected. Including feedback to adjust the multiple settings or formula parameters of a chemical machine, only M ^ ^ τ bottle grinding tools. The method of Jingye Sanlei ^ Qing patent scope No. 648, which also includes the feedback ^ ... chemical mechanical deposition tool or contains an electro chemical mechanical sink 1057-5667-PF (Nl) .ptd Page 349 200405184 VI. Scope of Patent Application Plural settings or recipe parameters of one of the tools of the product tool. 6 5 6 · If the method of applying for the scope of patent 6 4.8, which also includes feedback to adjust the complex differential pressure of a chemical mechanical polishing head 〇65 7 · If the method of applying for the scope of patent 648, which also Include feedback to adjust multiple recipe parameters for a process step. 65 8. If the method of applying for the scope of the patent No. 648, it also includes feedback to adjust the parameters of the complex synthesis formula of a manufacturing process. 6 5 9 · Method according to patent application No. 5 63, which also includes comparison and selection processing from the best known plural process method and plural consumables. 66 0. The method according to the scope of application for patent No. 5 63, which also includes feedback to adjust a plurality of settings or formulation parameters of a plasma etching process tool or a process including a plasma etching process tool. 6 6 1 · A method comprising measuring a semiconductor device according to a measurement day ', the measurement day is based on an attached model of a plasma etching pattern to confirm a complex critical dimension (CD) of a plurality of ic elements. 66 2. The method according to item 5 63 of the patent application scope, wherein the plurality of wafer state parameters generated by the pattern auxiliary model corresponding to the plurality of pattern auxiliary features include at least one of the following: critical dimension (CD), film thickness, height Aspect ratio, or trench width, or trench depth. 66 3. If the method of applying for patent scope No. 563, it also includes feedback to adjust a lithography tool or a plurality of settings or formula parameters of a lithography tool. 1057-5667-PF (Nl) .ptd Page 350 200405184 6. Application for Patent Scope 6 6 4 · The method of applying for Patent Scope 5 6 3, which also includes adjusting plural design rules, plural design specifications, or plural control bands . 66 5. If the method of applying for the scope of the patent No. 563, also includes a plurality of test structures or the design of the arrangement. 6 6 6 · The method according to the scope of patent application No. 563, which also includes a plurality of test structures and devices that combine a plurality of wafer parameters with the existence. 667. A device including a tool for measuring a parameter of a semiconductor device, the measuring tool including a control element for selecting a plurality of positions, and measuring according to a pattern auxiliary model corresponding to a process of the device. 6 6 8 · A method including using a pattern auxiliary model to determine a manufacturing recipe and a plurality of device settings for a process of manufacturing an integrated circuit (1C), the manufacturing recipe and the device settings reducing a plurality of wafer state parameters or Electrical processes introduce variation. 66 9. The method according to item 668 of the scope of patent application, wherein the wafer state parameters include at least one film thickness of the overall production. 67 0. The method described in the scope of application for patent No. 668, which also includes using a plurality of test wafers to characterize one of the wound patterns attached to the integrated circuit production process, and use these in the model Graphic attached. 671. The method according to item 67 of the scope of patent application, wherein a part of the production process includes an electroplating process. 67 2. The method according to item 67 of the scope of patent application, wherein part of the production process includes oxidative deposition. 67 3. The method according to item 67 of the scope of patent application, wherein part of the production process includes chemical mechanical grinding. Raw 200405184 VI. Scope of patent application 674 · As described in item 670 of the scope of patent application, where part of the production process includes plasma etching. 675. The part of the direct production process as described in item 670 of the scope of patent application includes lithography. 4. Method U 67 6. The method described in the patent scope No. 668, 669, 67, 67, 67, 672, 673, 6 74 or 675, wherein the model's plural pattern auxiliary features correspond to the plural numbers imported by the process. Variation of wafer state parameters. 67 7. According to the method described in the scope of patent application No. 676, the wafer state parameters of Zhizhong include at least one of the following examples: film thickness, array height, step height, film resistance, capacitance, crosstalk noise, and Coupling capacitor. 678. The method according to item 676 of the scope of application for a patent, wherein the pattern attached special features include at least one of the following: line spacing, line width, and effective density. 679. The method described in the scope of patent application No. 668, which also includes the use of the model to generate the complex crystal prediction and complex electrical parameters of the wafer state. 680. The method described in the scope of patent application No. 668 or 6-9, which also includes the use of a cost function to measure the plural results of these predictions. 681 "The method described in item 68 of the scope of patent application, which also includes the use of the cost function to set a finer order than the age, Q 0 ^ ^ formula or complex equipment to set 0 682. Such as the scope of patent application 68 The method described in item 〇 also includes the use of multiple optimization methods to select recipes and multiple equipment settings, which can minimize the variation of multiple wafer states or electrical parameters. 68 3. The method described in item 682 of the scope of patent application, wherein 200405184 VI. Method for optimizing the scope of patent application including tempering (anneal formula and approximation line 68 4) Such as the convergence of using the cost function method 6 8 5. Applying a single process step 6 8 6 · If applying greater than one Item process 68 7. If the claim is transmitted to a 6 8 8 via a graphic backup setting • If the claim is directly transmitted to the system. 6 8 9. If the claim is directly transmitted to a specific batch of 69 0 • If the claim is used The number of the pattern as a 6 9 1 · Use the pattern as stated 1057-5667-PF (Nl) .Ptd page 353 includes the following items to J / Single, single, combined gradient, 1 ng of simulation), dynamic program, approximate dynamic program, linear program. Please refer to the method described in item 683 of the patent, which also includes the number of quadratic (qUaclratic) to promote these convergences. The method described in the above method includes the method described in Patent Scope 668, +, _ x. ^ ^ ^ ^ ^ 呗, which includes steps or process flow. Please refer to the method described in the scope of patent No. 668, χ ,. Bei, which is also a user. Rong Xi Group's manufacturing formula and plural patents please apply for patent scope No. 668, +, 丄 ^ At least-manufacturing recipes to 1 pass and 'which also includes 1¾ tools or a production automatic patent scope No. 668, +, _丄 At least-manufacturing recipes to the method according to the pounds, which also includes one of the wafers memory device. 1. A wafer tool or the alleged patent scope No. 668. A method for predicting or rooting the attached model, which also includes a single process step. For the results of one or more electrical procedures, please refer to the patent scope. 668 offices. The auxiliary model uses the method of prediction or root ^, which also includes, suspected or complex electrical parameters 200405184 The number 9 is the result of multiple, process steps or one M process flow. To develop the model using the method described in item 668 of the patent scope, which also includes 1M wafers of inter-products to develop the model, which will make the plural Ht moxibustion signs correspond to at least one process. Variation of complex state parameters or electrical parameters. m The method according to item 692 of the scope of patent application, wherein these =: characteristics include at least one of the following: line spacing, line $, and effective bifurcation. 69 4. As the method described in the scope of patent application No. 692, these parameters in beans include at least one of the following examples: film thickness, array height, 69 5. The method described in scope of patent application No. 692, where The wafer status parameters include at least one of the following examples: thin film resistors, capacitors, noise, and coupling capacitors. 69 6. The method described in item 692 of the scope of patent application, which also includes ensuring the manufacturing capacity of the 1 (^ design) before placing an order (tape ut) on the photomask and manufacturing. 69 7 The method described in item 68, which also includes tape out and simulation of the manufacturing capability of the design before manufacturing. 6 9 8 · The method described in item 68 of the scope of patent application, It also includes determining a process flow in a plurality of pre-selected items of 1C design. 69 9 · The method described in item 6 of the scope of patent application 68, which also includes changing the parameters of a plurality of formulations in an IC manufacturing process to characterize the plurality pattern 1057-5667-PF (Nl) .ptd Page 354 200405184 6. Scope of Patent Application Attached. 7 0 0 • If the process trend is included in the process (dr 701. If the process trend includes a pad. 70 2. If the application is soft on the medium 70 3. If the request provides a pattern 70 4. If applied to process synthesis, 7 0 5. If applied to process optimization 7 0 6 · If applied to a web server 7 0 7. As in China and France, which also includes a customized network 7 〇 8 · as The process of claiming-the patent scope across a crystal party-a life cycle if t) 〇 patent scope plasma reactor faults patent scope implementation. Please patent the scope of the user interface Please patent the scope and apply the patent scope on a network, and implement the patent scope on a network. Please include the scope of patents corresponding to different services. Please manufacture the method described in item 699 after the patent process steps or plural, and execute the formula to characterize the method described in item 700 when the plural points are included in the distribution. Established ⑽ The method described in item 668, which is the method described in item 668, which is also covered so that a user can obtain the result. The method according to item 668, wherein the method is performed on a server. The method described in item 6 68 is implemented on the server. The method described in item 6 68 is a method in which the user described in item 704, 70 5 or 706 is used to generate the method described in item 6 68 on the web server, wherein In the multiple process steps, defects are identified spatially (pos t-manufactured 1057-5667-PF (Nl) .ptd Page 355 200405184 VI. Application for Patent Scope 7 0 9 · If you apply for dedicated servo force prediction, apply for dedicated servo process, you can apply for one, the method described in scope 668 , Which also includes receiving the method described in item 1 of the 0C = 0 range of the 1C using a specific process or tool, which also includes: automatically providing a process tool or plural processes with selected recipes or plural settings. The method described in item 668 of the profit range, which also mentions that the "罔 路 server corresponds to one click to obtain a method of item 668 in the best profit range, and the web server corresponds to a single order. Achieved a best 713. As described in item 668 of the scope of the patent application, the number of process hours or the number of processes has been specialized, and the process has been switched (sh ift.) The maintenance and repair work of the schedule and multiple process tools described in the scope of the patent No. 668. 彳 ,,, and also include 715 · Select the multiple consumables group described in the scope of the patent application No. 668. Which also includes 716 · such as The expendable consumable group described in the scope of application for patent No. 668 includes a plurality of polishing pads, a plurality of polishing liquids, and / or the like. Special rolling composite production can be supplied through a netting process, including supply and encapsulation. 71 0 · If using a net or step 71 1 · As a user 71 2 · If applying for a special user, you can start from a 71 7. A method including the following steps: Analysis of the electrical effects of the manufacturing process according to one or more steps and 200405184 6. Scope of patent application-a pattern attached model, generating a strategy to compare multiple consumable groups Or equipment; and Λ use the electrical impact analysis and the pattern accessory model to evaluate the expected results of the multiple integrated circuit design using a selected set of such consumables or equipment. / 71 8 · The method according to item 71 of the scope of patent application, wherein the consumable groups include a plurality of grinding mills, a plurality of grinding liquids, or a plurality of gases. 719. The method according to item 717 of the scope of patent application, wherein the equipment includes CMP, ECD, plasma etching, lithography, or deposition equipment. 7 2 0 · A method including the following steps: &amp; Electrical impact analysis of a manufacturing process release and a pattern attachment model according to one or more steps to generate a strategy to analyze or diagnose a plurality of consumable groups or equipment; And use the electrical impact analysis and the pattern attachment molding to evaluate the expected results of the multiple integrated circuit design using a selected set of such consumables or equipment. 721. The method according to item 720 of the scope of patent application, wherein the consumable groups include a plurality of abrasives, a plurality of abrasives, or a plurality of gases. 72 2. The method according to item 72 of the scope of patent application, wherein the equipment includes CMP, ECD, plasma etching, lithography, or deposition equipment. f 7 2 3 · A method including the following steps: Based on one or more steps of an electrical impact analysis of the manufacturing process and a pattern attachment model, a prediction of one of the plurality of isolated trench geometries is generated. 72 4. The method according to item 723 of the scope of patent application, wherein the system 1057-5667-PF (Nl) .ptd Page 357 ~ --- 200405184 6. Scope of Patent Application The process includes CMP. 7 2 5 · If the application process includes plasma erosion 7 2 6 · If you apply for specialization to characterize the plural specific aspect ratio of the plural 7 2 7 · If you apply for the establishment of one for analysis 7 2 8 · If you apply for the application Including compiling about tools or 7 2 9 · If applying for creating tools or designing 7 3 0 · If applying for providing providing via a network 7 3 1 · If applying for including also predicting an active groove fillet (runding 7 3 2 · If applying for the prediction of an active device voltage (thresho 1 d 7 3 3 · If applying for the prediction of an active device flow exclusively. 7 3 4 · If the application also includes the method described in item 723, The method described in item 676 includes the method described in item 676, which also includes a diagnostic tool or a control tool. The method library described in item 6 and 76 is included in the method. The method described in item 676 is included in the method. , Which also includes the aggregate statistics of consumption behavior. The method described in item 6 76 of the scope of interest, which also includes a plurality of standards. The method described in item 6 7 6 of scope, which also includes the data. 723 area of interest Or the method described in item 724, wherein Device interface and an isolation trench interval interface interface). The method described in item 7 2 5 of the scope of interest, which also includes ^ and "Isolation trench interface interface threshold voltage" ° profit The method according to item 7 2 3 of Qianwei, wherein the method described in item 723, which is one of the leakage benefit ranges of an interface between an isolation zone and an isolation trench section, also includes 1057-5667-PF (Nl) .ptd p.358 200405184 == Motion 丨 device〗 region and an isolation trench section of the -Interface polycrystalline stone, vertical ,, and τ3 structure (polysilicon stringer) 73 5. The method described in item 723 of the scope of patent application, straight and also Including the process of defining multiple or isolating structures to form a complex or multiple process. 0 6. 6. The method as described in item 735 of the scope of patent application, which also includes selecting a specific shallow trench isolation design. 737. The method as described in claim 723 of the scope of patent application, which also includes selecting a design or a plurality of process features to affect the rounded condition of the groove corners. H 7 3 8. A method comprising the following steps: According to the electrical impact analysis of a trench isolation manufacturing process and one of the pattern attachment models in one or more steps, a strategy is generated to configure a plurality of dummy fills in the process Oxidation zone; and using the electrical impact analysis and the pattern auxiliary model to evaluate the expected results using the dummy fill configuration, the electrical impact analysis and use of the pattern auxiliary model are included in the generation of the dummy fill Part of it. 73 9. The method described in item 79, 80, 81, or 82 of the scope of patent application, further comprising: generating the strategy based on the configuration of the dummy filling in the production process according to the pattern auxiliary model generation; and using a cost function ( c 〇stfuncti 〇η) Evaluate the impact caused by the dummy filling adjustment during the wafer stage process and electrical parameter variation 1057-5667-PF (Nl) .ptd Page 359