TWI728576B - Manufacturing method of semiconductor structure and computer-readable storage medium - Google Patents

Abstract

A manufacturing method of semiconductor structure is provided. The manufacturing method includes following operations. A predetermined process parameter is obtained. The semiconductor structure is divided into a plurality of units. A first parameter is distributed to a portion of the units and a second parameter is distributed to another portion of the units. A first simulation event and a second simulation event are obtained respectively. A process simulation is performed. The process simulation performs the first simulation event to the units having the first parameter and performs the second simulation event to the units having the second parameter. The predetermined process parameter is adjusted according to a simulation result. A process of the semiconductor structure is performed.

Description

Manufacturing method of semiconductor structure and computer readable recording medium

The present disclosure relates to a manufacturing method, in particular to a manufacturing method of a semiconductor structure and a computer readable recording medium.

A wafer fabrication plant can use multiple processing operations to manufacture or complete semiconductor wafers. Such processing operations and related manufacturing tools may involve deposition, polishing, grinding, thermal oxidation, diffusion, ion implantation, epitaxy, etching, and lithography techniques. In each operation, measurement tools may be used to monitor the quality and yield of products (such as semiconductor wafers).

The embodiment of the present disclosure discloses a method for manufacturing a semiconductor structure, including: obtaining preset process parameters of the semiconductor structure; dividing the semiconductor structure into a plurality of units; allocating a first parameter to a part of the units, and allocating a second parameter In the other part of the units; obtain the first simulation event and the second simulation event respectively; perform process simulation, which is performed for the units with the first parameter, the first simulation event, and for the units with the first parameter The units of the second parameter perform the second simulation event; adjust the preset process parameters according to the simulation result; and perform the manufacturing process of the semiconductor structure.

Another embodiment of the present disclosure discloses a method for manufacturing a semiconductor structure, including: performing a process of the semiconductor structure according to preset process parameters; obtaining process parameters; dividing the semiconductor structure into a plurality of units; and assigning a first parameter to the semiconductor structure. Equal part of the unit and assign the second parameter to the other part of the unit; obtain the first simulation event and the second simulation event respectively according to the process parameter; perform the process simulation, the process simulation is for the first parameter The units perform the first simulation event, and for the units with the second parameter, perform the second simulation event; obtain simulation results; and adjust the preset process parameters according to the simulation results.

Another embodiment of the present disclosure discloses a computer-readable recording medium that stores at least one program. After the computer loads and executes the program, a simulation method of a semiconductor manufacturing process can be completed. The simulation method includes: obtaining a semiconductor structure preview Set the process parameters; divide the semiconductor structure into a plurality of units; assign the first parameter to one part of the units, and assign the second parameter to the other part of the units; obtain the first simulation according to the preset process parameters Event and second simulation event; process simulation is performed for the units with the first parameter, the first simulation event is performed, and for the units with the second parameter, the second simulation is performed Events; and obtain simulation results.

The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and configurations are described below to simplify the disclosure. These are only examples and are not intended to be limiting. For example, in the following description, a first member formed on or on a second member may include an embodiment in which the first member and the second member are formed in direct contact, and may also include an additional member formed on the first member. An embodiment in which the first member and the second member may not be in direct contact between the member and the second member. In addition, the present disclosure may repeat element symbols and/or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself specify one of the relationships between the various embodiments and/or configurations discussed.

The embodiments of the present disclosure are discussed in detail below. However, it should be understood that the present disclosure provides many applicable inventive concepts that can be embodied in a variety of specific background content. The specific embodiments discussed are only illustrative and do not limit the scope of this disclosure.

In addition, for ease of description, spatially relative terms (such as "bottom", "below", "below", "above", "up", "below", "left", "right" and the like can be used in this text ) To describe the relationship between one element or component and another element or component(s), as shown in the figure. In addition to the orientations depicted in the figures, spatially relative terms are also intended to cover different orientations of the device in use or operation. The device can be oriented in other ways (rotated by 90 degrees or in other orientations), and therefore the spatial relative descriptors used in this article can also be interpreted. It will be understood that when an element is referred to as being “connected to” or “coupled to” another element, it can be directly connected or coupled to the other element, or intervening elements may be present.

The manufacturing method of the semiconductor device may include multiple operations. These operations and related manufacturing tools or equipment may involve deposition, polishing, grinding, thermal oxidation, diffusion, ion implantation, epitaxy, etching and lithography techniques. In various technology-related operations, structural parameters may deviate due to different conditions. For example, during deposition, epitaxy, or etching processes, random deviations of structures (for example, shapes) may occur due to material properties, process conditions, or other factors.

The present disclosure provides a method for manufacturing a semiconductor structure to solve the above-mentioned problems. The semiconductor structure manufacturing method of the present disclosure can divide the semiconductor structure into a plurality of units, and assign different or the same parameters to each unit, corresponding to different parameters, and perform process simulation on each unit with different simulation events. Based on the simulation results, the shape of the semiconductor structure can be predicted, so that the process parameters can be adjusted and corrected to alleviate the problem of deviation of parameters (such as geometric parameters (shape)).

FIG. 1 is a flowchart illustrating a manufacturing method 100 of a semiconductor structure in some embodiments according to the present disclosure.

Referring to FIG. 1, in some embodiments, a method 100 for manufacturing a semiconductor structure includes operation 102, operation 104, operation 106, operation 108, operation 110, operation 112, and operation 114.

FIG. 2A is a top view illustrating a certain stage of the semiconductor structure 200 according to the present disclosure in some embodiments. The semiconductor structure 200 may include, but is not limited to, for example, a silicon substrate. In the example of a silicon substrate, the semiconductor structure 200 may further include other semiconductor materials, such as silicon germanium, silicon carbide, or gallium arsenide. In this embodiment, the semiconductor structure 200 includes a silicon p-type semiconductor substrate (P-substrate) or an n-type semiconductor substrate (N-substrate). Alternatively, the semiconductor structure 200 includes another elemental semiconductor, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; alloy semiconductors, It includes SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or a combination thereof. In other alternative embodiments, the semiconductor structure 200 may include a doped epitaxial layer, a graded semiconductor layer, and/or a semiconductor layer above another semiconductor layer of a different kind, such as a silicon layer on a silicon germanium layer.

FIG. 2B is a schematic cross-sectional view of the semiconductor structure 200 shown in FIG. 2A in a dashed box along the line A-A. Please refer to FIGS. 1, 2A, and 2B. In operation 102, the preset process parameters of the semiconductor structure 200 can be obtained. In the semiconductor structure 200, for example, but not limited to, a semiconductor material may form the reaction surface 204. The semiconductor material may include, for example, a crystalline phase material that is grown to increase in the semiconductor structure 200 during an epitaxial process or a thin film deposition process, or a semiconductor material that is etched during an etching process of the semiconductor structure 200. In some embodiments, the semiconductor material may include, for example, silicon, germanium, or other materials with matching lattice structure. In some embodiments, the reactive surface 204 may be formed of molecules 202 of semiconductor material. It is worth mentioning that the reaction surface 204 can be formed using atoms, lattice units or other basic units for reaction.

In some embodiments, a computer or a server can be used to perform part or all of the operations of the method shown in FIG. 1. For example, but not limited to, a simulator can be used to perform part or all of the operations of the method shown in FIG. 1. Multiple simulation methods can be applied to perform part or all of the operations of the method shown in FIG. 1. For example, but not limited to, the Lattice Kinetic Monte Carlo mode can be used. In this mode, the molecules 202 on the reaction surface 204 of the semiconductor structure 200 may be displayed in a spherical manner.

In some embodiments, the processes that can be simulated include, but are not limited to, an epitaxial process, a thin film deposition process, and an etching process. Therefore, the preset process parameters of the semiconductor structure 200 include, but are not limited to, preset process parameters such as deposition, epitaxy, or etching. For example, preset parameters such as the growth rate of the deposition process, the growth rate of the epitaxial process, the gas concentration of the epitaxial process, and the etching rate of the etching process.

3 is a schematic top view illustrating the reaction surface 204 of FIG. 2B of the semiconductor structure 200 according to the present disclosure in some embodiments. 1 and 3, in operation 104, the semiconductor structure 200 is divided into a plurality of units 2021. In some embodiments, the units 2021 are distinguished by, for example, the molecule 202 shown in FIG. 2B as a unit. In some other embodiments, the units 2021 can also be distinguished by atoms, lattice units or other basic units for reaction, which are not intended to limit the present disclosure.

4 is a schematic top view illustrating the reaction surface 204 of FIG. 3 of the semiconductor structure 200 according to the present disclosure in some embodiments. 1 and 4, in operation 106, parameter 1 is allocated to a part of the units 2021, parameter 2 is allocated to a part of the units 2021, parameter 3 is allocated to a part of the units 2021, and allocated Parameter 4 is in another part of these units 2021. It is worth mentioning that, in this embodiment, parameter 1, parameter 2, parameter 3, and parameter 4 are taken as examples for description, but it is not restrictive. In some embodiments, more or fewer parameters can also be included.

The parameter assignment can be achieved by, for example, but not limited to, information assignment for different positions of the reaction surface 204 of the semiconductor structure 200 or assigning attributes related to the parameter.

It should be noted that the number of parameters is related to the simulated events of the semiconductor structure and can be set by the user. For example, if the number of subsystems including the parameter is K, the selection of the parameter i is 1≦i≦K. That is, the parameters allocated to the units 2021 can be 1, 2...K. In some embodiments, the number of parameters may correspond to the number of groups for simultaneous calculation (parallel operation) preset by the user. For example, the unit 2021 is preset to be divided into 4 groups for parallel operation, then the parameter The number of is 4, and it is preset that the units 2021 are divided into K groups for parallel operation, and the number of parameters is K, which is non-limiting. Furthermore, the allocation of parameters can be uniformly generated from the parameter set of all sub-systems through the uniform random number generation (Random Number Generating, RNG) equation.

On the other hand, since the number of parameters is related to the number of simulation events, if the number of parameters is small (that is, K is small), the simulation events assigned to each parameter are more. If the number of parameters is large (that is, K is larger), the simulated events assigned to each parameter are less, which will be explained below.

In operation 108, the first simulation event and the second simulation event are obtained respectively. The first simulation event and the second simulation event respectively include, for example, one of a plurality of simulation events that may occur. The first simulation event and the second simulation event may include, for example, an atomic adsorption event, a surface passivation event, or an atomic desorption event, which is not limited.

It should be noted that the acquisition of the first simulation event and the second simulation event is determined by probability, for example. For example, each simulation event that may occur has its own probability of occurrence. Therefore, when obtaining a simulation event that may occur, a simulation event with a high probability of occurrence may be first obtained as the first simulation event or the second simulation event. In some embodiments, the probability of a simulated event can be calculated by the following formula, which is not limiting.

為反應物之反應之活化壁障(activation barrier)，k為波茲曼常數，T為溫度。 p is a parameter related to reaction gas pressure, molecular mass or viscosity coefficient, etc.,

It is the activation barrier of the reaction of the reactant, k is the Boltzmann constant, and T is the temperature.

In some embodiments, the acquisition of the first simulation event and the second simulation event can be performed at the same time. In other words, it is possible to simultaneously calculate the occurrence probability of possible simulation events, and obtain the first simulation event and the second simulation event. In addition, this embodiment takes the first simulation event and the second simulation event as examples for description, but it is not restrictive. In some embodiments, more or fewer simulated events may also be included.

In operation 110, a process simulation is performed. In the process simulation, the first simulation event is performed for the units 2021 with parameter 1, and the second simulation event is performed for the units 2021 with parameter 2. In some embodiments, the third simulation event is performed for the units 2021 with the parameter 3, and the fourth simulation event is performed for the units 2021 with the parameter 4. In some embodiments, the simulated events are different simulated events. Furthermore, as mentioned above, the number of parameters is related to the number of simulation events. If the number of parameters is small (that is, there are fewer parallel operation groups) and there are more simulation events assigned to each parameter, the number of simulation events in each unit 2021 There are more simulation events allocated, so the calculation time may be longer, but because there are more simulation events that can be selected, the accuracy of the process simulation can be increased. On the other hand, if the number of parameters is large (that is, there are more groups of parallel operations) and the simulated events allocated to each parameter are less, since each unit 2021 allocates fewer simulated events, the calculation time may be longer. Short, but because there are fewer simulation events that can be selected, the accuracy of the process simulation may decrease (that is, the system is distorted). It should be noted that the number of parameters is related to the number of simulation events to be performed, but the accuracy of the process simulation is not the only consideration based on the number of parameters. For example, you can also consider adjusting the probability of occurrence of different simulated events based on their importance.

In some embodiments, before the process simulation is performed, it can be determined whether there is a conflict event in the process simulation. The conflict event includes, for example, that the distance between one of the units 2021 performing the first simulation event and one of the units 2021 performing the second simulation event is a certain distance. The specific distance is, for example, 0 or more and 10 times or less of the minimum distance between the units 2021, which is non-limiting. The specific distance of 0, for example, means that the two units 2021 are connected to each other. The minimum distance between the units 2021, for example, means that although the two units 2021 are not connected, they are adjacent to each other within the reaction influence range.

In some embodiments, if it is determined that the process simulation is a conflict event, the first simulation event or the second simulation event of one of the units 2021 located within a certain distance is cancelled. In other words, if the first simulation event and the second simulation event cannot be performed at the same time within a certain distance or will cause an error, cancel one of the first simulation event or the second simulation event, and select a new simulation event to replace it. The first simulation event or the second simulation event that was cancelled.

In some embodiments, the process simulation can simultaneously perform the first simulation event, the second simulation event, the third simulation event, and the fourth simulation for the units 2021 with parameter 1, parameter 2, parameter 3, and parameter 4, respectively. event.

FIG. 5 is a cross-sectional schematic diagram illustrating a certain stage of the semiconductor structure 200 according to the present disclosure in some embodiments along the line A-A of FIG. 2A. In some embodiments, after process simulation, after various simulation events are performed on the units 2021 as shown in FIG. 4, the intermediate simulation result of the semiconductor structure 200 after a preset simulation time can be obtained. The preset simulation time can be set by the user and is not restrictive. As shown in FIG. 5, the intermediate simulation result is, for example, that new molecules 206 are formed on the semiconductor structure 200 to form a new reaction surface 208.

In some embodiments, the probability of occurrence of the first simulation event and the second simulation event can be corrected respectively according to the intermediate simulation results. In some embodiments, the correction of the probability of occurrence of the simulated event can be carried out at the same time. For example, in the case of a new reaction surface 208, a new simulated event may be generated between the molecule 202 and the molecule 206, or the probability of occurrence of the simulated event of the molecule 202 may also need to be adjusted and corrected due to the molecule 206. In other words, if the semiconductor structure 200 of the intermediate simulation result is different from the expected result or the actual result, the occurrence probability of the first simulation event and the second simulation event can be adjusted, for example, the first simulation event or the second simulation event can be adjusted up or down. Probability of occurrence. Furthermore, the first simulation event and the second simulation event are determined by the probability of each possible simulation event. Therefore, according to the simulation results, the simulation obtained as the first simulation event or the second simulation event can be corrected. The probability of occurrence of the event, so that the type of simulated event is more in line with the requirements.

In some embodiments, based on the corrected occurrence probability of the first simulation event and the second simulation event, the process simulation for the next preset simulation time can be performed. That is, as the semiconductor structure 200 changes during the manufacturing process (for example, from the reaction surface 204 to the reaction surface 208), the probability of occurrence of different simulation events will also change. Therefore, operation 108 and operation 110 are performed again until the preset condition for ending (for example, the preset number of simulations or the preset end time, etc.) is met to obtain the simulation result.

Referring to FIG. 1, in operation 112, the preset process parameters are adjusted according to the simulation result. In some embodiments, if the simulation result of the semiconductor structure 200 is different from the expected result or the actual result, the preset process parameters can be adjusted to make the actual process result more in line with the requirements.

In operation 114, the manufacturing process of the semiconductor structure is performed. In some embodiments, the actual semiconductor structure manufacturing process can be performed according to the adjusted preset process parameters, such as, but not limited to, an epitaxial process, a thin film deposition process, and an etching process.

For example, in some embodiments, when the source/drain regions are formed in the semiconductor structure, the source/drain regions can be grown through a selective epitaxial process. The source or drain material may include, for example, but not limited to, silicon, silicon germanium, or other suitable materials (for example, a material with a different lattice constant from the channel region). The epitaxial growth process can use precursors, such as but not limited to silane, dichlorosilane, germane, or the like.

Therefore, with the manufacturing method of the semiconductor structure of the present disclosure, the source/drain electrode to be grown can be divided into multiple units, and different or the same parameters can be assigned to each unit, corresponding to different parameters, and different simulation events can be performed on each unit. Process simulation. Based on the simulation results, the shape of the source/drain regions can be predicted, so that the process parameters (such as growth time, etc.) can be adjusted and corrected to alleviate the problem of shape deviation of the parameters (such as geometric parameters (shape)).

Moreover, in some embodiments, for example, in a chemical vapor deposition process, a variety of gases are mixed before the gas enters the reactor to cause a chemical reaction in the reactor and for the purpose of the reaction to deposit solid materials on the substrate. . Or, in some embodiments, such as in physical vapor deposition, plasma sputtering bombardment is used, and atoms or molecules are ejected from the target material by high-energy particle bombardment, so that the ejected atoms or molecules can be It condenses on the substrate and becomes a thin film. Alternatively, in some embodiments, for example, when atomic layer deposition is a gas phase chemical process, a surface-controlled growth mechanism is used to provide a dense film with few (or no) pores.

Similarly, with the semiconductor structure manufacturing method of the present disclosure, the site to be deposited on the substrate can be divided into multiple units, and different or the same parameters can be assigned to each unit, corresponding to different parameters, and the process simulation can be performed on each unit with different simulation events. . With the simulation results, the shape of the place to be deposited can be predicted, so that the process parameters (such as material concentration, etc.) can be adjusted and corrected to alleviate the problem of the deviation of the parameters (such as geometric parameters (shape)).

Moreover, in some embodiments, for example, in the etching process, the semiconductor structure manufacturing method of the present disclosure can divide the area to be etched on the substrate into multiple units, and assign different or the same parameters to each unit, corresponding to different Parameter, process simulation for each unit with different simulation events. Based on the simulation results, the shape of the place to be etched can be predicted, so that the process parameters (such as etchant concentration, etc.) can be adjusted and corrected to alleviate the problem of shape deviation of the parameters (such as geometric parameters (shape)). The etching process may include a dry etching process, a wet etching process or other etching processes.

In summary, the semiconductor structure manufacturing method of the present disclosure can divide the semiconductor structure (such as the reaction surface) into multiple units, and assign different or the same parameters to each unit, corresponding to different parameters, and different simulation events for each unit Carry out process simulation. Based on the simulation results, the shape of the semiconductor structure can be predicted, so that the process parameters can be adjusted and corrected to alleviate the problem of the shape deviation of the parameters (such as geometric parameters (shape)).

Furthermore, the manufacturing method of the semiconductor structure of the present disclosure can simultaneously perform the following operations for a plurality of units on the reaction surface: obtaining a simulated event, performing a simulated event, and correcting the probability of occurrence of the simulated event. In this way, the time-consuming and computing resource requirements of process simulation can be reduced. In addition, in some embodiments, conflicting events at a specific distance can be cancelled, thereby reducing the buffer area between adjacent units. Because the simulation may overlap with each other and not calculate or repeat calculations, the simulation results may be generated. Errors and other issues.

FIG. 6 is a flowchart illustrating a method 600 of manufacturing a semiconductor structure in other embodiments according to the present disclosure. Referring to FIG. 6, in some embodiments, a method 600 for manufacturing a semiconductor structure includes operation 602, operation 604, operation 606, operation 608, operation 610, operation 612, operation 614, and operation 616.

In operation 602, the manufacturing process of the semiconductor structure is performed according to preset process parameters. In operation 604, process parameters are obtained. In operation 606, the semiconductor structure is divided into a plurality of units. In operation 608, the first parameter is allocated to one part of the units, and the second parameter is allocated to another part of the units. In operation 610, the first simulation event and the second simulation event are respectively obtained according to the process parameters. In operation 612, a process simulation is performed. The process simulation performs a first simulation event for the units with the first parameter, and performs a second simulation event for the units with the second parameter. In operation 614, a simulation result is obtained. In operation 616, the preset process parameters are adjusted according to the simulation result.

The difference between the manufacturing method 600 of FIG. 6 and the manufacturing method 100 of FIG. 1 is that the manufacturing method 600 first performs the process of the semiconductor structure according to the preset process parameters, and then obtains the process parameters of the semiconductor structure during or after the process, and then according to the actual Simulate the process parameters during or after the process. Among them, the simulation operation process has been described in detail in FIG. 2A, FIG. 2B, FIG. 3, FIG. 4, and FIG. 5, and will not be repeated here.

Therefore, the manufacturing method 600 can be simulated by the process parameters during or after the process, so that the preset process parameters can be adjusted and corrected according to the actual situation to alleviate the problem of the shape deviation of the parameters (such as geometric parameters (shape)).

In some embodiments of the present disclosure, a computer-readable recording medium can be used to store at least one program. After the computer loads and executes the program, the simulation method of the semiconductor manufacturing process can be completed. The above-mentioned simulation method is the same as the manufacturing method 100 and the manufacturing method 600 described in FIG. 1, FIG. 2A, FIG. 2B, FIG. 3, FIG. 4, FIG. 5, and FIG.

In some embodiments, providing a method for manufacturing a semiconductor structure includes: obtaining preset process parameters of the semiconductor structure; dividing the semiconductor structure into a plurality of units; assigning a first parameter to a part of the units, and assigning a second parameter In the other part of the units; obtain the first simulation event and the second simulation event respectively according to the preset process parameters; perform the process simulation, which performs the first simulation event for the units with the first parameters, and For the units with the second parameters, perform a second simulation event; obtain a simulation result; and according to the simulation result, perform a manufacturing process of the semiconductor structure.

In other embodiments, a method for manufacturing a semiconductor structure is provided, which includes: performing a process of the semiconductor structure according to preset process parameters; obtaining process parameters; dividing the semiconductor structure into a plurality of units; allocating the first parameter among the units Part of the unit, and assign the second parameter to the other part of the units; obtain the first simulation event and the second simulation event respectively according to the process parameters; perform the process simulation. The process simulation is performed for the units with the first parameter. A simulation event, and for the units with the second parameter, a second simulation event is performed; the simulation result is obtained; and the preset process parameters are adjusted according to the simulation result.

In some other embodiments, a computer-readable recording medium is provided that stores at least one program. After the computer loads and executes the program, a simulation method of a semiconductor manufacturing process can be completed. The simulation method includes: obtaining a preset manufacturing process of a semiconductor structure Parameters; divide the semiconductor structure into a plurality of units; assign the first parameter to one part of the units, and assign the second parameter to the other part of the units; obtain the first simulation event and the second simulation event respectively according to the preset process parameters Simulation event; process simulation, process simulation is performed for the units with the first parameter, perform the first simulation event, and for the units with the second parameter, perform the second simulation event; and obtain the simulation result.

The features of several embodiments are summarized above, so that those familiar with the art can better understand the aspect of the present disclosure. Those familiar with the art should understand that they can easily use the present disclosure as a basis for designing or modifying other programs and structures to implement the same purpose and/or achieve the same advantages of the embodiments described herein. Those familiar with the art should also realize that these equivalent structures do not depart from the spirit and scope of the present disclosure, and various changes, substitutions and alterations can be made in this text without departing from the spirit and scope of the present disclosure.

100, 600: Manufacturing method 102, 104, 106, 108, 110, 112, 114, 602, 604, 606, 608, 610, 612, 614, 616: Operation 200: semiconductor structure 202, 206: Molecule 204, 208: reaction surface 2021: unit

When reading in conjunction with the drawings, the aspect of this disclosure is best understood from the following [Embodiments]. It should be noted that according to standard practice in the industry, the various components are not drawn to scale. In fact, for the sake of clarity, the size of each component can be increased or decreased arbitrarily. FIG. 1 is a flowchart illustrating a method of manufacturing a semiconductor structure in some embodiments according to the present disclosure. FIG. 2A is a top view illustrating a certain stage of the semiconductor structure according to the present disclosure in some embodiments. 2B is a schematic cross-sectional view of the semiconductor structure shown in FIG. 2A in a dashed box along the line A-A. 3 is a schematic top view illustrating the reaction surface of FIG. 2B of the semiconductor structure according to the present disclosure in some embodiments. 4 is a schematic top view illustrating the reaction surface of FIG. 3 of the semiconductor structure according to the present disclosure in some embodiments. FIG. 5 is a cross-sectional schematic diagram illustrating a certain stage of the semiconductor structure according to the present disclosure in some embodiments along the line A-A in FIG. 2A. FIG. 6 is a flowchart illustrating a method of manufacturing a semiconductor structure in other embodiments according to the present disclosure.

100: manufacturing method

102, 104, 106, 108, 110, 112, 114: Operation

Claims (10)

A method for manufacturing a semiconductor structure, including: Obtain the preset process parameters of the semiconductor structure; Divide the semiconductor structure into a plurality of units; Allocate the first parameter to one part of the units, and allocate the second parameter to the other part of the units; Obtain the first simulation event and the second simulation event respectively; Performing a process simulation, the process simulation performing the first simulation event for the units with the first parameter, and performing the second simulation event for the units with the second parameter; According to the simulation results, adjust the preset process parameters; and Perform the manufacturing process of the semiconductor structure. Such as the manufacturing method of claim 1, further including: Determine whether there is a conflict event in the process simulation. Such as the manufacturing method of claim 2, wherein the conflict event includes a distance between one of the units performing the first simulation event and one of the units performing the second simulation event is a specific distance. For example, the manufacturing method of claim 3, wherein if the judgment is yes, cancel the first simulation event or the second simulation event of one of the units located within the specific distance. A method for manufacturing a semiconductor structure, including: Perform the manufacturing process of the semiconductor structure according to the preset process parameters; Obtain process parameters; Divide the semiconductor structure into a plurality of units; Allocate the first parameter to one part of the units, and allocate the second parameter to the other part of the units; According to the process parameters, the first simulation event and the second simulation event are obtained respectively; Performing a process simulation, the process simulation performing the first simulation event for the units with the first parameter, and performing the second simulation event for the units with the second parameter; Obtain simulation results; and According to the simulation result, the preset process parameters are adjusted. Such as the manufacturing method of claim 5, which further includes: Determine whether there is a conflict event in the process simulation. Such as the manufacturing method of claim 6, wherein the conflict event includes a distance between one of the units performing the first simulation event and one of the units performing the second simulation event is a specific distance. Such as the manufacturing method of claim 5, which further includes: According to the adjusted preset process parameters, the process of the semiconductor structure is performed. A computer can read a recording medium and store at least one program. When the computer loads and executes the program, a simulation method of a semiconductor manufacturing process can be completed. The simulation method includes: Obtain the preset process parameters of the semiconductor structure; Divide the semiconductor structure into a plurality of units; Allocate the first parameter to one part of the units, and allocate the second parameter to the other part of the units; Obtain the first simulation event and the second simulation event respectively; Performing a process simulation that performs the first simulation event for the units with the first parameter, and performs the second simulation event for the units with the second parameter; and Obtain simulation results. For example, the recording medium of claim 9 further includes: Determine whether there is a conflict event in the process simulation.

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