TW200403871A - Integrated metal-insulator-metal capacitor and metal gate transistor - Google Patents

Integrated metal-insulator-metal capacitor and metal gate transistor Download PDF

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TW200403871A
TW200403871A TW092117823A TW92117823A TW200403871A TW 200403871 A TW200403871 A TW 200403871A TW 092117823 A TW092117823 A TW 092117823A TW 92117823 A TW92117823 A TW 92117823A TW 200403871 A TW200403871 A TW 200403871A
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metal
gate
capacitor
integrated circuit
circuit structure
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TW092117823A
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TWI232002B (en
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Lawrence A Clevenger
Louis L Hsu
Kwong-Hon Wong
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Ibm
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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Description

200403871 玖、發明說明： 【發明所屬之技術領域】 本發明一般關於微電子電路，及更特別地關於一微電子 電路與具有金屬-絕緣層-金屬電容器的裝置。 【先前技術】 現今動態隨機存取記憶體（DRAM)環境最關心的是達到 高密度。當DRAM尺寸愈來愈大時，所關心的是其功能。 因此，增進DRAM功能是關键，特別對短週期、高速内埋 的DRAM。為了與技術具體化的靜態隨機存取記憶體 (SRAM)競爭，DRAM必需發生許多功能上的突破。一種該 突破是進一步縮小DRAM尺寸。一 DRAM巨觀尺寸小於相同 容量的SRAM約10至15倍。而且，尺寸愈小，延遲愈少。不 像傳統單獨的DRAM，可擦拭DRAM的尺寸（eDRAM)更難以 縮小，其增加製程成本。 一金屬-絕緣層-金屬（MIM)電容器通常在半導體中用做 一去藕合電容器。一 MIM電容器包括由導電材料如多晶矽 、金屬或金屬合金製造的一下或上電極。而且，在電極三 明治夾層中間是一薄介電層如氮化矽、氧氮化矽、氧化矽 或高k材料如氧化銘、五氧化纽、二氧化欽、鈇酸魏鋇等。 MIM電容器可以獨立元件被加入到一晶片，及通常被加 在終端金屬層。更進步的MIM電容器版本可以被積體化在 一晶片粒上，例如在各種線背端層之間，其中由於較近鄰 接觸到電晶體的矽層，其可以提供一更有效的去藕合功能 及具有引入外界雜訊的較小傾向。表示在美國專利 86245 - 200403871 5,903,493及美國專利6，198,617的兩個傳統設計，其完全的 揭露併入文中做參考。在這些裝置中，電容器元件在金屬區 域Ml之上。 已知當晶片尺寸繼續變得愈來愈小，有需要從傳統的多 晶石夕閘極結構移到一金屬閘極結構。例如見Tadahiro Ohmi 等人的’’New Paradigm of Silicon Technology’’，Proceedings of the IEEE, Vol.89, No.3, March 2001, pp 394-412 ； Yee-Chia Yeo等人的’’Dual-Metal Gate CMOS Technology with Ultrathin Silicon Nitride Gate Dielectric"，IEEE Electron Device Letters, Vol.22, No.5, May 2001, pp 227-229 ； Qiang 等人的 nDual-Metal Gate Technology for Deep-Submicron CMOS Transistor"， IEEE 2000 Symposium on VLSI Technology Digest of Technical Papers, pp 72-73 ； Gardner 等人申請的美國專利號碼6,057,583"Transistor with Low
Resistance Metal Source and Drain Vertically Displaced From the Channel*’ ； Gardner等人申請的美國專利號碼 6，165,858’’Enhanced Silicidation Formation for High Speed MOS Device by Junction Grading with Dual Implant Dopant Species” ； Huang等人申請的美國專利號碼6,033,963 ’’Method of Forming a Metal Gate for CMOS Devices Using a Replacement gate Process” ； Liang等人申請的美國專利號碼 6，130，123’’Method for Making a Complementary Metal Gate Electrode Technology1· ; Maiti等人申請的美國專利號碼 6,049,114MSemiconductor Device Having a Metal Containing 86245
200403871
Layer Ovedying a Gate Dielectric"，其完全的揭露併入文中 做參考。 並且，依據電路設計，閘極材料的選擇可以具有一功求 數匹配P型石夕或N型珍結構，或一功函數位於= 之間，其被指定為中能隙金屬。這三群問級材料的血型例 子個別是Ni、TaN、Ru0與M〇N ; Ru、Ta與⑽；及w。相 似導體材料可以被用在"夕的源極與汲極區域上，因此具有 利用這些金屬接觸之-敗為-MIM電容器下電極的好處， 其可以比傳統的多晶矽閘極電極與MIM電容器的組合大大 縮小物理空間。 ' θ 因此，有需要對一新茛置其利用一金屬 免屬接觸做電晶體源 極/汲極與MIM電容器下電極的雙重電極。甚且，有需要對
-新裝置其提供-更高的堆積密度，而沒有伴隨傳統電 體裝置的其他問題。 E 【發明内容】 回顧前面及傳統電晶體裝置其他問題、缺點與壞處，本 發明已設計及是本發明一個目的提供一 、 ^ 〜構與万法用來製 造具有金屬閘極與金屬接點電容器的微 % 丁兒路。本發明 另-個目的是利用共用製程步驟及金屬閑極與金屬電容哭 間的材料大大減少製造該裝置的製程成本。而本發明另二 個目的是利用使用高密度DRAM的方法。 為了獲得上面提到的目的，根據本發明、 π ~万面一積體 講結構包括-對電μ ’有提供每個電容器具有被1 緣層分隔的金屬板’及該金屬問極半導體電晶體電氣連接 86245 200403871 到$亥等電容器。智雷％油 4 、一 4甩日日k的金屬間極及每個電容器的金屬 包括相同的金屬層在積體電路結構中。更特別地， 今m — 有―上金屬板垂直地在下 .广及母個電晶體的金屬閘極及該等電容ϋ的每個 上王屬板包括相同的金屬層在積體電路結構中。進—步， 每個電晶體包括一沒極區域連接到_臨近電 下金屬板。 」 本1月也I疋供形成一金屬_絕緣層_金屬電容器及具有— 金屬閘極的—結合的半導體電晶體之方法。該方法形成犧 牲閘極結構的目案在—基板上，接臨犧牲閘極結構形成側 壁填隙層’形成第一金屬層接臨側壁填隙I，平坦化第一 金屬層，移除犧牲閘極結構’形成一絕緣層在第一金屬層 上’從-閘極區域移除_部份第_金屬層，及形成第二金 屬層在該絕緣層上與在該閘極區域中 晶體閑極及電晶體平板兩者。 屬曰… 第-金屬層的平坦化減少第二金屬層中的孔洞與表面不 規則。减緣層包括—電容器絕緣層與—閘極絕緣層兩者 。並且，形成茲侧壁填隙層之後，本發明在基板中摻雜源 極與沒極區域。 【實施方式】 對eDRAM不僅DRAM的功能必需改進，其他邏輯電路 如CPU的功能也必需改進以增進整個系統的功能。目前習 知趨勢是使用金屬閘極用及支撐電路兩者的内埋 應用。使用一金屬電容器（如一 MIM)用在DRAM及支撐電路 86245 二 200403871 節省晶片尺寸’特別地當併用—高k介電材料時。融(介電 常數)材料如氧化銘、五氧化妲、二氧化欽、鈦酸總鋇或： 他鐵電材料是與金屬板匹配。以下說明形成—金屬問極與 在一 DRAM晶片結構肩並間排列金屬接觸電容器的一製程 。然而，下面所示具體實施例僅是一實施例及，如一般熟 悉此項技藝之人士應知道，本發明同樣應用到其他結構如 需要一電容器的支撐電路之處。 現在參考附圖，及更特別地參考圖丨，所示是一部份完成 的U兒子裝置1包括一基板1000 ,淺溝隔離（STI)區域14⑻ ，一閘極絕緣層如一薄犧牲氧化物層1200在811區域1400上 ，基板1000，及閘極電極1100座落在閘極絕緣層12〇〇上。 基板1000較佳地包括一雜質摻雜井13〇〇，如一矽晶圓或在 絕緣層上覆矽的晶圓。該Siri區域14〇〇一傳統方法形成如光 微影蝕刻形成圖案，乾式蝕刻至深度低於半導體接面之下 ，如那些熟悉此項技藝人士習知之後續製程步驟形成的氧 化物填充沉積及化學機械研磨（CMP)平坦化。該薄犧牲氧化 物層1200形成在基板1〇〇〇上接著形成氧化物虛擬閘極圖案 1100具有一氧化物厚度從i μηι至3 μιη。該虛擬閘極較佳地 具有一高深寬比（例如10至30)以減少在以下說明的平坦化 製程中之缺陷及孔洞。 圖2表示氮化物側壁填隙物1500其是使用一傳統製程如 沉積與蝕刻形成在每個閘極圖案1丨00的側壁上。填隙物厚 度需要在最小微影|虫刻特徵尺寸範圍内以幫助減小電路尺 寸。進一步，圖2說明增加的雜質佈植之影響其轉變輕摻雜 86245 - -10- 200403871 區域1300成更重摻雜區域16〇〇，16〇1及16〇2其最後將形成 電晶體的源極/汲極區域。 在圖3 ’使用任何傳統方法包括cvd、濺鍍等沉積第一金 屬層1700在基板1000、側壁填隙物15〇〇、閘極電極11〇〇及 STI區域1400上。該沉積包括具有一與矽低反應性的金屬（ 如所示）或一雙層結構。具一雙層結構，沉積一薄擴散障壁 層如ΤιΝ接著一底結節板用做電容器電極。該擴散障壁防止 結節板材料與矽源極及汲極接點反應。 圖4說明裝置1實施一化學機械研磨製程後達到平坦化該 、’、口構1。圖5中’ 一遮罩（未表示）被用來移除被虛擬閘極區域 110 0佔據面積中之虛擬閘極材料11⑼及犧牲氧化物12 〇 〇。 該氧化物1200仍舊在側壁填隙物1500之下。較佳地，本發 明為了僅移除露出的氧化物及因此使用一選擇性電浆蝕刻 或濕式蝕刻留下孔洞2100在閘極區域。 圖6中，一裁切遮罩2200被用來定義每個電容器的結節板 3500，3700。項目2300—般表示該結節板區域。區域36〇〇 做為犧牲區域稍後被移除。圖7中，一高k介電層2400覆蓋 結節板3500及3700，側壁填隙物1500及基板1〇〇〇露出的部 份。 另一遮罩2500，如圖8所示，具有一開孔2600被用來連結 一選擇性蝕刻製程以移除犧牲區域3600及露出的高k介電 材料2400。如圖9所示，接著移除遮罩2500。如圖1〇所示， 另一層金屬2800被沉積在結構1上及被平坦化。第二金屬 2800可以是與第一金屬1700相同或不同的材料。金屬層 86245 . 200403871 2800的厚度可以被控制以致不需研磨製程。遮罩2700於是 形成圖案在該結構上。 實施一金屬蝕刻製程通過遮罩2700至蝕刻第二金屬2800 以形成電容器平板3000與3400，閘極3100與3300，及一共 同源極接點3200。接著移除遮罩2700及以一絕緣層取代。 或者，該遮罩2700可以做為一絕緣層。如此項技藝所熟悉 ，實施增加的製程以使該結構與其他裝置連接及絕緣。 該製程形成圖11與13所示的雙電容器結構。更特別地， 金屬電容器平板3000，絕緣層2400及金屬結節板3500形成 第一電容器。相似地，金屬電容器平板3400，絕緣層2400 及金屬結節板3700形成第二電容器。汲極區域1600，閘極 3100，及共同源極1601包括一電晶體其與第一電容器（3000 ，2400，3500)接觸及汲極區域1602，閘極3300及共同源極 1601包括第二電晶體其容許鄰接第二電容器（3400，2400， 3 700)。圖13是一俯視圖與圖11所示相同的結構。並且，圖 13所示第一電容器（3000，2400，3500)通常稱項目3800，第 二電容器（3400，2400，3700)通常稱項目3802。進一步，圖 13所示位元線3710其包括接點3705形成電氣連接到共同源 極接點3200。 使用本發明，該結構維持一實際上平坦的結構，其容許 金屬層2800完全地形成上平板，閘極與源極接點。不用本 發明製程，金屬層2800將有一不規則的（非平面的）形狀，如 圖12所示。更特別地，如圖4所示平坦化製程建立一平坦表 面其容許剩下製程維持一均勻的平坦表面。如圖12所示結 -12- 86245 ： 200403871 構將減低產率，因為接點， 結構可靠地艰忐中尸土 σσ平板等將不如本發明的 。偁J非地形成電氣連接。因 的結構比較實際上具有較 Λ㈣構當與傳統 乂回產率與較高可靠度。 並且’本發明使用相同 ,τ 、’屬層做為閘極3100盥雷宏哭的 上平板3000, 3400兩者。利用 〇”包奋备的 地捭谁裝W Μ 乍閘極舁上金屬板，驚人 地ί曰進裝置的功能。進一步 ’ 電容哭平m * 厂利用相同金屬層做為閘極與 :千板兩者’本發明減少製程成本與材料成本。並且 ，精減少製程步驟的數目，本 因此增加產率與可靠度。 S心“缺陷的機會及 雖然本發明已利用較佳 住八把只她例說明，那些熟悉此項 技U士應孩瞭解本發明可以在附錄的申請專利範圍的精 神及範圍内修正來實施。 【圖式簡單說明】 從以上本發明較佳具體實施例的詳細說明參考附圖將更 瞭解前述及其他目的、方面與好處，其中： 圖1是部份完成的微電子裝置橫截面圖示； 圖2是部份完成的微電子裝置橫截面圖示； 圖3是部份完成的微電子裝置橫截面圖示； 圖4是部份完成的微電子裝置橫截面圖示； 圖5是部份完成的微電子裝置橫截面圖示； 圖6是部份完成的微電子裝置橫截面圖示； 圖7是部份完成的微電子裝置橫截面圖示； 圖8是部份完成的微電子裝置橫截面圖示； 圖9是部份完成的微電子裝置橫截面圖示； 86245 ： -13- 200403871 圖10是部份完成的微電子裝置橫截面圖示； 圖11是一完成的微電子裝置橫截面圖示； 圖12是一完成的微電子裝置橫截面圖示； 圖13是圖11 一完成的微電子裝置俯視圖示。 【圖式代表符號說明】 1 微電子裝置 1000基板 1100虛擬閘極區域 1200犧牲氧化物 1300雜質摻雜井 1400淺溝隔離（STI)區域 1500側壁填隙物 1600、1601、1602重摻雜區域 1700第一金屬層 2100孔洞 2200裁切遮罩 2300結節板區域 2400高k介電層 2500、2700 遮罩 2600開孔 2800第二金屬層 3000、3400金屬電容器平板 3100、3300 閘極 3200共同源極接點 -14- 86245 ： 200403871 3500、3700電容器的結節板 3600犧牲區域 3705接點 3710位元線 3800 、 3802 項目 -15- 86245 ：

Claims (1)

  1. 200403871 拾、申請專利範圍： 1. 一種積體電路結構，包括： 一電容器，具有被一絕緣層分隔的金屬板；及 一半導體電晶體，電連接到該電容器及具有一金屬閘 極。 2. 如申請專利範圍第1項之積體電路結構，其中該金屬閘極 及該金屬板之一包括相同金屬層在該積體電路結構中。 3. 如申請專利範圍第1項之積體電路結構，其中該電容器包 括一垂直電容器，具有一上金屬板垂直在一下金屬板上。 4. 如申請專利範圍第3項之積體電路結構，其中該金屬閘極 與該上金屬板包括相同金屬層在該積體電路結構中。 5. 如申請專利範圍第3項之積體電路結構，其中該電晶體包 括一汲極區域連接到下金屬板。 6. 一種積體電路結構，包括： 一對電容器，各具有被一絕緣層分隔的金屬板；及 半導體電晶體，各電連接到該等電容器之一， 其中各半導體電晶體具有一金屬閘極。 7. 如申請專利範圍第6項之積體電路結構，其中該等電晶體 的各金屬閘極及各電容器的金屬板之一包括相同金屬層 在該積體電路結構中。 8. 如申請專利範圍第6項之積體電路結構，其中各電容器包 括一垂直電容器具有一上方金屬板垂直在一下方金屬板 9. 如申請專利範圍第8項之積體電路結構，其中該等電晶體 86245 ： 的各金屬閘極及該等電容哭 屬層在該積體電路結構中各上万金屬板包括相同金 10.2請專利範圍第8項之積體電路結構，其中各電晶體包 n 一任 鄰接％合奋的個別下方金屬板。 .種形成-金屬'絕緣層-金屬電容器及一具有— 極的結合半導體電晶體之方法，該方法包括： " 形成第一金屬層； 形成一絕緣層在該第一金屬層上； 從一閘極區域移除一部份該第一金屬層；及 形成第二金屬層在該絕緣層上與在該閘極區域中， /、中A第一金屬層包括該電晶體的一閘極及該電晶體 的一平板。 U·如申請專利範圍第u項之方 隙物鄰接犧牲閘極結構，其 側壁填隙物上。 法’進一步包括形成側壁填 中該第一金屬層被形成在該 13·如申請專利範圍第丨丨項之方法，進—步包括在形成該側 壁填隙物之後，摻雜在該基板中的源極與汲極區域。 14·如申請專利範圍第11項之方法，進一步包括平坦化該第 一金屬層。 1 5.如申請專利範圍第14項之方法，其中該第一金屬層的平 坦化減少在該第二金屬層中的孔洞及表面不規則。 1 6.如申請專利範圍第丨丨項之方法，進一步包括形成一絕緣 層在該第一金屬層上。 1 7·如申請專利範圍第16項之方法，其中該絕緣層包括一電 86245 18.200403871 容器絕緣層與一閘極絕緣層。 如申μ專利範圍第丨丨項之方法，其中該平板包括該電容 器的一上平板。 19. 20. 21. 22. 23, 種形成一金屬·絕緣層_金屬電容器及一具有一金屬閘 極的結合半導體電晶體之方法，該方法包括： 形成犧牲閘極結構圖案在一基板上； 形成側壁填隙物鄰接該等犧牲閘極結構； 形成第一金屬層鄰接該側壁填隙物； 平坦化該第一金屬層； 移除該等犧牲閘極結構； 形成一絕緣層在該第一金屬層上； 從一閘極區域移除一部份該第一金屬層；及 形成第二金屬層在該絕緣層上與在該閘極區域中， 其中該第二金屬層包括該電晶體的一閘極及該電晶體 的一平板。 如申請專利範圍第19項之方法，其中該第一金屬層的平 坦化減少在該第二金屬層中的孔洞及表面不規則。 如申請專利範圍第19項之方法，其中該絕緣層包括一電 容器絕緣層與一閘極絕緣層。 如申請專利範圍第19項之方法，進一步包括在形成該側 壁填隙物之後，摻雜在該基板中的源極與汲極區域。 如申請專利範圍第21項之方法，其中該平板包括該電容 器的一上平板。 86245 ；
TW092117823A 2002-08-21 2003-06-30 Integrated metal-insulator-metal capacitor and metal gate transistor TWI232002B (en)

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