TW200402873A - Nonvolatile memory device - Google Patents

Nonvolatile memory device Download PDF

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Publication number
TW200402873A
TW200402873A TW092121497A TW92121497A TW200402873A TW 200402873 A TW200402873 A TW 200402873A TW 092121497 A TW092121497 A TW 092121497A TW 92121497 A TW92121497 A TW 92121497A TW 200402873 A TW200402873 A TW 200402873A
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TW
Taiwan
Prior art keywords
memory device
patent application
volatile memory
item
voltage
Prior art date
Application number
TW092121497A
Other languages
Chinese (zh)
Inventor
Masahiko Hirai
Naotake Sato
Original Assignee
Canon Kk
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Publication date
Application filed by Canon Kk filed Critical Canon Kk
Publication of TW200402873A publication Critical patent/TW200402873A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0009—RRAM elements whose operation depends upon chemical change
    • G11C13/0014—RRAM elements whose operation depends upon chemical change comprising cells based on organic memory material
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/101—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including resistors or capacitors only
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K19/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00
    • H10K19/80—Interconnections, e.g. terminals

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  • Engineering & Computer Science (AREA)
  • Nanotechnology (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
  • Read Only Memory (AREA)
  • Thin Film Transistor (AREA)

Abstract

The invention provides a nonvolatile memory device that enables formation of integrated circuits on a substrate such as glass and resin substrates and selection of a desired cell, where the nonvolatile memory device comprises a matrix wiring, a switching element, and a memory element, wherein the memory has a changeable impedance, and both the switching element and the memory element comprises an organic semiconductor or an organic electric conductor or both.

Description

200402873 (1) 玖、發明說明 .【發明所屬之技術領域】 本發明係關於一種非揮發性記憶裝置，包含一矩陣接 線，一開關元件，和一記憶元件。 【先前技術】 近年來，使用有機半導體材料之電子裝置已廣泛的發 展’且有許多報告針對於有機EL(電致發光），有機 TFT(薄膜電晶體），和有機半導體雷射之發展。有機 TFT(典型的有機電晶體），特別的被約定爲以低成本的形 成積體電路在如玻璃和樹脂之廉價材料之基底上之技術。 關於有機電晶體之構造方面，已揭示之裝置包括一源 極電極，一汲極電極，一閘極絕緣膜，和一閘極電極 (USP5596208 ， 6278127 ， 5946551 ， 5981970 ， 6210479 ， 6344660，和 6344662) 〇 關於有機電晶體方面，所需的是建構一非揮發性記憶 裝置在如玻璃和樹脂之廉價基底上。但是，迄今仍無記憶 構造，其功能可與製造在一矽基底上之快閃記憶體和 EEPROM(電可抹除可程式唯讀記憶體）相容。日本專利申 請案公開第200卜1 8943 1號案揭示一記憶體構造，其可儲 存多重値在單一胞中，其中有機材料之阻抗隨所施加電壓 而改變，但是，該專利案仍未揭示積體電路形成在玻璃或 樹脂基底上以選擇所需胞之構造。 (2) (2)200402873 【發明內容】 本發明旨在解決在習知技藝之記憶構造中之問題，亦 即，難以形成非揮發性記憶裝置在如玻璃和樹脂基底之廉 價基底上以選擇所需胞。因此，本發明之目的乃在提供一 種非揮發性記憶裝置，其以有機材料構成，且其可製造積 體電路在如玻璃和樹脂基底之廉價基底上以選擇所需胞。 因此，依照本發明，於此提供一種非揮發性記憶裝 置，包含一矩陣接線，一開關元件，和一記億元件，其中 該記憶元件具有一可變阻抗，開關元件和記憶元件包含一 有機半導體元件或一有機電導體或兩者皆有。 依照本發明，一種非揮發性記憶裝置乃構造成可形成 在玻璃或樹脂基底上，且可選擇所需胞。 【實施方式】 在本發明之非揮發性記憶裝置之構造中，記億元件具 有一可變阻抗，和開關元件和記憶元件包含一有機半導體 元件或一有機電導體或兩者皆有。此構造乃根據當施加之 一高於讀取電壓之寫入電壓時，在讀取電壓上之記億元件 之有機電導體之阻抗會改變。 特別的，較佳的是，當施加高於讀取電壓之寫入電壓 時，在讀取電壓上之記憶元件之有機電導體之阻抗不可反 向的增加。根據此特性，一旦寫入之資訊變成非可再寫， 不僅在安全的觀點上是較佳的’且相較於EEPROM，其亦 可允許使用較簡單的驅動方法。 200402873200402873 (1) 发明. Description of the invention. [Technical field to which the invention belongs] The present invention relates to a non-volatile memory device including a matrix connection, a switching element, and a memory element. [Previous Technology] In recent years, electronic devices using organic semiconductor materials have been extensively developed 'and many reports have been directed at the development of organic EL (electroluminescence), organic TFT (thin-film transistor), and organic semiconductor lasers. Organic TFTs (typical organic transistors) are specifically agreed upon as low-cost technology for forming integrated circuits on a substrate of inexpensive materials such as glass and resin. Regarding the structure of the organic transistor, the disclosed device includes a source electrode, a drain electrode, a gate insulating film, and a gate electrode (USP5596208, 6278127, 5946551, 5981970, 6210479, 6344660, and 6344662) With regard to organic transistors, what is needed is to construct a non-volatile memory device on an inexpensive substrate such as glass and resin. However, there is no memory structure so far, and its function is compatible with flash memory and EEPROM (electrically erasable programmable read-only memory) fabricated on a silicon substrate. Japanese Patent Application Publication No. 200b 1 8943 1 discloses a memory structure that can store multiple cells in a single cell, where the impedance of the organic material changes with the applied voltage, but the patent has not yet revealed The bulk circuit is formed on a glass or resin substrate to select the desired cell configuration. (2) (2) 200402873 [Summary of the invention] The present invention aims to solve the problem in the memory structure of the conventional art, that is, it is difficult to form a non-volatile memory device on an inexpensive substrate such as a glass and a resin substrate to select an Need cells. Therefore, an object of the present invention is to provide a non-volatile memory device which is composed of an organic material, and which can manufacture integrated circuits on inexpensive substrates such as glass and resin substrates to select a desired cell. Therefore, according to the present invention, there is provided a non-volatile memory device including a matrix wiring, a switching element, and a billion element, wherein the memory element has a variable impedance, and the switching element and the memory element include an organic semiconductor. An element or an organic electrical conductor or both. According to the present invention, a non-volatile memory device is configured to be formed on a glass or resin substrate, and a desired cell can be selected. [Embodiment] In the structure of the non-volatile memory device of the present invention, the billion-dollar element has a variable impedance, and the switching element and the memory element include an organic semiconductor element or an organic electric conductor or both. This structure is based on the fact that when a write voltage higher than the read voltage is applied, the impedance of the organic electric conductor of the billion-dollar element on the read voltage changes. In particular, it is preferred that when a write voltage higher than the read voltage is applied, the impedance of the organic electrical conductor of the memory element at the read voltage cannot be increased in the opposite direction. According to this characteristic, once the written information becomes non-rewritable, it is not only better from a security point of view, but also allows a simpler driving method to be used compared to EEPROM. 200402873

開關元件最好爲包括有機半導體或有 晶體。開關元件可選擇所需之記憶胞。電 電晶體，薄膜型電晶體，接面型電晶體等 任一'電晶體。有機半導體爲Fermi位準在 且具有半導體特性。有機電導體爲Fermi 之材料，且具有主金屬電導率。 開關元件爲一二極體，包含有機半 體。在此例中，可以相當簡單的矩陣構 置。 除了位元線和字線外，最好能提供地 之一端連接至位元線之一，電晶體之另一 一，和電晶體之又一端經由一記憶元件連 記憶元件可構造以展開介於在基底之 之兩電極，亦即，一記憶元件電極和地線 造使記憶元件可藉由印刷等形成。 非揮發性記憶裝置最好形成在一樹月I 許非揮發性記憶裝置之使用成如1C卡或 此1C卡或IC標記可使用當成用於季節性 或包裝傳送之非揮發性記憶裝置。替代的 卡匣上，以包含一光敏鼓或調色器在如雷 機之電照相系統中。此種使用是較佳的， 在出貨前或在產生使用時，儲存各種或大 以下參考圖式說明本發明之實施例。 機電導體之一電 晶體包括場效型 ，且可使用上述 帶隙中之材料， 位準接近導電帶 導體或有機電導 造建構一記憶裝 線，以使電晶體 端連接至字線之 接至地線之一。 .平面方向上分離 :間之間隙。此構 ‘基底上。如此允 IC標記之形式。 :通過，辨識卡， f，其可提供在一 射印表機和影印 因爲記憶裝置可 量的資訊。 (4) (4)200402873 第一實施例 圖1顯示1 6位元記憶裝置之構造，其包含位元線 BL1-BL4，與位元線交叉之字線 WM-WL4，和單元胞 C11-C14，每個胞由當成含有機半導體之開關元件之有機 TFT(薄膜電晶體）T11-T44之一和記憶元件R11-R44之一 所組成。有機TFT ΤΙ 1-Τ44之閘極電極連接至字線，汲極 電極連接至位元線，源極電極連接至記憶元件R1 1-R44之 一之一端，而記憶元件之另一端接地。 記憶元件之特別構造爲有機電導材料位於電極之間隙 間。此可藉由施加一液體材料在電極間並此其乾燥而達 成。記憶元件之電特性如圖2所示。當施加在電極間之電 壓從0V掃至5V時，在第一和第二掃線間之特性不同。 在弟一掃線中，電流量在約4V之應用電壓下實質下降， 導致高電阻狀態，且此高電阻狀態在第二掃線時保持。此 電阻之改變是不可逆的，且一旦達到高電阻狀態，則不會 返回低電阻狀態。當讀取電壓約爲3 V時，在低電阻狀態 中之記憶元件之電阻在高電阻狀態中增加兩級。亦即，阻 抗增加是不可逆的。 具有上述特性之有機電導體之例包括聚噻吩衍生物， 聚吡咯衍生物，聚苯胺衍生物，和聚對苯撐乙嫌撐衍生 物。 其次參考範例說明本發明之記憶裝置之驅動方法。 首先說明讀取操作。假設每一 TFT作用當成—p通 道。關於參考電壓方面（在圖1中示爲” Ref”），之電輝 (5) (5)200402873 (對應於3V電源電壓之2/3)施加至一感應放大器。其次， 在胞C23中之資訊受讀取如下。-3V之電壓施加至字線 WL3，以使選擇電晶體T23變成啓動狀態。而後，數// A 之固定電流施加至位元線BL2，而電壓限制爲-3V。此 時，如果C23受到選擇和R23在低電阻狀態下，電流從 BL2流至T23和至地，和BL2之電位變成接近地電壓。 因此，位元線BL2之電位變成高於參考電壓，和感應放 大器SA2輸出”1”。另一方面，當R23在高電阻狀態時， 電流難以從BL2流至T23和至地，且BL2之電位變成接 近電源電壓。因此，位元線BL2之電位變成低於參考電 壓，且感應放大器SA2輸出”0”。 其中說明寫入操作。假設R23在低電阻狀態當成初始 狀態。字線WL3施加以-3V之電壓和選擇電晶體T23啓 動。而後，約1 〇 # A之固定電流施加至位元線B L 2，而電 壓限制爲-6V。此時，C23受選擇和高於5V之電壓施加至 R2 3，和1 0 // A之電流流動。此時，R2 3不可逆的轉換成 高電阻狀態。藉由此動作，資訊寫入C2 3。 其次說明本發明之記憶裝置之製造方法。 圖3至6爲說明本實施例之記憶裝置之製造方法之示 意圖。參考數字1表示一基底，2爲接點，3爲記憶元件 電極，4爲地線，5爲閘極電極，6爲閘極絕緣膜，7爲汲 極電極，8爲源極電極，9爲有機半導體層，1〇爲保護 膜，1 1爲用於記憶元件之有機電導材料，和12爲保護 膜。 -8 - (6) (6)200402873 首先，如圖3所示，記億元件3，地線4，和閘極電 極5藉由蝕刻提供在以環氧樹脂製成之基底1之兩面（背 面和正面）之銅膜而形成，和接點2藉由以銅電鍍塡充一 通孔而形成。於此，閘極電極5連接至字線。記憶元件3 和地線4提供在基底1之一面上，和閘極電極5提供在另 一面上。 其次，如圖4所示，以濺鍍法形成氧化鋁薄膜當成閘 極絕緣膜6。此閘極絕緣膜使用一金屬掩模以覆蓋閘極電 極5而選擇的形成。再者，一金薄膜以真空沉積法形成當 成汲極電極7和源極電極8。它們使用一金屬掩模與閘極 絕緣膜6選擇性形成。此時，汲極電極7連接至位元線， 和源極電極8連接至接點2。 其次，如圖5所示，戊省（pentacene)真空沉積當成有 機半導體層9。關於閘極絕緣膜6方面，有機半導體層9 使用一金屬掩模以覆蓋介於源極電極8和汲極電極7包括 每一電極之一部份間之區域，亦即，覆蓋介於電極間之區 域而選擇性的形成。其次，酚醛淸漆樹脂應用和硬化當成 保護膜1 〇。 而後，如圖6所示，有機電導體Ped〇T/PSS (聚乙烯-雙氧-噻吩-聚苯乙烯-磺酸）應用和乾燥以展開介於記憶元 件電極3和地線4間之間隙，特別的覆蓋介於記憶元件電 極3和地線間之區域和它們一部份，藉以形成記憶元件。 而後，一保護膜12形成在其上。 再者’雖然圖中未顯示，位元線連接至感應放大器之 -9 - (7) (7)200402873 一端，和相較於另一端之參考電壓，當位元線電位高於參 考電壓時，輸出”1”（高電位：電壓靠近地電壓），而當位 元線電位低於參考電位時’輸出”0，，（低電位：電壓靠近源 極電壓）。 以下說明在讀取操作爲_ 3 V和寫入操作爲_ 6 v之預先 狀況，所製造之記憶裝置之區域。 首先說明讀取操作。-2V之電壓（亦即2v電源電壓之 2/3)施加至感應放大器當成參考電壓（圖1中之“Ref，，）。 其次，進行在胞C23中之資訊之讀取操作。-3V之電 壓施加至字線 WL3，和所選擇之電晶體T23啓動。其 次，5 β A之電流施加至位元線B L2，而其電壓限制爲-3V。此時，當C23受選擇且R23在低電阻狀態下，電流 從BL2流至T23，和至地，以引起BL2之電位變成靠近 地電壓。因此，位元線BL2之電位變成高於參考電壓， 且感應放大器SA2輸出”1”。另一方面，當R2 3在高電阻 狀態時，電流從BL2流至T23，而至地之電流變成極少， 禾口 BL2之電位變成靠近電源電壓。因此，位元線BL2之 電位變成低於參考電壓，且感應放大器SA2輸出”0”。 其次說明寫入操作。假設R23如同初始狀態在低電阻 狀態。-3V之電壓施加至字線WL3，和所選擇之電晶體 T23啓動。其次，1 0 // A之固定電流施加至位元線BL2， 而其電壓限制爲-6V。此時，當C23受選擇，高於5V之 電壓施加至R23，和10 // A之電流流動。此時’ R23不可 逆的轉換成高電阻狀態。因此，資訊寫入C23 ° -10· (8) (8)200402873 在本發明之非揮發性記憶裝置中，開關元件可爲二極 體。替代的，本發明之非揮發性記憶裝置亦可使用一接面 型電晶體當成開關元件。 第二實施例 此實施例之非揮發性記億裝置使用二極體當成開關元 件。圖7顯示此實施例之構造例。 在本實施例中，如同第一實施例，每一胞具有一開關 元件和一記憶元件。在第一實施例中，每一胞具有一電晶 體元件當成開關元件，替代的，在第二實施例中，每一胞 具有二極體元件當成開關元件。 如圖7所示，本實施例之非揮發性記憶裝置具有多數 胞在行和列方向（從Cl 1至C44)。例如，取一胞而言，胞 C 1 1具有二極體D 1 1和記憶元件Μ 1 1。每一記憶元件之一 端連接至每一胞之二極體，和另一端共同連接至字線 WL。於此有多重字線WL，且它們連接至多數記憶元件， 在行對行之基礎上。未連接至記憶元件之二極體之一端共 同連接至一位元線BL。於此有多重位元線BL，且它們連 接至多數二極體之一端，在列對列之基礎上。 其次說明讀取操作。例如，選擇胞C22，固定電壓 Vcc施加至BL2，因此電流經由電阻R2流至接地BL2。 在此狀況下，不低於Vcc之電壓乃施加至非WL2之字線 WL，因此，除了所選擇的外，無電流會流至胞中。此 時，藉由比較BL2之電位和參考電壓Ref，可讀取資訊。 -11 - 0)200402873 2Vcc 狀況 WL， 造使 藉以 【圖 和 主要 其次說明寫入操作。例如，選擇胞C22，固定電壓 施加至BL2，因此電流經由電阻R2流至BL2。在此 下，不低於2Vcc之電壓乃施加至非 WL2之字線 因此，除了所選擇的外，無電流會流至胞中。此構 所選擇之C22之記憶元件D22被施加一大電壓’且 改變阻抗。 式簡單說明】 圖丨爲第一實施例之電路構造之電路圖； 圖2爲記憶元件之電特性圖； 圖3爲第一實施例之記憶裝置之相關部份之截面圖； 圖4爲第一實施例之記憶裝置之相關部份之截面圖； 圖5爲第一實施例之記憶裝置之相關部份之截面圖； 圖6爲第一實施例之記億裝置之相關部份之截面圖； 圖7爲第二實施例之電路構造之電路圖。 元件對照表 BL1—BL4 位元線 WL1 — WL4 字線 C11—C14 單元胞 T11—T44 有機TFT R11-R44 記憶元件 1 基底 -12- 200402873 (10) 2 接點 3 記憶元件電極 4 地線 5 閘極電極 6 閘極絕緣膜 7 汲極電極 8 源極電極 9 有機半導體層 10 保護膜 11 有機導電材料 12 保護膜 SA2 感應放大器The switching element preferably includes an organic semiconductor or a crystal. The switching element can select a desired memory cell. Transistors, thin film transistors, junction transistors, etc. Organic semiconductors are Fermi-level and have semiconductor characteristics. The organic electrical conductor is made of Fermi and has the conductivity of the main metal. The switching element is a diode and includes an organic half. In this example, a fairly simple matrix construction is possible. In addition to the bit line and the word line, it is best to provide one end of the ground connected to one of the bit lines, the other one of the transistor, and the other end of the transistor through a memory element connected to the memory element. The two electrodes on the substrate, that is, a memory element electrode and a ground wire enable the memory element to be formed by printing or the like. The non-volatile memory device is preferably formed in a single month. The non-volatile memory device can be used as a 1C card or this 1C card or IC tag can be used as a non-volatile memory device for seasonal or package transfer. The replacement cassette contains a photosensitive drum or toner in an electrophotographic system such as a laser. This kind of use is preferred, and it is stored in various sizes or large before shipment or when it is used. The embodiments of the present invention will be described with reference to the drawings. One of the electromechanical conductors includes a field effect type, and the materials in the above band gap can be used, and the level is close to the conductive band conductor or organic conductance to build a memory wire so that the transistor end is connected to the word line and ground Line one. .Separation in the plane direction: the gap between. This structure ‘on the base. This allows the form of the IC mark. : Pass, identification card, f, which can provide information on a printer and photocopier because the memory device can measure. (4) (4) 200402873 First Embodiment FIG. 1 shows the structure of a 16-bit memory device, which includes bit lines BL1-BL4, a word line WM-WL4 that intersects the bit lines, and unit cells C11-C14 Each cell is composed of one of the organic TFTs (thin film transistors) T11-T44 and the memory elements R11-R44 as the switching elements containing organic semiconductors. The gate electrode of the organic TFT ΙΙ-Τ44 is connected to the word line, the drain electrode is connected to the bit line, the source electrode is connected to one end of one of the memory elements R1 1-R44, and the other end of the memory element is grounded. The memory element is particularly structured such that the organic conductive material is located between the electrodes. This can be achieved by applying a liquid material between the electrodes and drying it. The electrical characteristics of the memory element are shown in Figure 2. When the voltage applied between the electrodes is swept from 0V to 5V, the characteristics between the first and second scan lines are different. In the first sweep line, the amount of current substantially decreases at an applied voltage of about 4V, resulting in a high-resistance state, and this high-resistance state is maintained during the second sweep line. This resistance change is irreversible, and once it reaches the high resistance state, it will not return to the low resistance state. When the read voltage is about 3 V, the resistance of the memory element in the low resistance state is increased by two stages in the high resistance state. That is, the increase in impedance is irreversible. Examples of the organic electric conductor having the above characteristics include polythiophene derivatives, polypyrrole derivatives, polyaniline derivatives, and polyparaphenylene vinylene derivatives. Next, a driving method of the memory device of the present invention will be described with reference to examples. The read operation is explained first. It is assumed that each TFT acts as a -p channel. Regarding the reference voltage (shown as "Ref" in Fig. 1), the electric glow (5) (5) 200402873 (corresponding to 2/3 of the 3V power supply voltage) is applied to a sense amplifier. Second, the information in cell C23 is read as follows. A voltage of -3V is applied to the word line WL3, so that the selection transistor T23 is turned on. Then, a fixed current of a number // A is applied to the bit line BL2, and the voltage is limited to -3V. At this time, if C23 is selected and R23 is in a low resistance state, the current flows from BL2 to T23 and to ground, and the potential of BL2 becomes close to the ground voltage. Therefore, the potential of the bit line BL2 becomes higher than the reference voltage, and the inductive amplifier SA2 outputs "1". On the other hand, when R23 is in a high resistance state, it is difficult for current to flow from BL2 to T23 and to ground, and the potential of BL2 becomes close to the power supply voltage. Therefore, the potential of the bit line BL2 becomes lower than the reference voltage, and the sense amplifier SA2 outputs "0". It describes the write operation. Assume that R23 is the initial state in the low resistance state. The word line WL3 is activated by applying a voltage of -3V and the selection transistor T23. Then, a fixed current of about 10 # A is applied to the bit line B L 2 and the voltage is limited to -6V. At this time, C23 is selected and a voltage higher than 5V is applied to R2 3, and a current of 1 0 // A flows. At this time, R2 3 irreversibly transitions to a high resistance state. With this operation, information is written into C2 3. Next, a method for manufacturing the memory device of the present invention will be described. 3 to 6 are schematic views illustrating a method of manufacturing the memory device of this embodiment. Reference numeral 1 indicates a substrate, 2 is a contact, 3 is a memory element electrode, 4 is a ground wire, 5 is a gate electrode, 6 is a gate insulating film, 7 is a drain electrode, 8 is a source electrode, and 9 is For the organic semiconductor layer, 10 is a protective film, 11 is an organic conductive material for a memory element, and 12 is a protective film. -8-(6) (6) 200402873 First, as shown in FIG. 3, the memory element 3, the ground line 4, and the gate electrode 5 are provided on both sides (back surface) of the substrate 1 made of epoxy resin by etching. And front side), and the contact 2 is formed by filling a through hole with copper plating. Here, the gate electrode 5 is connected to a word line. The memory element 3 and the ground line 4 are provided on one side of the substrate 1, and the gate electrode 5 is provided on the other side. Next, as shown in FIG. 4, an aluminum oxide film is formed as a gate insulating film 6 by a sputtering method. This gate insulating film is formed selectively using a metal mask to cover the gate electrode 5. Furthermore, a gold thin film is formed as a drain electrode 7 and a source electrode 8 by a vacuum deposition method. They are selectively formed using a metal mask and the gate insulating film 6. At this time, the drain electrode 7 is connected to the bit line, and the source electrode 8 is connected to the contact 2. Secondly, as shown in Fig. 5, pentacene is vacuum deposited as an organic semiconductor layer 9. Regarding the gate insulating film 6, the organic semiconductor layer 9 uses a metal mask to cover a region between the source electrode 8 and the drain electrode 7 including a part of each electrode, that is, between the electrodes. Area and selective formation. Secondly, phenolic lacquer resin is applied and hardened as a protective film. Then, as shown in FIG. 6, the organic electrical conductor PedOT / PSS (polyethylene-dioxy-thiophene-polystyrene-sulfonic acid) is applied and dried to expand the gap between the memory element electrode 3 and the ground line 4 In particular, it covers the area between the memory element electrode 3 and the ground line and a part of them to form a memory element. Then, a protective film 12 is formed thereon. Furthermore, although it is not shown in the figure, the bit line is connected to one end of the sense amplifier (-9) (7) (7) 200402873, and compared to the reference voltage of the other end, when the bit line potential is higher than the reference voltage, Output "1" (high potential: voltage close to ground voltage), and 'output "0 when bit line potential is lower than the reference potential, (low potential: voltage close to source voltage). The following description is _ The 3 V and write operations are _ 6 v in advance, the area of the memory device manufactured. The read operation is explained first. A voltage of -2 V (that is, 2/3 of the 2 v power supply voltage) is applied to the sense amplifier as a reference voltage. ("Ref ,," in Figure 1). Secondly, the reading operation of the information in the cell C23 is performed. A voltage of -3V is applied to the word line WL3, and the selected transistor T23 is activated. Secondly, a current of 5 β A is applied to the bit line B L2 and its voltage is limited to -3V. At this time, when C23 is selected and R23 is in a low resistance state, the current flows from BL2 to T23, and to ground to cause the potential of BL2 to become close to ground. Therefore, the potential of the bit line BL2 becomes higher than the reference voltage, and the sense amplifier SA2 outputs "1". On the other hand, when R2 3 is in a high resistance state, the current flows from BL2 to T23, and the current to ground becomes extremely small, and the potential of BL2 becomes close to the power supply voltage. Therefore, the potential of the bit line BL2 becomes lower than the reference voltage, and the sense amplifier SA2 outputs "0". The write operation will be described next. It is assumed that R23 is in the low resistance state as it is in the initial state. A voltage of -3V is applied to the word line WL3, and the selected transistor T23 is activated. Secondly, a fixed current of 10 / A is applied to the bit line BL2, and its voltage is limited to -6V. At this time, when C23 is selected, a voltage higher than 5V is applied to R23, and a current of 10 // A flows. At this time, 'R23 is irreversibly converted to a high resistance state. Therefore, the information is written into C23 ° -10 · (8) (8) 200402873. In the non-volatile memory device of the present invention, the switching element may be a diode. Alternatively, the non-volatile memory device of the present invention may also use a junction type transistor as a switching element. Second Embodiment The non-volatile billion-counting device of this embodiment uses a diode as a switching element. FIG. 7 shows a configuration example of this embodiment. In this embodiment, as in the first embodiment, each cell has a switching element and a memory element. In the first embodiment, each cell has an electric crystal element as a switching element. Instead, in the second embodiment, each cell has a diode element as a switching element. As shown in Fig. 7, the non-volatile memory device of this embodiment has a plurality of cells in the row and column directions (from Cl 1 to C44). For example, taking a cell, the cell C 1 1 has a diode D 1 1 and a memory element M 1 1. One end of each memory element is connected to the diode of each cell, and the other end is commonly connected to the word line WL. There are multiple word lines WL, and they are connected to most memory elements on a row-to-row basis. One end of the diode not connected to the memory element is commonly connected to a bit line BL. There are multiple bit lines BL, and they are connected to one end of most diodes on a column-to-column basis. The read operation is explained next. For example, if cell C22 is selected and a fixed voltage Vcc is applied to BL2, the current flows to ground BL2 via resistor R2. Under this condition, a voltage not lower than Vcc is applied to the non-WL2 word line WL, so no current will flow into the cell except for the selected one. At this time, the information can be read by comparing the potential of BL2 with the reference voltage Ref. -11-0) 200402873 2Vcc status WL, so that [Figure and Main] Next, the write operation will be explained. For example, cell C22 is selected and a fixed voltage is applied to BL2, so current flows to BL2 through resistor R2. In this case, a voltage of not less than 2Vcc is applied to the non-WL2 word line. Therefore, no current will flow into the cell except for the selected one. The selected memory element D22 of C22 is applied with a large voltage ' and the impedance is changed. Brief description of the formula] Figure 丨 is a circuit diagram of the circuit structure of the first embodiment; Figure 2 is an electrical characteristic diagram of the memory element; Figure 3 is a cross-sectional view of relevant parts of the memory device of the first embodiment; Cross-sectional view of relevant parts of the memory device of the embodiment; FIG. 5 is a cross-sectional view of relevant parts of the memory device of the first embodiment; FIG. 6 is a cross-sectional view of relevant parts of the memory device of the first embodiment; FIG. 7 is a circuit diagram of a circuit configuration of the second embodiment. Component comparison table BL1—BL4 bit line WL1 — WL4 word line C11—C14 cell T11—T44 organic TFT R11-R44 memory element 1 base-12- 200402873 (10) 2 contact 3 memory element electrode 4 ground 5 gate Electrode electrode 6 Gate insulating film 7 Drain electrode 8 Source electrode 9 Organic semiconductor layer 10 Protective film 11 Organic conductive material 12 Protective film SA2 Induction amplifier

-13--13-

Claims (1)

(1) (1)200402873 拾、申請專利範圍 1 · 一種非揮發性記憶裝置，包含一矩陣接線，一開關 元件，和一記憶元件， 其中該記憶元件具有一可變阻抗，開關元件和記憶元 件包含一有機半導體元件或一有機電導體或兩者皆有。 2 ·如申請專利範圍第1項之非揮發性記憶裝置，其中 該記憶元件包含一有機電導體，其阻抗依照所施加之寫入 電壓而改變，該寫入電壓高於一讀取電壓。 3 ·如申請專利範圍第1項之非揮發性記憶裝置，其中 該記憶元件包含一有機電導體，其阻抗依照所施加之寫入 電壓而不可反向的改變，該寫入電壓高於一讀取電壓。 4 ·如申請專利範圍第1項之非揮發性記憶裝置，其中 該開關元件爲一電晶體。 5 ·如申請專利範圍第1項之非揮發性記憶裝置，其中 該開關兀件爲一二極體。 6.如申請專利範圍第4項之非揮發性記憶裝置，其中 該矩陣接線包含位元線，字線和地線，電晶體之一端連接 至位元線之一，電晶體之另一端連接至字線之一，和電晶 體之又一端經由記憶元件連接至地線之一。 7·如申請專利範圍第1項之非揮發性記憶裝置，其中 該記憶元件具有連接在基底之平面方向上分灕之兩電極之 構造。 8·如申請專利範圍第1項之非揮發性記憶裝置，其中 該矩陣接線，開關元件，和記憶元件乃形成在一樹脂或玻 -14- (2) 200402873 璃基底上。 9. 一種1C卡或1C標記，包含如申請專利範圍第8項 之非揮發性記憶裝置。 10. —種1C標記，包含如申請專利範圍第1項之非揮 發性記憶裝置。 1 1 . 一種用於根據一電子照相架構之影像形成裝置之 卡匣，包含如申請專利範圍第9項之1C卡或1C標記。(1) (1) 200402873 Patent application scope 1 · A non-volatile memory device including a matrix connection, a switching element, and a memory element, wherein the memory element has a variable impedance, a switching element and a memory element It includes an organic semiconductor element or an organic electrical conductor or both. 2. The non-volatile memory device according to item 1 of the patent application scope, wherein the memory element includes an organic electrical conductor whose impedance changes according to an applied write voltage, the write voltage being higher than a read voltage. 3. The non-volatile memory device according to item 1 of the patent application scope, wherein the memory element includes an organic electrical conductor whose impedance cannot be changed in reverse according to the applied write voltage, and the write voltage is higher than a read Take the voltage. 4. The non-volatile memory device according to item 1 of the patent application scope, wherein the switching element is a transistor. 5. The non-volatile memory device according to item 1 of the patent application scope, wherein the switch element is a diode. 6. The non-volatile memory device according to item 4 of the patent application, wherein the matrix wiring includes bit lines, word lines and ground lines, one end of the transistor is connected to one of the bit lines, and the other end of the transistor is connected to One of the word lines and the other end of the transistor are connected to one of the ground lines via the memory element. 7. The non-volatile memory device according to item 1 of the patent application scope, wherein the memory element has a structure in which two electrodes are connected in the plane direction of the substrate. 8. The non-volatile memory device according to item 1 of the patent application scope, wherein the matrix wiring, the switching element, and the memory element are formed on a resin or glass substrate. 9. A 1C card or 1C mark containing a non-volatile memory device as described in item 8 of the patent application. 10. A 1C mark containing a non-volatile memory device such as the one in the scope of patent application. 1 1. A cassette for an image forming apparatus according to an electrophotographic architecture, comprising a 1C card or a 1C mark such as item 9 of the scope of patent application. 1 2. —種用於噴墨印表機之卡匣，包含如申請專利範 圍第9項之1C卡或1C標記。1 2. A cartridge for inkjet printers, containing 1C cards or 1C marks such as those in item 9 of the patent application. -15--15-
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Families Citing this family (45)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7608855B2 (en) * 2004-04-02 2009-10-27 Spansion Llc Polymer dielectrics for memory element array interconnect
DE102004025675B4 (en) * 2004-05-26 2008-02-14 Qimonda Ag Integrated semiconductor memory with organic selection transistor
DE102004025676B4 (en) * 2004-05-26 2008-09-04 Qimonda Ag Integrated semiconductor memory with organic selection transistor
JP2006033809A (en) * 2004-06-14 2006-02-02 Semiconductor Energy Lab Co Ltd Copy machine with copy control function, scanner and facsimile, semiconductor device contained paper and semiconductor device contained film
US20080062451A1 (en) * 2004-06-14 2008-03-13 Semiconductor Energy Copy Machine with Copy Control Function, Scanner and Facsimile, and Piece of Paper and Film each Installed with Semiconductor Device
US8698262B2 (en) 2004-09-14 2014-04-15 Semiconductor Energy Laboratory Co., Ltd. Wireless chip and manufacturing method of the same
WO2006043573A1 (en) 2004-10-18 2006-04-27 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and driving method of the same
WO2006043611A1 (en) * 2004-10-22 2006-04-27 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
KR101219749B1 (en) * 2004-10-22 2013-01-21 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Semiconductor device
US7795617B2 (en) * 2004-10-29 2010-09-14 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, IC card, IC tag, RFID, transponder, paper money, valuable securities, passport, electronic device, bag, and clothes
JP4809658B2 (en) * 2004-10-29 2011-11-09 株式会社半導体エネルギー研究所 Display device and electronic apparatus using the same
US9734901B2 (en) 2004-10-29 2017-08-15 Semiconductor Energy Laboratory Co., Ltd. Display device with semiconductor memory cell
WO2006057417A1 (en) 2004-11-26 2006-06-01 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
JP4912671B2 (en) * 2004-11-26 2012-04-11 株式会社半導体エネルギー研究所 Semiconductor device
WO2006059554A1 (en) * 2004-12-03 2006-06-08 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
JP4954537B2 (en) * 2004-12-03 2012-06-20 株式会社半導体エネルギー研究所 Semiconductor device
EP1839335A4 (en) * 2005-01-21 2011-09-14 Semiconductor Energy Lab Semiconductor device
WO2006085633A1 (en) * 2005-02-10 2006-08-17 Semiconductor Energy Laboratory Co., Ltd. Memory element and semiconductor device
US8030643B2 (en) 2005-03-28 2011-10-04 Semiconductor Energy Laboratory Co., Ltd. Memory device and manufacturing method the same
US7926726B2 (en) 2005-03-28 2011-04-19 Semiconductor Energy Laboratory Co., Ltd. Survey method and survey system
JP5008323B2 (en) * 2005-03-28 2012-08-22 株式会社半導体エネルギー研究所 Memory device
TWI395321B (en) 2005-03-31 2013-05-01 Semiconductor Energy Lab Semiconductor device and driving method thereof
US7700984B2 (en) 2005-05-20 2010-04-20 Semiconductor Energy Laboratory Co., Ltd Semiconductor device including memory cell
US7688272B2 (en) 2005-05-30 2010-03-30 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US7868320B2 (en) 2005-05-31 2011-01-11 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
JP4932329B2 (en) * 2005-05-31 2012-05-16 株式会社半導体エネルギー研究所 Semiconductor device
US8188461B2 (en) 2005-05-31 2012-05-29 Semiconductor Energy Laboratory Co., Ltd. Organic memory device
US7660145B2 (en) 2005-07-01 2010-02-09 Semiconductor Energy Laboratory Co., Ltd. Storage device and semiconductor device
JP5019821B2 (en) * 2005-08-12 2012-09-05 株式会社半導体エネルギー研究所 Semiconductor device
KR101369864B1 (en) * 2005-08-12 2014-03-05 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Semiconductor device and method for manufacturing the same
JP5157448B2 (en) * 2005-10-19 2013-03-06 富士通株式会社 Resistance memory element and nonvolatile semiconductor memory device
EP1946374A4 (en) 2005-11-09 2014-01-01 Semiconductor Energy Lab Semiconductor device and manufacturing method thereof
US7566899B2 (en) * 2005-12-21 2009-07-28 Palo Alto Research Center Incorporated Organic thin-film transistor backplane with multi-layer contact structures and data lines
EP1850378A3 (en) 2006-04-28 2013-08-07 Semiconductor Energy Laboratory Co., Ltd. Memory device and semicondutor device
JP5137453B2 (en) * 2006-04-28 2013-02-06 株式会社半導体エネルギー研究所 Method for manufacturing semiconductor device
US7719001B2 (en) 2006-06-28 2010-05-18 Semiconductor Energy Laboratory Co., Ltd Semiconductor device with metal oxides and an organic compound
CN102646681B (en) 2006-10-04 2015-08-05 株式会社半导体能源研究所 Semiconductor device
EP2076923B1 (en) 2006-10-24 2012-08-15 Semiconductor Energy Laboratory Co, Ltd. Semiconductor device including storage device and method for driving the same
KR101416876B1 (en) 2006-11-17 2014-07-08 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Semiconductor device and method for manufacturing the same
US7988057B2 (en) 2006-11-28 2011-08-02 Semiconductor Energy Laboratory Co., Ltd. Memory device and semiconductor device
JP5263757B2 (en) 2007-02-02 2013-08-14 株式会社半導体エネルギー研究所 Method for manufacturing semiconductor device
US8283724B2 (en) 2007-02-26 2012-10-09 Semiconductor Energy Laboratory Co., Ltd. Memory element and semiconductor device, and method for manufacturing the same
JP5525694B2 (en) 2007-03-14 2014-06-18 株式会社半導体エネルギー研究所 Semiconductor device and manufacturing method of semiconductor device
KR101234598B1 (en) * 2011-02-28 2013-02-19 한국전자통신연구원 Read/write apparatus and method of rom cell using organic thin film transistor
KR101361690B1 (en) * 2011-07-26 2014-02-12 광주과학기술원 Switching device and resistance variable memory device using the same

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3170101B2 (en) * 1993-04-15 2001-05-28 株式会社東芝 Semiconductor device and manufacturing method thereof
JP3559580B2 (en) * 1993-12-17 2004-09-02 財団法人国際科学振興財団 Semiconductor device
US6385407B1 (en) * 1998-12-28 2002-05-07 Hitachi Maxell, Ltd. Accommodating enclosure and management system
EP1186042A1 (en) * 2000-03-28 2002-03-13 Koninklijke Philips Electronics N.V. Integrated circuit with programmable memory element

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