DE102004025676B4 - Integrated semiconductor memory with organic selection transistor - Google Patents

Abstract

integrated Semiconductor memory with a cell array of a variety of in Lines (0-n) and columns (0-m) on a substrate arranged memory cells, each one Memory element (S11, S12, S13) with two electrodes and an associated selection transistor (T11, T12, T13), wherein the control electrodes of the selection transistors of the individual lines by word lines running in the row direction (x) (WL0, WL, WL2) and a controlled electrode of the selection transistors (T11, T12, T13) of the individual columns either with one in the column direction (y) current bit line (BL1, BL2, BL3) or with a digit line (DL1, DL2, DL3) or with a field plate (FP) is connected and one electrode of each memory element (S11, S12, S13) with the other controlled electrode of the associated Selection transistor (T11, T12, T13) and the other electrode each Memory element (S11, S12, S13) either with a bit line (BL1, BL2, BL3) of a digit line (DL1, DL2, DL3) or a field plate (FP), each memory cell (S11, S12, S13) being connected as Storage element an organic storage element (S) ...

Description

The invention relates to an integrated semiconductor memory according to the preamble of claim 1. Such an integrated semiconductor memory is off WO 03/052827 A1 with the English version of the US 2004/0196688 A1 known.

• 1. Arbeitsspeicher mit extrem kurzen Zugriffszeiten, wie sie heute in enormem Umfang in Computern zur Anwendung kommen, werden fast ausschließlich auf der Grundlage flüchtiger Speicherarchitekturen („volatile memory"), insbesondere in der DRAM-Technologie („dynamic random access memory") gefertigt. Die DRAM-Technologie beruht auf der Speicherung elektronischer Ladungen in einem kapazitiven Speicherelement, also in einem Kondensator. Jede Speicherzelle repräsentiert eine Speichereinheit („bit") und wird durch einen Kondensator und einen Auswahltransistor (einen Feldeffektransistor, FET) gebildet. Aufgabe des Auswahltransistors ist die elektrische Isolation der einzelnen Speicherzellen voneinander und von der Peripherie des Zellenfeldes; durch Schalten des jeweiligen Auswahltransistors kann auf jede beliebige Zelle gezielt und einzeln zugegriffen werden („random access"). Die DRAM-Architektur zeichnet sich durch extrem geringen Platzbedarf (weniger als ein Quadratmikrometer pro Speicherzelle) und extrem geringe Fertigungskosten (weniger als 10^–8 Euro pro Speicherzelle) aus. Entscheidender Nachteil des DRAM-Konzepts ist die Flüchtigkeit der gespeicherten Information, da die im Kondensator gespeicherte Ladung so klein ist (weniger als 500.000 Elektronen), dass sie bei Abschalten der Versorgungsspannung nach kurzer Zeit (innerhalb weniger Millisekunden) aufgrund von Leckströmen innerhalb des Zellenfeldes verloren geht.
• 2. Nichtflüchtige Speicher ("nonvolatile memory"), die die gespeicherte Information auch nach Abschalten der Versorgungsspannung über lange Zeiträume (mehrere Jahre) nicht verlieren, sind für ein breites Spektrum von Anwendungen (Digitalkameras, Mobiltelefone, mobile Navigationsinstrumente, Computerspiele, usw.) von Interesse und könnten auch den Umgang mit Computern revolutionieren, da ein Hochfahren des Computers nach dem Einschalten unnötig würde ("instant-on computer"). Zu den bereits existierenden nichtflüchtigen Speichertechnologien gehören die so genannten Flash-Speicher, bei denen die Information in Form elektronischer Ladungen im Gate-Dielektrikum eines Silizium-Feldeffekttransistors gespeichert und als Änderung der Schwellspannung des Transistors detektiert wird. Da die elektronische Ladung im Gate-Dielektrikum des Transistors "gefangen" ist, geht sie auch bei Abschalten der Versorgungsspannung nicht verloren. Ein wesentlicher Nachteil der Flash-Technologie sind die relativ hohen Schreib- und Lösch-Spannungen, die sich aus der Notwendigkeit ergeben, die zu speichernde elektronische Ladung sicher und reproduzierbar in das Gate-Dielektrikum zu injizieren bzw. von dort wieder abzuziehen. Weitere Nachteile sind die im Vergleich zum DRAM deutlich längeren Zugriffszeiten sowie die aufgrund der hohen Belastung des Gate-Dielektrikums beim Schreiben und Löschen beschränkte Zuverlässigkeit.
• 3. Aufgrund der oben genannten Nachteile von Flashspeichern werden seit mehreren Jahren neue Technologien für nichtflüchtige Halbleiterspeicher auf der Grundlage diverser physikalischer Konzepte entwickelt. Dazu gehören die ferroelektrischen und die magnetoresistiven Speicher, bei denen die gespeicherte Information als Änderung der elektrischen Polarisation (aufgrund der Verschiebung des Zentralatoms in einem Perovskit-Kristall) bzw. als Änderung eines elektrischen Widerstands in einer Anordnung ferromagnetischer Schichten ausgelesen wird. Für die Integration ferroelektrischer Speicherelemente ist die Verwendung eines Auswahltransistors (ähnlich der DRAM-Speicherzelle) zwingend notwendig, um das sichere Auslesen der gespeicherten Informationen zu gewährleisten. Magnetoresistive Speicher können prinzipiell ohne Auswahltransistor integriert werden, da eine Isolation der einzelnen Speicherelemente nicht unbedingt notwendig ist. Dabei hat die Implementierung von Zellen ohne Auswahltransistor den wesentlichen Vorteil eines deutlich geringeren Platzbedarfs, was zu einer deutlich höheren Integrationsdichte und einem niedrigeren Fertigungsaufwand pro Zelle führt. Allerdings wird das Auslesen der gespeicherten Information durch die Verwendung eines Auswahltransistors erheblich einfacher und sicherer, und es ist abzusehen, dass den ersten magnetoresistiven Speicherprodukten ein Aufbau mit Auswahltransistor zugrunde liegen wird.

The semiconductor memory market is currently served by a relatively manageable number of products:

• 1. Memory with extremely short access times, as they are today used in enormous amounts in computers, are manufactured almost exclusively on the basis of volatile memory architectures ("volatile memory"), in particular in the DRAM technology ("dynamic random access memory") , The DRAM technology is based on the storage of electronic charges in a capacitive storage element, ie in a capacitor. Each memory cell represents a memory unit ("bit") and is formed by a capacitor and a selection transistor (a field effect transistor, FET) .The purpose of the selection transistor is to electrically insulate the individual memory cells from each other and from the periphery of the cell array by switching the respective selection transistor Any cell can be specifically and individually accessed ("random access"). The DRAM architecture is characterized by extremely small footprint (less than one square micrometer per memory cell) and extremely low manufacturing costs (less than 10 ^-8 euros per memory cell). The key drawback of the DRAM concept is the volatility of the stored information, since the charge stored in the capacitor is so small (less than 500,000 electrons) that it will be lost after a short time (within a few milliseconds) due to leakage currents within the cell field when the supply voltage is switched off goes.
• 2. Nonvolatile memories, which do not lose the stored information even after disconnecting the supply voltage for long periods of time (several years), are suitable for a wide range of applications (digital cameras, mobile phones, mobile navigation instruments, computer games, etc.). Of interest and could also revolutionize the use of computers, since a start-up of the computer after switching would be unnecessary ("instant-on computer"). The existing non-volatile memory technologies include the so-called flash memory, in which the information is stored in the form of electronic charges in the gate dielectric of a silicon field effect transistor and detected as a change in the threshold voltage of the transistor. Since the electronic charge is "trapped" in the gate dielectric of the transistor, it is not lost even when the supply voltage is switched off. A major disadvantage of the flash technology is the relatively high write and erase voltages that result from the need to safely and reproducibly inject the electronic charge to be stored into the gate dielectric or to withdraw it therefrom. Other disadvantages are the significantly longer access times compared to the DRAM and the limited reliability due to the high loading of the gate dielectric during write and erase.
• 3. Due to the above-mentioned disadvantages of flash memories, new technologies for non-volatile semiconductor memories based on various physical concepts have been developed for several years. These include the ferroelectric and the magnetoresistive memories, in which the stored information is read out as a change in the electrical polarization (due to the shift of the central atom in a perovskite crystal) or as a change in an electrical resistance in an arrangement of ferromagnetic layers. For the integration of ferroelectric memory elements, the use of a selection transistor (similar to the DRAM memory cell) is absolutely necessary in order to ensure safe reading of the stored information. Magnetoresistive memory can in principle be integrated without a selection transistor, since an isolation of the individual memory elements is not absolutely necessary. The implementation of cells without a selection transistor has the significant advantage of a significantly smaller footprint, resulting in a significantly higher integration density and a lower production cost per cell. However, reading the stored information becomes much easier and safer through the use of a select transistor, and it is anticipated that the first magnetoresistive memory products will be based on a select transistor design.

The above-mentioned storage concepts are exclusively produced or developed on silicon platforms, that is, the production of the storage elements takes place exclusively on silicon substrates ("silicon wafers") and exclusively by using transistors based on silicon as semiconductors. Alternatively, both memory concepts and transistor designs are currently being developed that do not require the use of silicon wafers, and which in principle enable the fabrication of mass storage devices on inexpensive glass substrates and even on flexible polymer films. Such novel mass storage devices are of interest for a variety of applications, principally for all users applications for which the ferroelectric and magneto-resistive memories are being developed, as well as for applications in which the use of silicon substrates adversely affects the cost or the possible uses.

The enclosed 1a - 1f show six possible circuit diagrams of an optional volatile or nonvolatile memory cell with an optional capacitive, resistive or based on another physical concept storage element S and a selection transistor T.

The six in the 1a - 1f The diagrams shown differ in the arrangement and interconnection of each of the memory element S and the selection transistor T with a word line WL, a bit line BL, a digit line DL and a field plate FP. It should be noted here that in the 1a - 1f Basic circuits of a memory element with a selection transistor are known per se in the prior art:

1a shows that the drain terminal of the selection transistor T to the bit line BL and the memory element S between the source of the selection transistor T and a field plate FP is located.

According to 1b the drain terminal of the selection transistor T is connected to the bit line BL and the memory element is connected between the source terminal of the selection transistor T and a digit line DL which is connected in parallel with the word line WL.

According to 1c the drain terminal of the selection transistor T is connected to the bit line BL and the memory element S is connected between the source terminal of the selection transistor T and a digit line DL, which runs parallel to the bit line BL.

According to 1d the source terminal of the selection transistor T is connected to a field plate FP and the memory element S is connected between the drain terminal of the selection transistor T and the bit line BL.

1e shows that the source terminal of the selection transistor T on a digit line DL and the memory element S between drain of the selection transistor T and the bit line BL, wherein the digit line DL is parallel to the word line WL.

According to 1f the source terminal of the selection transistor T lies on a digit line and the memory element S between the drain terminal of the selection transistor T and the bit line BL, wherein the digit line DL runs parallel to the bit line BL.

The Selection of the memory cell S always takes place via the word line WL, the in any case connected to the gate electrode of the selection transistor T. is. By applying a suitable potential to the word line WL (eg, a negative potential when connected to the select transistor T is a p-type Transistor with negative threshold voltage) becomes the selection transistor T is open (electrically conductive) and stored in the memory element S information can by applying suitable potentials to bit line BL and digit line DL or field plate FP via the bit line is read out in a read cycle or in a write cycle. or erase cycle changed become.

A execution the memory cell with a digit line DL has compared to a version with a field plate FP has the advantage of having the potential on this line targeted for the cell will be changed which is currently being accessed. An embodiment of an integrated semiconductor memory with field plate FP can lead to a smaller space requirement of the cell field to lead.

An essential criterion in the realization of the memory cells is the bit line capacity, which should be as small as possible in the interests of fast access times. Depending on whether the capacitance associated with the selection transistor T is greater or smaller than the capacitance associated with the memory element S, either the embodiments according to FIGS 1a - 1c (Where the selection transistor T is located on the bit line BL) or the embodiments according to the 1d - 1f (Where the memory element S between bit line BL and drain of the selection transistor T is located) on the lower bit line capacity.

2a shows a highly simplified circuit diagram of a cell array of an integrated semiconductor memory, according to 1b is executed. That is, in the memory cells, the drains of the select transistors T01-T0m (one row 0) on the bit lines BL0-BLm and the memory elements S01-S0m (the row 0) each between the source of the select transistor (T01-T0m) and the digit line DL0 lie. The digit line DL0 runs parallel to the word line WL0 (for simplicity, in 2a only provide the selection transistors and the memory elements of a 0th row with reference numerals). 2 B shows a highly simplified circuit diagram of a cell array according to 1f is executed. In this embodiment, the source terminals of the selection transistors T01-T0m are at digit lines DL0-DLm, and the memory elements S01-S0m are each between the drain terminal of the selection transistor and the associated bit line BL0-BLm. The digit lines DL0-DLm are parallel to the bit lines BL0-BLm. Again, for simplicity, only the selection transistors and the memory elements of the 0-th row provided with reference numerals. Of course they give 2a - 2 B only a section of a m column (bit lines) and n lines (word lines) existing cell array again. The row direction is designated by x and the column direction by y.

3 shows a highly simplified circuit diagram of an existing m columns and n rows cell array, which is implemented with common bit lines ("shared bit lines"). In this embodiment, the memory cells of the first, third, fifth, etc. columns are offset from the memory cells of the zeroth, second, fourth column (y-direction) by one line at a time. The circuit arrangement of the memory elements and the selection transistors corresponds to the arrangement according to 2 B in which the digit lines DL0, DL1 are replaced by bit lines BL1, BL3 and so on.

The above based on the 1 described, known from the prior art circuit diagrams of volatile or nonvolatile memory cells with optional capacitive, resistive or based on another physical concept storage elements and each a selection transistor and the basis of the 2a . 2 B and 3 described circuit diagrams of differently executed cell fields, which are also known in the art, serve as a basis for circuit arrangements of an integrated semiconductor memory according to the invention.

In a cited in the preamble of claim 1 cited above with reference to the 12 to 17 described embodiment of the non-volatile integrated semiconductor memory according to the preamble of claim 1 is the consisting of an organic active layer, a source electrode and a contact electrode storage element in a plane with the drain electrode and the organic semiconductor layer and the source of the running as a field effect transistor selection transistor, and only its gate electrode is located in a lower layer on the substrate, ie below the level of the other integrated elements of the selection transistor and the memory element. In addition, the cross section in 12A document that the memory element and the selection transistor of the known non-volatile semiconductor integrated memory have no planar structure. Also with another in 26 This embodiment of the known non-volatile integrated semiconductor memory shown in this document are the integrated elements of the memory element and the selection transistor except the gate electrode provided above substantially in one plane, ie that in this embodiment of the known non-volatile integrated semiconductor memory, the organic active layer not is located in the thickness direction of the device between an upper and lower memory element electrode and the lower electrode does not lie directly on the substrate, but forms a contact plug to a horizontally extending select line at the electrode of the selection transistors of the individual columns either with a bit line running bit line or is connected to a digit line or to a field plate and an embodiment of the 26 this document extends below the memory element and the selection transistor. It turns out that in the known non-volatile semiconductor integrated memory to the input based on the 1a - 1f . 2a . 2 B and 3 described circuit variants in an integrated form with the help of the integration methods described in the document and arrangements to realize the integration steps in the manufacturing process according to the circuit variants would have to be changed.

It is an object of this invention to provide a concept for an integrated semiconductor memory, which can be realized without silicon substrate and its memory cells optionally capacitive, resistive or based on another physical concept storage elements, in particular non-volatile memory elements based on an organic material and a Include the basis of an organic semiconductor layer realized selection transistor in such a way that, without changing the basic way of integration, in the 1a - 1f . 2a . 2 B and 3 described memory circuit variants can be realized.

These Task is solved according to the claim.

Accordingly, an integrated semiconductor memory having a cell array of a plurality of arranged in rows and columns on a substrate memory cells, each having a memory element with two electrodes and an associated selection transistor, wherein the control electrodes of the selection transistors of the individual lines by running in the line direction word lines and a controlled electrode of each memory element is connected to the other controlled electrode of the associated selection transistor and the other electrode of each memory element is connected to either a bit line, a digit line or a field plate, each memory cell having as memory element an organic memory element with an organic active layer arranged between the two electrodes as a selection transistor has a field effect transistor with an organic semiconductor layer, which is integrated in an inverse-coplanar arrangement, wherein the organic semiconductor layer above arrive outside the gate electrode is arranged and the source and drain contact are in direct contact with the gate dielectric, characterized in that seen in the thickness direction of the integrated semiconductor memory, the two electrodes of the organic memory element form a directly lying on the substrate lower electrode and an upper electrode, wherein the lower electrode and the upper electrode overlap at least partially in the lateral direction, and the organic active layer is in the thickness direction between the two electrodes, and the selection transistors and the memory elements on the support substrate both have a planar structure and are integrated laterally side by side in a plane.

at an integrated semiconductor memory according to the invention The substrate does not need to be a silicon substrate, but can be made Glass, a polymer film, a metal foil coated with an insulating layer or also made of paper and other substrates that are not silicon contain.

at an embodiment have the gate electrode of the selection transistor and the lower electrode of the memory element on the same material. In a variant of the embodiment consist of the gate electrode of the selection transistor and the lower Electrode of the memory element respectively made of different materials.

In Preferred embodiment, the embodiment can be designed be that the source and drain electrodes of the selection transistor and the upper electrode of the memory element have the same material.

In In an alternative advantageous embodiment, the source and drain electrodes the selection transistor on the one hand and the upper electrode of the memory element on the other hand consist of different materials.

Advantageously, with the preferred exemplary embodiments described below in detail and their variants of an integrated semiconductor memory according to the invention, all of them can be described above with reference to FIGS 1a - 1f . 2a . 2 B and 3 implemented circuit variants realize integrated semiconductor memory.

Consequently describes the description below with reference to the drawing preferred embodiments and their variants of an integrated semiconductor memory according to the invention. The Drawing figures show in detail:

1a to 1f the already described at the beginning six circuit diagrams of an optional volatile or non-volatile memory cell with an optional capacitive or resistive memory element and a selection transistor;

2a and 2 B highly simplified circuit diagrams of two cell fields consisting of m x n memory cells each executed according to the 1b respectively. 2f (already described at the beginning);

3 a simplified circuit diagram of a cell array, carried out with common bit lines (already described at the beginning);

4a - 4f schematic cross sections through differently designed memory cells according to the invention 1a - 1c ,

5a - 5e schematic cross sections through differently shaped memory cells according to the invention according to the 1e and 1f ;

6 a schematic layout view of a section of a cell array with memory cells according to the invention according to the 1b . 2a and 4b with a W / L ratio of the select transistor of FIG. 1;

7 a schematic layout layer of a section of a cell array with memory cells according to the invention according to the 1b . 2a and 4b with a W / L ratio of the selection transistor of about 10.

8th a schematic layout view of a section of a cell array with memory cells according to the invention according to the 1f . 2 B and 5c with a W / L ratio of the select transistor of FIG.

9 a schematic layout view of a section of a cell array with memory cells according to the invention according to the 1f . 2 B and 5c with a W / L ratio of about 10, and

10 a schematic layout view of a section of a cell array with memory cells according to the invention according to the 1c . 3 and 4f with a W / L ratio of the select transistor of FIG.

In the schematic cross sections of memory cells of a semiconductor memory according to the invention performing 4a - 4f is the memory element and the selection transistor of each memory cell with S and T, the bit line with BL, the word line with WL, the field plate with FP, the gate dielectric with GD, the organic semiconductor layer of the field effect transistor T with os and the organic active layer of the memory element S. denoted by as. The selection transistors T all in the 4a - 4f Variants shown are integrated in an inverse-coplanar arrangement, in which the organic semiconductor layer is arranged os of the selection transistor T above its gate electrode and its source and drain electrode each in direct contact with the gate dielectric GD.

4a shows a schematic cross section of the consisting of the memory element S with the organic active layer as and the selection transistor T with the organic active layer as planar planar memory cell according to the in 1a shown circuit with a field plate FP, which is here the lowest metal layer (metal-0). The field dielectric FD forms an insulation between the different metal layers, ie the field plate FP and the source / drain contacts and the upper electrode of the memory element S. 4a shows that the source / drain contacts of the selection transistor T can be made of the same material as the upper electrode of the memory element S. This also applies to the variants according to FIGS 4b and 4c to.

4b shows a schematic cross-section of an embodiment of the invention in 1b shown circuit of a planar memory cell using the same material for the realization of each of the gate electrode of the selection transistor T and the lower electrode of the memory element S and therefore necessarily with a parallel to the word line WL led digit line DL.

4c shows a schematic cross-section of an embodiment of the invention in the 1b and 1c shown circuits of a planar memory cell using two different materials for the realization of each of the gate electrode of the selection transistor T and the lower electrode of the memory element S and therefore with an optionally parallel to the word line WL or parallel to the bit line BL executed digit line DL.

4d shows a schematic cross-section of an embodiment of the invention in the 1b and 1c shown circuits of a planar memory cell using two different materials for the realization of each of the gate electrode of the selection transistor T and the upper electrode of the memory element S and therefore with an optionally parallel to the word line WL or parallel to the bit line BL executed digit line DL. In contrast, the lower electrode of the memory element S may comprise the same material as the drain / source contacts of the selection transistor T.

4e shows a schematic cross-section of an embodiment of the invention in the 1b and 1c shown circuits of a planar memory cell using four different materials respectively for the realization of each of the gate electrode and the source and drain contacts of the selection transistor T and the upper and lower electrode of the memory element S and therefore with an optional parallel to the word line WL or parallel to the bit line BL executed digit line DL.

4f shows a schematic cross-section of an embodiment of the invention in the 1b and 1c shown circuits of a planar memory cell using the same material for the realization of the gate electrode of the selection transistor T and the lower electrode of the memory element S, but with the ability to lead the digit line DL either parallel to the word line WL or parallel to the bit line or with the possibility of second bit line. Therefore, the embodiment is according to 4f particularly suitable for the realization of a cell array with common bit lines according to 3 ,

The 5a - 5e each show in schematic cross-section according to the invention executed memory cells according to the circuits in the 1e and 1f , Also in the in the 5a and 5e illustrated planar memory cells of the selection transistor T is integrated in an inverse-coplanar arrangement. The reference numerals are in the 5a - 5e the same as you in the 4a - 4f were used. The digit line DL is in the embodiments according to the 5a - 5e optionally parallel to the word line WL or parallel to the bit line BL out. According to 5a For example, the source / drain electrode of the selection transistor T may be made of the same material as the upper electrode of the memory element S. 5b For example, the upper electrode of the selection transistor T may be made of the same material as the lower electrode of the memory element S. The bit line BL is in all embodiments according to FIGS 5b - 5e in an upper metallization layer and the word line WL always in a lowermost metal layer (metal-0). In the execution according to 5a the bit line is also in the lowest metal layer (metal-0).

All in the 4a - 4f and 5a - 5e shown embodiments of planar semiconductor memory cells according to the invention are suitable for the realization of a cell array of a plurality of arranged in rows and columns on a substrate planar memory cells, each having a memory element S with an associated in the same level adjacent selection transistors T, wherein the control electrodes of the selection transistors of the individual rows by word lines WL running in the row direction and a controlled electrode of the selection transistors T of the individual columns, either with an in column direction current bit line BL or a digit line DL or a field plate FP and an electrode of each memory element to the other controlled electrode of the associated selection transistor T and the other electrode of each memory element S either with a bit line BL or with a digit line DL or with a Field plate FP is connected. In the integrated semiconductor memory according to the invention, each memory cell has an organic memory element S with an organic active layer as arranged between the two electrodes and a selection transistor T consisting of a field effect transistor with an organic semiconductor layer os, the selection transistors T and the memory elements S on the substrate does not have to be silicon, integrated as planar elements and arranged laterally side by side in one plane.

• 1. Metall-0 (DL bzw. FP bzw. DL; untere Elektrode des Speicherelements)
• 2. Metall-1 (WL und Gateelektrode des Auswahltransistors T; gegebenenfalls DL bzw. untere Elektrode des Speicherelements);
• 3. Felddielektrikum FD (Isolation der verschiedenen Metalllagen);
• 4. Gatedielektrikum GD (Isolation zwischen Gateelektrode und Halbleiterschicht des Auswahltransistors T);
• 5. Aktive Schicht as des Speicherelements S;
• 6. Metall-2 (Bitleitung BL bzw. Digitleitung DL, Source- und Drainkontakte des Auswahltransistors T; obere bzw. gegebenenfalls untere Elektrode des Speicherelements S);
• 7. Organische Halbleiterschicht os des Auswahltransistors T;
• 8. Metall-3 (BL bzw. DL, obere Elektrode des Speicherelements).

The realization of in the 4a - 4f and 5a - 5e shown embodiments of the invention memory cells requires the deposition and patterning of the following functional layers on the (not shown) substrate. In the following list, optional layers are written in italics.

• 1. Metal-0 (DL or FP or DL, lower electrode of the memory element)
• 2. metal-1 (WL and gate electrode of the selection transistor T, optionally DL or lower electrode of the memory element);
• 3. field dielectric FD (insulation of the different metal layers);
• 4. gate dielectric GD (insulation between gate electrode and semiconductor layer of the selection transistor T);
• 5. Active layer as of the memory element S;
• 6. metal 2 (bit line BL or digit line DL, source and drain contacts of the selection transistor T, upper or possibly lower electrode of the memory element S);
• 7. Organic semiconductor layer os of the selection transistor T;
• 8. Metal-3 (BL or DL, upper electrode of the memory element).

When Substrate are for example glass, polymer film, metal foil (coated with an insulating layer), paper and other materials. Especially Although the use of silicon as a substrate is possible, though unnecessary. The layers metal-0, metal-1, metal-2 and Metal 3 need be metallically conductive, so by deposition of inorganic metals (For example, aluminum, copper, titanium, gold), conductive oxides (for example indium tin oxide), or conductive polymers (for example Polyaniline) are generated. The gate dielectric and the field dielectric have to have good insulator properties; these are both inorganic Insulators, such as silica and alumina, but in particular also insulating polymers, such as polyvinylphenol suitable. As organic semiconductor layer os for the selection transistor T come a range of materials in question, especially pentacene, diverse Oligothiophene and polythiophene. For execution of the active layer as the memory element S are currently a number of Ansät zen both for capacitive as well as for resistive memory effects discussed.

All in the 4 and 5 illustrated preferred embodiments of inventive memory cells use a planar structure, that is, the memory element and the selection transistor are adjacent to each other in a plane integrated on the substrate. In comparison with a vertical structure in which the memory element and the selection transistor-at least partially-are superposed, the planar structure has the advantage that it is much easier to realize from a technological point of view.

All in the 4 and 5 shown memory cells use a selection transistor, which is manufactured in inverse-co-planar ("inverted co-planar") execution. In the inverse-coplanar design, the organic semiconductor layer os is disposed above (above the gate electrode) (inverse to the ordinary silicon field-effect transistor in which the gate electrode is disposed at the top), and the source and drain contacts are in direct contact with the gate dielectric GD (FIG. In contrast to the staggered design, where the semiconductor layer is between the gate dielectric and the source / drain contacts, the inverse coplanar design is the most commonly used design for organic transistors, but in principle all can be used in 1 illustrated circuits in memory cells according to the invention also realize with organic selection transistors in any other construction.

An important criterion in the execution of the memory cell is the question of whether the same material is used for the realization of the gate electrode of the selection transistor T and the lower electrode of the memory element S, or whether two different materials are used. In principle, the realization of the memory cell is simpler if the same material (metal-1 in FIG. 2) is used for the gate electrode of the selection transistor and the lower electrode of the memory element 4b and 5c ) is used, since in this case only one process step becomes necessary for the realization of both structures. In certain cases, however, it may be necessary to carry out the gate electrode of the selection transistor T and the lower electrode of the memory element S with two different materials. For example, in the literature, resistive Memory is discussed which requires the use of very specific materials for the lower electrode of the memory element, such as copper or indium tin oxide. Depending on the design of the selection transistor (in particular, depending on the choice of material for the gate dielectric) such materials may be unsuitable for the realization of the gate electrode of the selection transistor and therefore the use of two different materials (metal-O, optimized for the realization of the lower electrode of the memory element; Metal-1, optimized for the realization of the gate electrode of the selection transistor, see 4a . 4c . 4e . 5a . 5d and 5e ). Similar considerations apply to the choice of materials for the realization of the source and drain contacts of the select transistor and the upper electrode of the memory element. In principle, the realization of the memory cell is easier if the same material (metal-2 in 4a . 4b . 4c . 5a . 5d . 5d ), but in some cases it may be necessary to use two different materials. Also in this case, those in the 4 respectively. 5 slightly modified.

6 shows in the form of a schematic layout representation of a section of a cell array according to the invention of planar memory cells with circuit arrangements according to the 1b and 2a and a cross-sectional structure according to 4b , The illustrated cell array consists of nine cells organized in three columns (bit lines BL1, BL2, BL3) and three rows (word lines WL1, WL2, WL3) and three digit lines (DL1, DL2, DL3). The selection transistors of a first row of the cell array are respectively denoted by T11, T12, T13 and the associated laterally in the same level integrated memory elements of the first row of the cell array are each denoted by S11, S12 and S13.

An important criterion in the execution of memory cells is the ratio W / L of the channel width W to the channel length L of the selection transistor, the so-called W / L ratio. This W / L ratio of the selection transistor decisively determines its electrical resistance, that is, the current flowing through the transistor at a certain combination of gate-source voltage and drain-source voltage (the current is proportional to the W / L ratio). L-ratio). In the in 6 As shown, the W / L ratio of the selection transistors is approximately equal to 1. That is, W = L. In principle, the illustrated design allows the realization of any desired W / L ratio. This is how the layout view of the 7 a section of a cell array according to the invention of planar memory cells in the circuit arrangements according to the 1b and 2a and with the cross-sectional structure of 4b in which the W / L ratio of the selection transistor is about 10. The displayed cell field consists, as already in 6 nine memory cells organized in three rows and three columns. The channel width W is approximately equal to the length of the inner contour of the drain contact D, that is, approximately 2a + b, and the channel length is approximately equal to the distance between the drain contact D and the source contact S.

The 8th and 9 show schematic layout representations of two cell arrays of planar memory cells according to the invention according to the circuit arrangements of 1f and 2 B and the cross-sectional structure according to 5c , wherein the selection transistors in 8th a W / L ratio of about 1 and in 9 have a W / L ratio of about 10. Also the 8th and 9 represent a cell array of nine memory cells organized in three columns and three rows. The selection transistors of a first row (WL1) are respectively denoted by T11, T12, T13 and the memory elements of that row are respectively denoted by S11, S12 and S13.

Finally, the layout view shows the 10 schematically a cell array with inventive planar memory cells, the circuits according to the 1c and 3 realize and the cross-sectional structure according to 4f to have. The W / L ratio of the selection transistors is 1.

In principle, each circuit according to the 1a - 1f and each in the cross-sectional illustrations of 4a - 4f and 5a - 5e illustrated embodiments of the memory cells according to the invention with any W / L ratio of the selection transistors are realized, so that in the 6 - 10 shown layouts are only examples.

The following is an example of a process for the realization of the in the layout of 6 illustrated cell array explained. According to the in 6 illustrated preferred embodiment of an integrated semiconductor memory according to the invention is made for each of the six functional layers to be structured, that is metal-1, active layer as the memory element S, field dielectric FD, gate dielectric GD, metal-2 and organic semiconductor layer os of the selection transistor T a chrome mask, which allows the structuring of the deposited layers by means of photolithographic processes.

On a substrate, for example of glass, an approximately 30 nm thick layer of aluminum is applied by thermal evaporation, which is patterned by means of photolithography and wet chemical etching in aqueous potassium hydroxide solution to the first metal layer (metal-1; selection transistor T; lower electrode of the memory element S; Word line WL).

in the the second step becomes the active layer as of the memory element (S) For example, a polymer that can be modified by a specifically electrical resistance is characterized, deposited and structured. To generate the field dielectric FD, one of a suitable organic solvents (For example, propylene glycol monomethyl ether acetate, PGMEA) a layer about 300 nm thick Spun on polyvinylphenol, thermally (at about 200 ° C) crosslinked and by photolithography and etching structured in an oxygen plasma.

following the gate dielectric GD is defined, for example by spin coating and photolithographically patterning an approximately 100 nm thick layer Polyvinylphenol or by applying an approximately 3 nm thick electrically isolating molecular self-assembling monolayer (self assembling mono layer "; SAM).

in the next Step is deposited by about 30 nm thick gold layer and using Photolithography and wet chemical etching the second metal layer (Metal 2, source and drain contacts of the selection transistor T; BL).

When Organic semiconductor layer os of the selection transistor is finally a about 30 nm thick layer of pentacene evaporated and by photolithography (with the aid of a water-soluble photoresist) and structured plasma etching.

Summarized the invention gives a semiconductor memory in which an organic Selection transistor, that is a field effect transistor having an organic semiconductor layer together with an organic storage element, that is one between two electrodes arranged organic active layer with optional capacitive, resistive or on a different physical concept based electrical storage behavior together to a planar Memory cell on any substrate, which preferably not made of silicon, to be integrated. This is especially valuable placed so that selection transistor and memory element arranged so are that the gate electrode of the transistor as the word line and the drain or source contact of the transistor or the electrodes the memory element either as a bit line, digit line or Field plate executed are.

as

active Layer of the memory element

os

organic Layer of the selection transistor

BL, BL0-BLm

bit

DL, DL0-DLm

digit lines

WL WL0-WLm

word lines

S, S11, S12, S13, S01, S02, S03-S0m

storage elements

T T11, T12, T13, T01-T0m

select transistors

DG

gate dielectric

FP

field plate

S, D

source, drain

a, b

Side lengths of the drain contact

W

channel width

L

channel length

x, y

row, column direction

Claims (16)

Integrated semiconductor memory comprising a cell array comprising a multiplicity of memory cells arranged in rows (0-n) and columns (0-m) on a substrate, each having a storage element (S11, S12, S13) with two electrodes and an associated selection transistor (T11, T12, T13), wherein the control electrodes of the selection transistors of the individual rows by word lines (WL0, WL, WL2) running in the row direction (x) and a controlled electrode of the selection transistors (T11, T12, T13) of the individual columns either with a column direction (Y) is connected to the current bit line (BL1, BL2, BL3) or to a digit line (DL1, DL2, DL3) or to a field plate (FP) and one electrode of each memory element (S11, S12, S13) to the other controlled electrode of the associated selection transistor (T11, T12, T13) and the other electrode of each memory element (S11, S12, S13) either with a bit line (BL1, BL2, BL3) of a digit line (DL1, DL2, DL3) or a Field memory (FP) is connected, wherein each memory cell (S11, S12, S13) as a memory element, an organic memory element (S) with an arranged between the two electrodes organic active layer (as) and as a selection transistor (T11, T12, T13) a field effect transistor (T) having an organic semiconductor layer (os) integrated in an inverse-coplanar arrangement, the organic semiconductor layer (os) being arranged above the gate electrode and the source and drain contacts being in direct contact with the gate dielectric, characterized that seen in the thickness direction of the integrated semiconductor memory, the two electrodes of the organic memory element (S) one directly on the sub strat lying lower electrode and an upper electrode, wherein the lower electrode and the upper electrode overlap at least partially in the lateral direction and the organic active layer (as) in the thickness direction between the two electrodes, and the selection transistors (T11, T12, T13) and the storage elements (S11, S12, S13) on the substrate both have a planar structure and are integrated laterally next to one another in a plane. Integrated semiconductor memory according to Claim 1, characterized in that the substrate is not a silicon substrate is. Integrated semiconductor memory according to claim 1 or 2, characterized in that the substrate consists of glass. Integrated semiconductor memory according to claim 1 or 2, characterized in that the substrate comprises a polymer film. Integrated semiconductor memory according to claim 1 or 2, characterized in that the substrate is coated with an insulating layer Metal foil is. Integrated semiconductor memory according to claim 1 or 2, characterized in that the substrate consists of paper. Integrated semiconductor memory according to one of claims 1 to 6, characterized in that the gate electrode of the selection transistors (T11, T12, T13) and the lower electrode of the memory elements (S11, S12, S13) have the same material. Integrated semiconductor memory according to one of claims 1 to 6, characterized in that the gate electrode of the selection transistors (T11, T12, T13) and the lower electrode of the memory elements (S11, S12, S13) each have different materials. Integrated semiconductor memory according to one of claims 1 to 8, characterized in that the source and drain contact of Selection transistors (T11, T12, T13) and the upper electrode of the Memory elements (S11, S12, S13) have the same material. Integrated semiconductor memory according to one of claims 1 to 8, characterized in that the source and drain contact of Selection transistors (T11, T12, T13) and the upper electrode of the memory elements (S11, S12, S13) each have different materials. Integrated semiconductor memory according to one of the preceding Claims, characterized in that the drain contact of the selection transistor (T) on the bit line (BL) and the memory element (S) between the source contact of the selection transistor (T) and the field plate (FP) is located. Integrated semiconductor memory according to one of claims 1 to 10, characterized in that the drain contact of the selection transistor (T) on the bit line (BL) and the memory element (S) between the source contact of the selection transistor (T) and the parallel to Word line extending digit line (DL) is located. Integrated semiconductor memory according to one of claims 1 to 10, characterized in that it drain contact of the selection transistor (T) on the bit line (BL) and the memory element (S) between the source contact of the Auswahltransistora (T) and the parallel to Bit line (BL) extending digit line (DL) is located. Integrated semiconductor memory according to one of claims 1 to 10, characterized in that the source contact of the selection transistor (T) on the field plate (FP) and the memory element (S) between the drain contact of the selection transistor (T) and the bit line (BL) lies. Integrated semiconductor memory according to one of claims 1 to 10, characterized in that the source contact of the selection transistor (T) on the digit line (DL) and the memory element (S) between the drain contact of the selection transistor (T) and the bit line (BL) where the digit line (DL) is parallel to the word line (WL) runs. Integrated semiconductor memory according to one of claims 1 to 10, characterized in that the source contact of the selection transistor (T) on the digit line (DL) and the memory element (S) between the drain contact of the selection transistor (T) and the bit line (BL) where the digit line (DL) is parallel to the bit line (BL) runs.