WO2005117024A1

WO2005117024A1 - Integrated semiconductor memory comprising an organic selector transistor

Info

Publication number: WO2005117024A1
Application number: PCT/DE2005/000926
Authority: WO
Inventors: Hagen Klauk; Marcus Halik; Ute Zschieschang; Günter Schmid; Christine Dehm
Original assignee: Infineon Technologies Ag
Priority date: 2004-05-26
Filing date: 2005-05-20
Publication date: 2005-12-08
Also published as: DE102004025676B4; DE102004025676A1

Abstract

The invention relates to an integrated semiconductor memory comprising a cell field that is composed of a plurality of memory cells which are arranged in lines and rows. An organic selector transistor (T11, T12, T13) which represents a field effect transistor with an organic semiconductor layer (os) is integrated in each memory cell along with an organic storage element (S11, S12, S13), i.e. an organic layer (as) that is disposed between two electrodes and alternatively has a capacitive or resistive electrical storage behavior so as to form a planar memory cell on any substrate, said substrate preferably not being made of silicon. The selector transistors (T11, T12, T13) and the storage elements (S11, S12, S13) of the inventive semiconductor memory are arranged such that the gate electrode of the selector transistors (T11, T12, T13) is embodied as a word line (WL1, WL2, WL3) while the drain contact or source contact of the selector transistors (T11, T12, T13) or the electrodes of the storage elements (S11, S12, S13) are configured as a bit line (BL1, BL2, BL3), a digit line, or a magnetoresistor. In principle, the ratio between the channel width (W) and the channel length (L) of the selector transistors can be randomly adjusted.

Description

description

Integrated semiconductor memory with organic selection transistor

The invention relates to an integrated semiconductor memory having a cell array comprising a plurality of memory cells arranged in rows and columns on a substrate, each of which has a memory element with two electrodes and an associated selection transistor.

The market for semiconductor memories is currently served by a relatively manageable number of products:

1. Main memory with extremely short access times, as are used to an enormous extent in computers today, are produced almost exclusively on the basis of volatile memory architectures ("volatile memory"), in particular in DRAM technology ("dynamic random access memory") , DRAM technology is based on the storage of electronic charges in a capacitive storage element, i.e. in a capacitor. Each memory cell represents a memory unit ("bit") and is formed by a capacitor and a selection transistor (a field effect transistor, FET). The task of the selection transistor is the electrical insulation of the individual memory cells from one another and from the periphery of the cell array; By switching the respective selection transistor, any cell can be specifically and individually accessed ("random access"). The DRAM architecture is characterized by extremely small space requirements (less than one square micron per memory cell) and extremely low manufacturing costs (less than 10 ^{~ 8} euros per memory cell). The decisive disadvantage of the DRAM concept is the volatility of the stored information, since the charge stored in the capacitor is so small (less than 500,000 electrons) that it Switching off the supply voltage after a short time (within a few milliseconds) is lost due to leakage currents within the cell field.

2. Nonvolatile memory ("nonvolatile memory"), which does not lose the stored information even after the supply voltage has been switched off for long periods (several years), is suitable for a wide range of applications (digital cameras, mobile phones, mobile navigation instruments, computer games, etc .) of interest and could also revolutionize the way computers are used, since it would not be necessary to start up the computer after switching it on ("instant-on computer"). Existing non-volatile memory technologies include what are known as flash memories, in which the information is stored in the form of electronic charges in the gate dielectric of a silicon field-effect transistor and is detected as a change in the threshold voltage of the transistor. Since the electronic charge is "trapped" in the gate dielectric of the transistor, it is not lost even when the supply voltage is switched off. A major disadvantage of flash technology are the relatively high write and erase voltages, which result from the need to safely and reproducibly inject the electronic charge to be stored into the gate dielectric or to withdraw it from there. Other disadvantages are the significantly longer access times compared to the DRAM and the limited reliability due to the high load on the gate dielectric when writing and erasing.

3. Due to the above-mentioned disadvantages of flash memories, new technologies for non-volatile semiconductor memories based on various physical concepts have been developed for several years. These include the ferroelectric and magnetoresistive memories, in which the stored information as a change in the electronic electrical polarization (due to the shift of the central atom in a perovskite crystal) or as a change in electrical resistance in an arrangement of ferromagnetic layers. For the integration of ferroelectric memory elements, the use of a selection transistor (similar to the DRAM memory cell) is absolutely necessary in order to ensure the safe reading of the stored information. Magnetoresistive memories can in principle be integrated without a selection transistor, since isolation of the individual memory elements is not absolutely necessary. The implementation of cells without a selection transistor has the essential advantage of a significantly smaller space requirement, which leads to a significantly higher integration density and a lower manufacturing effort per cell. However, the use of a selection transistor makes reading out the stored information considerably easier and safer, and it is foreseeable that the first magnetoresistive memory products will be based on a structure with a selection transistor.

The above-mentioned memory concepts are produced or developed exclusively on silicon platforms, that is to say that the memory elements are produced exclusively on silicon substrates (“silicon wafers”) and exclusively using transistors based on silicon as semiconductors. As an alternative to this, both memory concepts and transistor concepts are currently being developed which do not require the use of silicon wafers and which in principle enable the production of mass memories on inexpensive glass substrates and even on flexible polymer films. Such novel mass storage devices are of interest for a large number of applications, in principle both for all applications for which the ferroelectric and magnetoresistive memories are being developed, and for applications in which the use of silicon Zium substrates adversely affect the costs or the possible uses.

The attached FIGS. 1 a - lf show six possible circuit diagrams of an optionally volatile or non-volatile memory cell with an optionally capacitive, resistive or memory element S based on another physical concept and a selection transistor T.

The six circuit diagrams shown in FIGS. La-lf differ in the arrangement and connection of the memory element S and the selection transistor T with a word line WL, a bit line BL, a digit line DL and a field plate FP. It should be noted here that the basic interconnections of a memory element with a selection transistor shown in FIGS. 1 a - 1 are known per se in the prior art:

FIG. 1 a shows that the drain connection of the selection transistor T is on the bit line BL and the memory element S lies between the source connection of the selection transistor T and a field plate FP.

According to FIG. 1b, the drain connection of the selection transistor T is on the bit line BL and the memory element is between the source connection of the selection transistor T and a digit line DL, which is led in parallel with the word line WL.

According to FIG. 1 c, the drain connection of the selection transistor T is on the bit line BL and the memory element S is between the source connection of the selection transistor T and a digit line DL, which runs parallel to the bit line BL.

According to FIG. 1d, the source connection of the selection transistor T lies on a field plate FP and the memory element S lies between the drain connection of the selection transistor T and the bit line BL. FIG. 1 shows that the source terminal of the selection transistor T is on a digit line DL and the memory element S is between the drain terminal of the selection transistor T and the bit line BL, the digit line DL running parallel to the word line WL.

According to FIG. 1f, the source connection of the selection transistor T is connected to a digit line and the memory element S lies between the drain connection of the selection transistor T and

Bit line BL, the digit line DL running parallel to the bit line BL.

The memory cell S is always selected via the word line WL, which is connected in each case to the gate electrode of the selection transistor T. By applying a suitable potential to the word line WL (for example a negative potential if the selection transistor T is a p-type transistor with a negative threshold voltage), the selection transistor T is opened (electrically conductive) and the information stored in the memory element S can be transmitted through Applying suitable potentials to bit line BL and digit line DL or field plate FP can be read out via the bit line in a read cycle or changed in a write or erase cycle.

An embodiment of the memory cell with a digit line DL has the advantage over an embodiment with a field plate FP that the potential on this line can be specifically changed for the cell that is currently being accessed. Designing an integrated semiconductor memory with FP field plate can lead to a smaller space requirement for the cell field.

An important criterion in the implementation of the memory cells is the bit line capacity, which should be as small as possible in the interest of fast access times. Depending on- that the capacitance associated with the selection transistor T is greater or smaller than the capacitance associated with the memory element S is either shown in FIGS. 1 a - lc (in which the selection transistor T is located on the bit line BL) or the configurations in accordance with FIGS ld-lf (in which the memory element S lies between the bit line BL and the drain connection of the selection transistor T) has the lower bit line capacitance.

FIG. 2a shows a highly simplified circuit diagram of a cell array of an integrated semiconductor memory, which is designed according to FIG. 1b. This means that in the case of the memory cells, the drain connections of the selection transistors TOI - TO (a line 0) on the bit lines BL0 - BLm and the memory elements SOI - SOm (the line 0) each between the source connection of the selection transistor (T01 - TOm) and of the digit line DL0. The digit line DL0 runs parallel to the word line WL0 (for simplification only the selection transistors and the memory elements of a 0th line are provided with reference numerals in FIG. 2a). FIG. 2b shows a highly simplified circuit diagram of a cell field which is designed according to FIG. 1f. In this embodiment, the source connections of the selection transistors T01 - TOm are on digital lines DL0 - DLm and the memory elements S01 - SOm are each between the drain connection of the selection transistor and the associated bit line BL0 - BLm. The digit lines DL0 - DLm run parallel to the bit lines BL0 - BLm. Here too, only the selection transistors and the memory elements of the 0th line are provided with reference numerals for simplification. Of course, FIGS. 2a-2b only show a section of a cell field consisting of m columns (bit lines) and n rows (word lines). The row direction is labeled x and the column direction is labeled y.

3 shows a greatly simplified circuit diagram of a cell field consisting of m columns and n rows, which common bit lines ("shared bit lines") is executed. In this embodiment, the memory cells of the first, third, fifth, etc. column are each offset by one row compared to the memory cells of the zero, second, fourth column (y direction). The circuit arrangement of the memory elements and the selection transistors corresponds to the arrangement according to FIG. 2b, the digit lines DLO, DL1 being replaced by bit lines BL1, BL3 etc.

The circuit diagrams of volatile or non-volatile memory cells described above with reference to FIG. 1, which are known per se from the prior art, with either capacitive, resistive or memory elements based on another physical concept and in each case a selection transistor and those based on FIG. 2a, 2b and 3 described circuit diagrams of differently designed cell fields, which are also known in the prior art, serve as the basis for circuit arrangements of an integrated semiconductor memory according to the invention.

It is therefore an object of the invention to provide a concept for an integrated semiconductor memory which can be implemented without a silicon substrate and whose memory cells optionally have capacitive, resistive or memory elements based on another physical concept, in particular non-volatile memory elements based on an organic material, and one contain a selection transistor realized on the basis of an organic semiconductor layer.

According to an essential aspect, the above object is achieved by an integrated semiconductor memory having a cell array composed of a plurality of memory cells arranged in rows and columns on a substrate, each of which has a memory element with two electrodes and an associated selection transistor, the control electrodes of the selection transistors of the individual lines by in the line direction current word lines and a controlled electrode of the selection transistors of the individual columns are either connected to a bit line running in the column direction, or to a digit line or to a field plate, and one electrode of each storage element is connected to the other controlled electrode of the associated selection transistor and the other electrode of each storage element is connected to either a bit line, a digit line or a field plate. According to the invention, the integrated semiconductor memory is distinguished in that each memory cell has an organic one

Has memory element with an organic active layer arranged between the two electrodes and a selection transistor consisting of a field effect transistor with an organic semiconductor layer, and the selection transistors and the memory elements are integrated on the substrate as planar elements and are arranged laterally next to one another in one plane.

In the case of an integrated semiconductor memory according to the invention, the substrate does not need to be a silicon substrate but can consist of glass, a polymer film, a metal film covered with an insulating layer or also of paper and other substrates which do not contain silicon.

In a preferred exemplary embodiment, the selection transistors are integrated in an inverse-coplanar arrangement, in which the organic semiconductor layer is arranged above the gate electrode and the source and drain electrodes of the selection transistors are in direct contact with the gate dielectric.

In a variant of this exemplary embodiment, the gate electrode of the selection transistor and the lower electrode of the memory element can have the same material. In an alternative variant of the preferred exemplary embodiment, the gate electrode of the selection transistor and the lower one Electrode of the memory element each consist of different materials.

In a further preferred embodiment, the preferred exemplary embodiment can be designed such that the source and drain electrodes of the selection transistor and the upper electrode of the memory element have the same material.

In an alternative advantageous embodiment, the source and drain electrodes of the selection transistor on the one hand and the upper electrode of the memory element on the other hand consist of different materials.

Advantageously, with the preferred exemplary embodiments described below in detail and their variants of an integrated semiconductor memory according to the invention, all circuit variants of integrated semiconductor memories described above with reference to FIGS. 1a-2f, 2a, 2b and 3 can be realized.

The following description, based on the drawing, thus describes preferred exemplary embodiments and their variants of an integrated semiconductor memory according to the invention. The drawing figures show in detail:

La to lf the six circuit diagrams already described at the beginning of an optionally volatile or non-volatile memory cell with an optionally capacitive or resistive memory element and a selection transistor;

Figs. 2a and 2b highly simplified circuit diagrams of two cell ^"Feider consisting of mxn memory cells each designed according to Figures lb and 2f (already described above). 3 shows a simplified circuit diagram of a cell field, implemented with common bit lines (already described at the beginning);

4a-4f are schematic cross sections through differently designed memory cells according to the invention according to FIGS.

5a-5e are schematic cross sections through differently designed memory cells according to the invention according to FIGS. Le and lf;

6 shows a schematic layout view of a section of a cell array with memory cells according to the invention according to FIGS. 1b, 2a and 4b with a W / L ratio of the selection transistor from FIG. 1;

7 shows a schematic layout layer of a section of a cell array with memory cells according to the invention according to FIGS. 1b, 2a and 4b with a W / L ratio of the selection transistor of approximately 10.

8 shows a schematic layout view of a section of a cell array with memory cells according to the invention according to FIGS. 1f, 2b and 5c with a W / L ratio of the selection transistor from FIG. 1.

9 shows a schematic layout view of a section of a cell array with memory cells according to the invention according to FIGS. 1f, 2b and 5c with a W / L ratio of approximately 10 and 10 shows a schematic layout view of a section of a cell array with memory cells according to the invention according to FIGS. 1c, 3 and 4f with a W / L ratio of the selection transistor from FIG. 1.

4a-4f, the memory element and the selection transistor of each memory cell are each with S and T, the bit line with BL, the word line with WL, the field plate with FP, the gate dielectric with GD, the organic semiconductor layer of the field effect transistor T with os and the organic active layer of the memory element S with as. The selection transistors T of all the variants shown in FIGS. 4a-4f are integrated in an inverse-coplanar arrangement, in which the organic semiconductor layer os of the selection transistor T is arranged above its gate electrode and its source and drain electrodes are each in direct contact with the gate dielectric GD stand.

4a shows a schematic cross section of the planar memory cell consisting of the memory element S with the organic active layer as and the selection transistor T with the organic active layer as according to the circuit shown in FIG. 1 a with a field plate FP, which here is the lowest metal layer ( Metal-0). The field dielectric FD forms an insulation between the different metal layers, i. H. 4a shows that the source / drain contacts of the selection transistor T can consist of the same material as the upper electrode of the storage element S. This also applies to the variants according to FIGS 4b and 4c.

4b shows a schematic cross section of an embodiment according to the invention of the circuit shown in FIG. naren memory cell using the same material for the implementation of the gate electrode of the selection transistor T and the lower electrode of the memory element S and therefore necessarily with a digit line DL run parallel to the word line WL.

4c shows a schematic cross section of an embodiment according to the invention of the circuits of a planar memory cell shown in FIGS. 1b and 1c using two different materials for realizing the gate electrode of the selection transistor T and the lower electrode of the memory element S and therefore with one alternatively parallel to the word line WL or parallel to the bit line BL digit line DL.

4d shows a schematic cross section of an embodiment according to the invention of the circuits of a planar memory cell shown in FIGS. 1b and 1c using two different materials for the implementation of the gate electrode of the selection transistor T and the upper electrode of the memory element S and therefore with one alternatively parallel to the word line WL or parallel to the bit line BL digit line DL. In contrast, the lower electrode of the memory element S can have the same material as the drain / source contacts of the selection transistor T.

4e shows a schematic cross section of an embodiment according to the invention of the circuits of a planar memory cell shown in FIGS. 1b and 1c using four different materials, each for the implementation of the gate electrode and the source and drain contacts of the selection transistor T and of the upper and lower ones Electrode of the memory element S and therefore with a digit line DL, which is optionally implemented parallel to the word line WL or parallel to the bit line BL. 4f shows a schematic cross section of an embodiment according to the invention of the circuits of a planar memory cell shown in FIGS. 1b and 1c using the same material for realizing the gate electrode of the selection transistor T and the lower electrode of the memory element S, but with the possibility of to run the digit line DL either parallel to the word line WL or parallel to the bit line or with the option of a second bit line. Therefore, the embodiment according to FIG. 4f is particularly suitable for the realization of a cell field with common bit lines according to FIG. 3.

5a-5e each show a schematic cross section of memory cells designed according to the invention in accordance with the circuits in FIGS. Le and lf. The selection transistor T is also integrated in an inverse-coplanar arrangement in the planar memory cells according to the invention shown in FIGS. 5a and 5e. The reference numerals in Figures 5a-5e are the same as those used in Figures 4a-4f. 5a-5e, the digital line DL is optionally routed parallel to the word line WL or parallel to the bit line BL. According to FIG. 5a, the source / drain electrode of the selection transistor T can consist of the same material as the upper electrode of the memory element S. According to FIG. 5b, the upper electrode of the selection transistor T can consist of the same material as the lower electrode of the memory element S. Die 5b-5e, bit line BL is in an upper metallization layer and the word line WL is always in a lowermost metal layer (metal 0). When executed according to

5a, the bit line is also in the lowest metal layer (metal 0).

All of the designs of planar semiconductor memory cells according to the invention shown in FIGS. 4a-4f and 5a-5e are suitable for realizing a cell field composed of a large number of rows and columns on a substrate. arranged planar memory cells, each having a memory element S with an associated selection transistor T integrated in the same plane next to it, the control electrodes of the selection transistors of the individual rows by word lines WL running in the row direction and a controlled electrode of the selection transistors T of the individual columns either with an in Column direction running bit line BL or with a digit line DL or with a field plate FP and one electrode of each memory element with the other controlled electrode of the associated selection transistor T and the other electrode of each memory element S either with a bit line BL or with a digit line DL or is connected to a field plate FP. In the integrated semiconductor memory according to the invention, each memory cell has an organic memory element S with an organic active layer as arranged between the two electrodes and a selection transistor T consisting of a field effect transistor with an organic semiconductor layer os, the selection transistors T and the memory elements S on the substrate, the does not have to be silicon, is integrated as planar elements and is arranged laterally next to one another in one plane.

The realization of the embodiments of memory cells according to the invention shown in FIGS. 4a-4f and 5a-5e requires the deposition and structuring of the following functional layers on the substrate (not shown). In the following list, optional layers are written in italics. 1. Metal-0 {DL or FP or DL; lower electrode of the memory element) 2. Metal-1 (WL and gate electrode of the selection transistor T; possibly DL or lower electrode of the memory element); 3. field dielectric FD (insulation of the various metal layers); 4. Gate dielectric GD (insulation between the gate electrode and the semiconductor layer of the selection transistor T); 5. Active layer as of the storage element S;

6. Metal-2 (bit line BL or digit line DL, source and drain contacts of the selection transistor T; upper or, if applicable, lower electrode of the memory element S); 7. Organic semiconductor layer os of the selection transistor T; 8. Metal-3 [BL or DL, upper electrode of the storage element).

Examples of substrates are glass, polymer film, metal foil (covered with an insulating layer), paper and others

Suitable materials. In particular, the use of silicon as a substrate is possible, but not necessary. The layers metal-0, metal-1, metal-2 and metal-3 must be metallically conductive, i.e. by depositing inorganic metals (for example aluminum, copper, titanium, gold), conductive oxides (for example indium tin oxide) , or conductive polymers (for example polyaniline). The gate dielectric and the field dielectric must have good insulator properties; inorganic insulators, such as silicon oxide and aluminum oxide, but in particular also insulating polymers, such as polyvinylphenol, are suitable for this. A number of materials can be used as the organic semiconductor layer os for the selection transistor T, in particular pentazene, various oligothiophenes and polythiophene. A number of approaches for capacitive as well as resistive memory effects are currently being discussed for the implementation of the active layer as of the memory element S.

All preferred exemplary embodiments of memory cells according to the invention shown in FIGS. 4 and 5 use a planar structure, that is to say the memory element and the selection transistor are integrated lying side by side in one plane on the substrate. In comparison with a vertical structure, in which the memory element and the selection transistor lie - at least partially - one above the other, the planar Structure the advantage that it is much easier to implement from a technological perspective.

All of the memory cells shown in FIGS. 4 and 5 use a selection transistor which is manufactured in an inverse-coplanar ("inverted co-planar") design. In the inverse-coplanar construction, the organic semiconductor layer os is arranged on the top (above the gate electrode) (inversely to the ordinary silicon field effect transistor in which the gate electrode is arranged on the top), and the source and drain contacts are in direct contact with the gate dielectric GD (in contrast to the staggered version, in which the semiconductor layer is located between the gate dielectric and the source / drain contacts. The inverse-coplanar version is the most frequently used design for organic transistors, but in principle all can be integrated into Fig. 1 implement circuits in memory cells according to the invention with organic selection transistors in any other design.

An important criterion in the design of the memory cell is the question of whether the same material is used for the implementation of the gate electrode of the selection transistor T and the lower electrode of the memory element S, or whether two different materials are used. In principle, the realization of the memory cell is simpler if the same material (metal-1 in FIGS. 4b and 5c) is used for the gate electrode of the selection transistor and the lower electrode of the memory element, since in this case only one is used to implement both structures Process step becomes necessary. In certain cases, however, it may be necessary to design the gate electrode of the selection transistor T and the lower electrode of the memory element S with two different materials. For example, resistive memories which require the use of very specific materials for the lower electrode of the memory element, such as, for example, copper or indium tin oxide, are discussed in the literature. ever after execution of the selection transistor (in particular depending on the choice of material for the gate dielectric), such materials may be unsuitable for the implementation of the gate electrode of the selection transistor and therefore the use of two different materials (metal-0, optimized for the implementation of the lower electrode of the memory element; metal -1, optimized for the implementation of the gate electrode of the selection transistor; see FIGS. 4a, 4c, 4e, 5a, 5d and 5e). Similar considerations relate to the choice of materials for the implementation of the source and drain contacts of the selection transistor and the upper electrode of the memory element. In principle, the realization of the memory cell is easier if the same material (metal-2 in Fig. 4a, 4b, 4c, 5a, 5d, 5d) is used, but in certain cases it may be necessary to use two different materials. In this case too, the designs shown in FIGS. 4 and 5 have to be slightly adapted.

6 shows in the form of a schematic layout representation a section of a cell array according to the invention made of planar memory cells with circuit arrangements according to FIGS. 1b and 2a and a cross-sectional structure according to FIG. 4b. The cell field shown consists of nine cells organized in three columns (bit lines BL1, BL2, BL3) and three rows (word lines WL1, WL2, WL3) and three digit lines (DL1, DL2, DL3). The selection transistors of a first row of the cell array are each denoted by TU, T12, T13 and the associated memory elements of the first row of the cell array laterally integrated in the same plane are denoted by S11, S12 and S13.

An important criterion when designing memory cells is the ratio W / L of the channel width W to the channel length L of the selection transistor, the so-called W / L ratio. This W / L ratio of the selection transistor decisively decides on its electrical resistance, that is to say on the amperage which, for a certain combination of gate Source voltage and drain-source voltage flow through the transistor (the current is proportional to the W / L ratio). In the cell field shown in FIG. 6, the W / L ratio of the selection transistors is approximately equal to 1. That is, W = L. In principle, the design shown allows the implementation of any W / L ratio. 7 shows a section of a cell array according to the invention from planar memory cells in the circuit arrangements according to FIGS. 1b and 2a and with the cross-sectional structure of FIG. 4b, in which the W / L ratio of the selection transistor is approximately 10. As already shown in FIG. 6, the cell field shown consists of nine memory cells which are organized in three rows and three columns. The channel width W results approximately from the length of the inner outline of the drain contact D, that is to say approximately 2a + b, and the channel length results approximately from the distance between the drain contact D and the source contact S.

8 and 9 show schematic layout representations of two cell arrays from planar memory cells according to the invention in accordance with the circuit arrangements in FIGS. 1f and 2b and the cross-sectional structure in accordance with FIG. 5c, the selection transistors in FIG. 8 having a W / L ratio of approximately 1 and in 9 have a W / L ratio of about 10. 8 and 9 also represent a cell array of nine memory cells, organized in three columns and three rows. The selection transistors of a first row (WL1) are each with TU, T12, T13 and the memory elements of this row with S11, S12 and Denoted S13.

Finally, the layout view of FIG. 10 schematically shows a cell array with planar memory cells according to the invention, which implement the circuits according to FIGS. 1c and 3 and have the cross-sectional structure according to FIG. 4f. The W / L ratio of the selection transistors is 1. In principle, each circuit according to FIGS. 1 a - 1 f and each embodiment of the memory cells according to the invention shown in the cross-sectional representations of FIGS. 4 a - 4 f and 5 a - 5 e can be implemented with any W / L ratio of the selection transistors, so that the in 6-10 are only examples.

A process for realizing the cell field shown in the layout of FIG. 6 is explained below as an example. According to the preferred exemplary embodiment of an integrated semiconductor memory according to the invention shown in FIG. 6, for each of the six functional layers to be structured, that is to say metal 1, active layer as of the memory element S, field dielectric FD, gate dielectric GD, metal 2 and organic semiconductor layer os of the selection transistor T made a chrome mask, which allows the structuring of the deposited layers by means of photolithographic processes.

A layer of aluminum, approximately 30 nm thick, is applied to a substrate, for example made of glass, which is structured by means of photolithography and wet-chemical etching in aqueous potassium hydroxide solution, around the first metal layer (metal-1; gate electrode of the selection transistor T; lower electrode of the memory element S; word line WL) to be defined.

In the second step, the active layer as of the storage element (S), for example a polymer which is characterized by a specifically variable electrical resistance, is deposited and structured. In order to generate the field dielectric FD, an approximately 300 nm thick layer of polyvinylphenol is spun on from a suitable organic solvent (for example propylene glycol monomethyl ether acetate, PGMEA), thermally crosslinked (at approximately 200 ° C.) and by means of photolithography and Textured etching in an oxygen plasma. The gate dielectric GD is defined below, for example by spinning on and photolithographically structuring an approximately 100 nm thick layer of polyvinylphenol or by applying an approximately 3 nm thick electrically insulating molecular self-assembling monolayer (“seif asembling mono layer”; SAM).

In the next step, an approximately 30 nm thick gold layer is evaporated and by means of photolithography and wet chemical

Etching defines the second metal layer (metal-2; source and drain contacts of the selection transistor T; bit line BL).

Finally, an approximately 30 nm thick layer of pentazen is evaporated as the organic semiconductor layer os of the selection transistor and structured by means of photolithography (with the aid of a water-soluble photoresist) and plasma etching.

In summary, the invention provides a semiconductor memory in which an organic selection transistor, that is to say a field effect transistor with an organic semiconductor layer together with an organic memory element, that is to say an organic active layer arranged between two electrodes, with either capacitive, resistive or based on another physical concept electrical storage behavior can be integrated together to form a planar storage cell on any substrate, which preferably does not consist of silicon. It is particularly important that the selection transistor and memory element are arranged such that the gate electrode of the transistor is designed as a word line and the drain or source contact of the transistor or the electrodes of the memory element are designed either as a bit line, digit line or field plate. LIST OF REFERENCE NUMBERS

he active layer of the memory element os organic layer of the selection transistor BL, BLO - BLm bit lines

DL, DLO - DLm digit lines

WL, WLO - WLm WortLeitungen

S, Sll, S12, S13, SOI, S02, S03 - SOm memory elements T, TU, T12, T13, TOI - TOm selection transistors

GD gate dielectric

FP field plate

S, D Source, Drain a, b Side lengths of the drain contact

W channel width

L channel length x, y row, column direction

Claims

claims

1. Integrated semiconductor memory with a cell array made up of a multiplicity of memory cells, each of which is arranged in rows (0-n) and columns (0-m) on a substrate

Have memory element (Sll, S12, S13) with two electrodes and an associated selection transistor (TU, T12, T13), the control electrodes of the selection transistors of the individual lines being controlled by word lines (WLO, WL1, WL2) running in the line direction (x) and a controlled one Electrode of the selection transistors of the individual columns is either connected to a bit line (BL1, BL2, BL3) running in the column direction (y) or to a digit line (DL1, DL2, DL3) or to a field plate (FP) and an electrode of each memory element (Sll, S12, S13) with the other controlled electrode of the associated selection transistor (TU, T12, T13) and the other electrode of each memory element either with a bit line (BL1, BL2, BL3), a digit line (DL1, DL2, DL3) or one Field plate (FP) is connected, characterized in that each memory cell (Sll, S12, S13) has an organic memory element (S) with an organi arranged between the two electrodes The active layer (as) and a selection transistor (TU, T12, T13) consisting of a field effect transistor (T) with an organic semiconductor layer (os) and the selection transistors (TU, T12, T13) and the memory elements (Sll, S12 , S13) are integrated on the substrate as planar elements and are arranged laterally next to one another in one plane.

2. Integrated semiconductor memory according to claim 1, so that the substrate is not a silicon substrate.

3. Integrated semiconductor memory according to claim 1 or 2, characterized in that the substrate consists of glass.

4. Integrated semiconductor memory according to claim 1 or 2, d a d u r c h g e k e n n z e i c h n e t that the substrate has a polymer film.

5. Integrated semiconductor memory according to claim 1 or 2, so that the substrate is a metal film coated with an insulating layer.

6. Integrated semiconductor memory according to claim 1 or 2, d a d u r c h g e k e n n z e i c h n e t that the substrate consists of paper.

7. Integrated semiconductor memory according to one of claims 1 to 6, characterized in that the selection transistors (TU, T12, T13) are integrated in an inverse-coplanar arrangement, in which the organic semiconductor layer (os) of each selection transistor is arranged above its gate electrode and its source and drain contact is in direct contact with the gate dielectric.

8. Integrated semiconductor memory according to one of claims 1 to 7, d a d u r c h g e k e n n z e i c h n e t that the gate electrode of the selection transistors and the lower

Electrode of the memory elements have the same material.

9. Integrated semiconductor memory according to one of claims 1 to 7, characterized in that the gate electrode of the selection transistors and the lower electrode of the memory elements each have different materials.

10. Integrated semiconductor memory according to one of claims 1 to 9, so that the source and drain contact of the selection transistors and the upper electrode of the memory elements have the same material.

11. Integrated semiconductor memory according to one of claims 1 to 9, d a d u r c h g e k e n n z e i c h n e t that the source and drain contact of the selection transistors and the upper electrode of the memory elements each have different materials.

12. Integrated semiconductor memory according to one of the preceding claims, d a d u r c h g e k e n n z e i c h n e t that the drain contact of the selection transistor (T) on the bit line (BL) and the memory element (S) between the source contact of the selection transistor (T) and a field plate (FP).

13. Integrated semiconductor memory according to one of claims 1 to 11, characterized in that the drain contact of the selection transistor (T) on the bit line (BL) and the memory element (S) between the source contact of the selection transistor (T) and the digit line running parallel to the word line ( DL).

14. Integrated semiconductor memory according to one of claims 1 to 11, characterized in that the drain contact of the selection transistor on the bit line and the memory element between the source contact of the selection transistor and the digit line (DL) running parallel to the bit line (BL).

15. Integrated semiconductor memory according to one of claims 1 to 11, d a d u r c h g e k e n n z e i c h n e t that the source contact of the selection transistor (T) on a field plate (FP) and the memory element (S) between the drain contact of the selection transistor (T) and the bit line (BL).

16. Integrated semiconductor memory according to one of claims 1 to 11, characterized in that the source contact of the selection transistor on the digit line (DL) and the memory element between the drain contact of the selection transistor and the bit line (BL), the digit line (DL) in parallel runs to the word line (WL).

17. Integrated semiconductor memory according to one of claims 1 to 11, characterized in that the source contact of the selection transistor (T) on the digit line (DL) and the memory element (S) lies between the drain contact of the selection transistor (T) and the bit line (BL), the digit line (DL) running parallel to the bit line (BL).