TW200302579A - Manufacture of bipolar transistors including silicon-germanium/silicon heterojunction - Google Patents
Manufacture of bipolar transistors including silicon-germanium/silicon heterojunction Download PDFInfo
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- TW200302579A TW200302579A TW91132765A TW91132765A TW200302579A TW 200302579 A TW200302579 A TW 200302579A TW 91132765 A TW91132765 A TW 91132765A TW 91132765 A TW91132765 A TW 91132765A TW 200302579 A TW200302579 A TW 200302579A
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- silicide layer
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- germanium
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- 229910000577 Silicon-germanium Inorganic materials 0.000 title claims abstract description 82
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 33
- 239000010703 silicon Substances 0.000 title claims abstract description 33
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 31
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 title abstract description 5
- 239000000758 substrate Substances 0.000 claims abstract description 136
- 239000004065 semiconductor Substances 0.000 claims abstract description 53
- 230000001681 protective effect Effects 0.000 claims abstract description 46
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 32
- 239000010410 layer Substances 0.000 claims description 209
- 229910021332 silicide Inorganic materials 0.000 claims description 111
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 109
- 238000000151 deposition Methods 0.000 claims description 64
- 238000004140 cleaning Methods 0.000 claims description 31
- 238000000034 method Methods 0.000 claims description 26
- 239000004575 stone Substances 0.000 claims description 19
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 claims description 14
- 239000000126 substance Substances 0.000 claims description 13
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 claims description 12
- YBMRDBCBODYGJE-UHFFFAOYSA-N germanium oxide Inorganic materials O=[Ge]=O YBMRDBCBODYGJE-UHFFFAOYSA-N 0.000 claims description 12
- 238000010438 heat treatment Methods 0.000 claims description 10
- PVADDRMAFCOOPC-UHFFFAOYSA-N oxogermanium Chemical compound [Ge]=O PVADDRMAFCOOPC-UHFFFAOYSA-N 0.000 claims description 9
- 239000011241 protective layer Substances 0.000 claims description 7
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 claims description 5
- 238000007654 immersion Methods 0.000 claims description 5
- 239000002253 acid Substances 0.000 claims description 4
- 238000013467 fragmentation Methods 0.000 claims description 3
- 238000006062 fragmentation reaction Methods 0.000 claims description 3
- OMBRFUXPXNIUCZ-UHFFFAOYSA-N dioxidonitrogen(1+) Chemical compound O=[N+]=O OMBRFUXPXNIUCZ-UHFFFAOYSA-N 0.000 claims 1
- 239000002019 doping agent Substances 0.000 claims 1
- 230000008021 deposition Effects 0.000 description 55
- 238000006243 chemical reaction Methods 0.000 description 50
- 239000007789 gas Substances 0.000 description 29
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 20
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 17
- 229910052732 germanium Inorganic materials 0.000 description 15
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 15
- 238000005229 chemical vapour deposition Methods 0.000 description 14
- 230000007547 defect Effects 0.000 description 10
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 9
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 9
- 229910052799 carbon Inorganic materials 0.000 description 9
- 239000000356 contaminant Substances 0.000 description 9
- 239000001301 oxygen Substances 0.000 description 9
- 229910052760 oxygen Inorganic materials 0.000 description 9
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 8
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 description 7
- 239000012535 impurity Substances 0.000 description 6
- 238000010521 absorption reaction Methods 0.000 description 5
- 150000001875 compounds Chemical class 0.000 description 5
- 238000011109 contamination Methods 0.000 description 5
- 239000010408 film Substances 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 4
- 229910000078 germane Inorganic materials 0.000 description 4
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000001704 evaporation Methods 0.000 description 3
- -1 germanium oxide compound Chemical class 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- 238000001816 cooling Methods 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000003344 environmental pollutant Substances 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 238000002474 experimental method Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 239000003960 organic solvent Substances 0.000 description 2
- 229910000073 phosphorus hydride Inorganic materials 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 231100000719 pollutant Toxicity 0.000 description 2
- 238000004062 sedimentation Methods 0.000 description 2
- 229910000077 silane Inorganic materials 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 238000005406 washing Methods 0.000 description 2
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- WHXSMMKQMYFTQS-UHFFFAOYSA-N Lithium Chemical compound [Li] WHXSMMKQMYFTQS-UHFFFAOYSA-N 0.000 description 1
- 235000010627 Phaseolus vulgaris Nutrition 0.000 description 1
- 244000046052 Phaseolus vulgaris Species 0.000 description 1
- 229910007264 Si2H6 Inorganic materials 0.000 description 1
- 238000004833 X-ray photoelectron spectroscopy Methods 0.000 description 1
- 229910021536 Zeolite Inorganic materials 0.000 description 1
- DQGHRSPFUXUGOS-UHFFFAOYSA-N [SiH4].[Os] Chemical compound [SiH4].[Os] DQGHRSPFUXUGOS-UHFFFAOYSA-N 0.000 description 1
- NIXOWILDQLNWCW-UHFFFAOYSA-N acrylic acid group Chemical group C(C=C)(=O)O NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 239000000908 ammonium hydroxide Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229960004424 carbon dioxide Drugs 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000007865 diluting Methods 0.000 description 1
- HNPSIPDUKPIQMN-UHFFFAOYSA-N dioxosilane;oxo(oxoalumanyloxy)alumane Chemical compound O=[Si]=O.O=[Al]O[Al]=O HNPSIPDUKPIQMN-UHFFFAOYSA-N 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- QUZPNFFHZPRKJD-UHFFFAOYSA-N germane Chemical compound [GeH4] QUZPNFFHZPRKJD-UHFFFAOYSA-N 0.000 description 1
- 229910052986 germanium hydride Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- CABDFQZZWFMZOD-UHFFFAOYSA-N hydrogen peroxide;hydrochloride Chemical compound Cl.OO CABDFQZZWFMZOD-UHFFFAOYSA-N 0.000 description 1
- 229910052744 lithium Inorganic materials 0.000 description 1
- 239000008267 milk Substances 0.000 description 1
- 210000004080 milk Anatomy 0.000 description 1
- 235000013336 milk Nutrition 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- GSWAOPJLTADLTN-UHFFFAOYSA-N oxidanimine Chemical compound [O-][NH3+] GSWAOPJLTADLTN-UHFFFAOYSA-N 0.000 description 1
- 230000020477 pH reduction Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 229910052702 rhenium Inorganic materials 0.000 description 1
- WUAPFZMCVAUBPE-UHFFFAOYSA-N rhenium atom Chemical compound [Re] WUAPFZMCVAUBPE-UHFFFAOYSA-N 0.000 description 1
- VDNSGQQAZRMTCI-UHFFFAOYSA-N sulfanylidenegermanium Chemical compound [Ge]=S VDNSGQQAZRMTCI-UHFFFAOYSA-N 0.000 description 1
- 238000007669 thermal treatment Methods 0.000 description 1
- 239000010455 vermiculite Substances 0.000 description 1
- 229910052902 vermiculite Inorganic materials 0.000 description 1
- 235000019354 vermiculite Nutrition 0.000 description 1
- 239000010457 zeolite Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02043—Cleaning before device manufacture, i.e. Begin-Of-Line process
- H01L21/02052—Wet cleaning only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02441—Group 14 semiconducting materials
- H01L21/0245—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02658—Pretreatments
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66242—Heterojunction transistors [HBT]
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Bipolar Transistors (AREA)
- Weting (AREA)
Abstract
Description
200302579 ⑴ 玖、發蝻說明 (發明說明應敘明··發明所屬之技術 —* 无引技術、内谷、實施方式及圖式簡單說明） 發明背景 !_·發明領^ ::::關於一種製造包含鍺鶴/石夕化物 ==晶體(HBT)的方法，以及適合用來製造 體之+導體基板。 2·相關技辞說明 包含鍺矽化物/矽化物昱皙桩人 y / u奶”為接合面之雙極電晶體（HBTs) 係以1 〇十億赫茲（GHz)或更高的古 m , θ 、、 又冋的阿頻率運作，因此是用於高 速通信裝置或高速功率電晶體。 圖1顯示傳統異質接合面之雙極電晶體（HBT)的剖面圖。 矽基板102之主要表面，係以作為HBT集極之用的磊晶矽化 物層1〇3覆蓋。此一磊晶矽化物層1〇3之上表面係以作為 HBT基極之用的鍺矽化物層1〇1覆蓋。作為hbt射極之用的 重摻雜石夕化物層1 04沈積於鍺石夕化物層i 〇丨之上。集極電極 105係沈積於矽基板ι〇2之背面。射極電極ι〇6係形成於矽化 物層104上。基極電極107係形成於鍺矽化物層1〇1上。傳統 的HBT具有小的輸入阻抗，因此以高速運作。 通常以化學氣相沈積（CVD)形成鍺矽化物膜。圖2顯示用 於鍺矽化物膜之沈積的傳統CVD裝置。此一 CVD裝置包含 一沈積反應室109，一基板支架110，及一承載搖動反應器 111。將以鍺矽化物膜覆蓋的基板108載入沈積反應室ι〇9 中’並固定於基板支架110。基板支架110包含一加熱器（未 顯示）以升高石夕基板1 08的溫度。在鍺矽化物膜之沈積期間 200302579200302579 蝻 玖, description of the invention (the description of the invention should be stated ... the technology to which the invention belongs— * non-citing technology, inner valley, embodiment and simple illustration of the invention) Background of the invention! _ · Invention collar ^ :::: about a A method for manufacturing a germanium crane / stone compound == crystal (HBT), and a + conductor substrate suitable for manufacturing a body. 2. Relevant technical descriptions: Bipolar transistors (HBTs) containing germanium silicides / silicides Yuxi Pingren y / u milk "as the joint surface are ancient m at 10 billion hertz (GHz) or higher, The θ, 冋, and 冋 frequencies operate, so it is used for high-speed communication devices or high-speed power transistors. Figure 1 shows a cross-section of a traditional heterojunction bipolar transistor (HBT). The main surface of the silicon substrate 102 The epitaxial silicide layer 10 is used as the HBT collector. The upper surface of the epitaxial silicide layer 10 is covered with the germanium silicide layer 101 as the HBT base. As The heavily doped stone oxide layer 1 04 for the hbt emitter is deposited on the germanium oxide layer i 〇 丨. The collector electrode 105 is deposited on the back of the silicon substrate ι〇2. It is formed on the silicide layer 104. The base electrode 107 is formed on the germanium silicide layer 101. Conventional HBT has a small input impedance and therefore operates at a high speed. Generally, germanium silicide is formed by chemical vapor deposition (CVD) Fig. 2 shows a conventional CVD device for the deposition of germanium silicide film. This CVD device includes a sinker. A reaction chamber 109, a substrate holder 110, and a shaking reactor 111. A substrate 108 covered with a germanium silicide film is loaded into the deposition reaction chamber 109 and fixed to the substrate holder 110. The substrate holder 110 includes a heating (Not shown) to raise the temperature of the Shixi substrate 108. During the deposition of the germanium silicide film 200302579
(2) ，沈積反應室109供應包含氫矽化物氣體之沈積氣體，如甲 矽烷與乙矽烷，以及氫鍺化物氣體，如鍺烷。氫矽化物與 氫鍺化物之反應形成鍺石夕化物膜。 鍺矽化物層1 0 1的沈積係藉由下列過程來完成。以磊晶石夕 化物層103覆蓋的矽基板102經由承載搖動反應室U1傳送 到沈積反應室109，並固定於石夕化物支架11 〇。接著，石夕基 板102以攝氏800度〜攝氏900度的溫度，熱處理1〇〜6〇分鐘。 熱處理將氧與碳從蠢晶石夕化物層1 〇 3的表面上移除。接著石夕 基板102的溫度調整到理想的沈積溫度，一般是在攝氏5〇〇 度〜攝氏800度的範圍。接著供應沈積氣體到沈積反應室ι〇9 中，同時矽基板1 02保持於理想的沈積溫度。然後藉由停止 沈積氣體的供應，或冷卻石夕基板10 8，停止鍺石夕化物層1 〇 1 的沈積。鍺矽化物層101的厚度可以藉由沈積時間與/或沈 積反應室的壓力來調整。鍺矽化物膜的濃度則可以藉由沈 積氣體的組成來調節。 在鍺矽化物層101沈積之後，藉由與鍺矽化物層10 2相同 的CVD方法，在鍺矽化物層101上沈積矽化物層丨〇4。鍺石夕 化物層101與矽化物層104的沈積係以不同的cvd反應室來 實施，以避免污染。鍺石夕化物層1 〇 1與石夕化物層1 具有不 同的導電類型，而且通常要求矽化物層1〇4是重摻雜的。如 果鍺矽化物層101與矽化物層104是在相同的反應室沈積， 其將使重摻雜的雜質殘留在反應室中。殘留的雜質可能污 染鍺矽化物層101。使用不同反應室供鍺矽化物層ι〇1與石夕 化物層104之沈積，有效地避免雜質的污染。 200302579(2) The deposition reaction chamber 109 supplies a deposition gas containing a hydrosilicide gas, such as silane and disilane, and a germanogas gas, such as germane. The reaction of hydrosilicide and germanohydrogenide forms a germanium oxide film. The germanium silicide layer 101 is deposited by the following process. The silicon substrate 102 covered with the epitaxial stone material layer 103 is transferred to the deposition reaction room 109 via the load-shaking reaction chamber U1, and is fixed to the stone material holder 11. Next, the Shi Xi substrate 102 is heat-treated at a temperature of 800 ° C to 900 ° C for 10 to 60 minutes. The heat treatment removes oxygen and carbon from the surface of the spinelite layer 103. Next, the temperature of the Shixi substrate 102 is adjusted to an ideal deposition temperature, which is generally in a range of 500 ° C to 800 ° C. Then, a deposition gas is supplied into the deposition reaction chamber 109, while the silicon substrate 102 is maintained at a desired deposition temperature. Then, by stopping the supply of the deposition gas, or cooling the Shixi substrate 108, the deposition of the germanium oxide compound layer 101 is stopped. The thickness of the germanium silicide layer 101 can be adjusted by the deposition time and / or the pressure of the deposition reaction chamber. The concentration of germanium silicide film can be adjusted by the composition of the deposition gas. After the germanium silicide layer 101 is deposited, a silicide layer is deposited on the germanium silicide layer 101 by the same CVD method as the germanium silicide layer 102. The germanium oxide layer 101 and the silicide layer 104 are deposited in different cvd reaction chambers to avoid contamination. The germanium oxide layer 101 and the stone oxide layer 1 have different conductivity types, and it is generally required that the silicide layer 104 is heavily doped. If the germanium silicide layer 101 and the silicide layer 104 are deposited in the same reaction chamber, it will leave heavily doped impurities in the reaction chamber. The remaining impurities may contaminate the germanium silicide layer 101. Different reaction chambers are used for the deposition of the germanium silicide layer ι01 and the stone oxide layer 104, effectively avoiding contamination by impurities. 200302579
矽化物層104的沈積係藉由下列程序來達成。覆蓋鍺矽化 物層1 01的矽基板1 02，被傳送到沈積反應室中。接著矽基 板102以攝氏800度〜攝氏900度的溫度，熱處理1〇〜6〇分鐘。 熱處理將氧與碳從錯石夕化物層1 〇 1的表面上移除。接著石夕基 板1 02的溫度調整到理想的沈積溫度，一般是在攝氏5⑼度〜 攝氏δοο度的範圍。接著供應氫矽化物到沈積反應室中，同 時矽基板102保持於理想的沈積溫度。然後藉由停止氫矽化 物的供應，或冷卻矽基板1 08，停止矽化物層i 04的沈積。 石夕化物層1 04的厚度可以藉由沈積時間與/或沈積反應室的 壓力來調整。 製程良率與鍺矽化物異質接合面雙極電晶體（HBTs)性能 的改良，要求鍺石夕化物層與石夕化物層具有少的缺陷與平坦 的。包含於鍺矽化物層與矽化物層中的缺陷造成泄漏電流 。此外，這些層不良的平坦度使製程的精確度惡化，並降 低製程良率。鍺矽化物層與矽化物層的缺陷與不良的平坦 度是鍺矽化物異質接合面雙極電晶體（HBTs)製造的一個問 題。 目前認為缺陷與不良的平坦度係由下列兩個原因所引起 。一個原因是包含於鍺矽化物層與矽化物層中的應力，其 他的原因則是這些層表面的污染。 應力是由鍺矽化物層與矽化物層之晶格常數間的些微差 異所引起的。鍺矽化物層晶格常數隨著鍺濃度的增加而增 加。因此，在鍺矽化物層與矽化物層的接合面上存在晶格 錯位。晶格錯位引起作用於鍺矽化物層與矽化物層上的應 (4) (4)200302579The silicide layer 104 is deposited by the following procedure. The silicon substrate 102 covering the germanium silicide layer 101 is transferred to the deposition reaction chamber. Next, the silicon substrate 102 is heat-treated at a temperature of 800 ° C to 900 ° C for 10 to 60 minutes. The heat treatment removes oxygen and carbon from the surface of the wortite layer 101. Next, the temperature of the Shixi substrate 102 is adjusted to the ideal deposition temperature, which is generally in the range of 5 ° C to δοο ° C. Hydrosilicide is then supplied to the deposition reaction chamber while the silicon substrate 102 is maintained at the desired deposition temperature. Then, by stopping the supply of hydrosilicide or cooling the silicon substrate 108, the deposition of the silicide layer i04 is stopped. The thickness of the stone oxide layer 104 can be adjusted by the deposition time and / or the pressure of the deposition reaction chamber. The improvement of process yield and the performance of germanium silicide heterojunction bipolar transistors (HBTs) requires that the germanium oxide layer and the stone layer have fewer defects and are flat. Defects contained in the germanium silicide layer and silicide layer cause leakage current. In addition, the poor flatness of these layers deteriorates the accuracy of the process and reduces the process yield. Defects and poor flatness of the germanium silicide layer and silicide layer are a problem in the fabrication of germanium silicide heterojunction bipolar transistors (HBTs). At present, defects and poor flatness are considered to be caused by the following two reasons. One reason is the stress contained in the germanium silicide layer and the silicide layer, and the other cause is the contamination of the surface of these layers. The stress is caused by a slight difference in the lattice constants of the germanium silicide layer and the silicide layer. The lattice constant of the germanium silicide layer increases as the germanium concentration increases. Therefore, there is a lattice misalignment on the joint surface of the germanium silicide layer and the silicide layer. Lattice misalignment causes stress on germanium silicide layer and silicide layer (4) (4) 200302579
力。應力引起鍺石夕化物層中錯位，因而引起堆疊錯 疊錯誤造成鍺矽化物層之較差的平坦度。 、 賓（Bean)等人在應用物理通訊（Appned physics 第54期（刪年）第925頁中，揭示適當的鍺濃度與鍺石夕化物 層厚度有效地降低鍺矽化物層中的缺陷。所揭示的條件有 效地避免應力所造成之缺陷與平坦度惡化的產生。 可是，鍺矽化物層之沈積條件的最佳化，對於抑制由污 染所造成之缺陷與平坦度惡化的產生是無效的。尤其是在 沈積反應室之間傳送期間，沈積於鍺矽化物層上的污染物 是很難移除的。鍺矽化物層表面上的污染物引起矽化物層 中的堆疊錯誤，因此使石夕化物層的平坦度惡化。 目前認為鍺矽化物層表面上的污染物包含氧，碳，氣， 與金屬元素。污染物的減少傳統上是以化學清洗與真空反 應室中高溫的熱處理來達成。RC A清洗是一個化學移除污 染物的典型方法。RCA清洗包含下列步驟： (1)純水清洗數分鐘； (2)在攝氏75度下，浸浴於溶液中數分鐘，此一溶液由 氫氧化銨，過氧化氫，與水所組成； (3) 純水清洗數分鐘； (4) 於室溫下，浸浴於1%重量百分比的氟氫酸中數分鐘； (5) 純水清洗數分鐘； (6) 在室溫下，浸浴於溶液中數分鐘，此一溶液由鹽酸 過氧化氫，與水所組成； (7)純水清洗數分鐘； 200302579force. The stress causes dislocations in the germanium sulfide layer, and thus causes stacking errors and poor flatness of the germanium silicide layer. , Bean and others in Applied Physics Newsletter (Appned Physics No. 54 (Deleted Years), p. 925) revealed that proper germanium concentration and germanium oxide layer thickness effectively reduce defects in germanium silicide layer. The disclosed conditions effectively avoid the occurrence of defects and flatness deterioration caused by stress. However, the optimization of the deposition conditions of the germanium silicide layer is not effective in suppressing the generation of defects and flatness deterioration caused by pollution. Especially during the transfer between the sedimentation reaction chambers, the contaminants deposited on the germanium silicide layer are difficult to remove. The contaminants on the surface of the germanium silicide layer cause stacking errors in the silicide layer, thus making Shi Xi The flatness of the compound layer deteriorates. At present, the contaminants on the surface of the germanium silicide layer are considered to include oxygen, carbon, gas, and metal elements. Reduction of pollutants is traditionally achieved by chemical cleaning and high temperature heat treatment in a vacuum reaction chamber. RC A cleaning is a typical method of chemically removing contaminants. RCA cleaning includes the following steps: (1) pure water for several minutes; (2) immersed in the solution at 75 degrees Celsius Bell, this solution is composed of ammonium hydroxide, hydrogen peroxide, and water; (3) washed with pure water for several minutes; (4) immersed in 1% by weight of hydrofluoric acid for several minutes at room temperature (5) Wash with pure water for several minutes; (6) Soak in the solution for several minutes at room temperature. This solution consists of hydrochloric acid hydrogen peroxide and water; (7) Wash with pure water for several minutes; 200302579
(8) 在室溫下，浸浴於1%重量百分比的氟氫酸中數分鐘； (9) 純水清洗數分鐘； (1〇)在室溫下，浸浴於溶液中數分鐘，此一溶液由硫酸 ，過氧化氫，與水所組成； (11) 純水清洗數分鐘； 及 (12) 自旋乾燥。 可疋’因為化學清洗使用的酸非均向地姓刻鍺矽化物層 ’化學清洗在鍺矽化物層的表面上形成蝕刻凹陷，因而使 鍺矽化物層的平坦度惡化。蝕刻凹陷降低了鍺矽化物異質 接合面雙極電晶體（H]BTs)的製程良率。 錯石夕化物層表面上的清洗可以藉由使用有機溶劑，如丙 網’來達成。可是，污染物並不能被有機溶劑有效地移除。 另一個問題是矽化物層沈積之前熱處理所造成，來自鍺 矽化物層的鍺蒸汽。如上所述，在矽化物層沈積到鍺矽化 物層之刖’基板以攝氏8〇〇度〜攝氏9〇〇度的溫度熱處理，以 移除鍺石夕化物層表面上的污染物。熱處理有效地減少鍺矽 化物層表面上氧與碳的濃度到低於偵測極限。可是，熱處 理使鍺從鍺矽化物層蒸發。鍺蒸汽使鍺矽化物層的平坦度 惡化。鍺矽化物之較差的平坦度，使提供於其上之矽化物 層的平坦度惡化。 提供一種技術’有效地將缺陷從異質接合面雙極電晶體 (HBTs)中排除，並改善包含於HBTst之層的平坦度是有益 的。 200302579(8) immersed in 1% by weight of hydrofluoric acid for several minutes at room temperature; (9) washed with pure water for several minutes; (10) immersed in the solution for several minutes at room temperature. A solution consists of sulfuric acid, hydrogen peroxide, and water; (11) washing with pure water for several minutes; and (12) spin drying. It can be said that 'the chemically-cleaned acid is used to etch the germanium silicide layer'. The chemical cleaning forms an etching depression on the surface of the germanium silicide layer, thereby deteriorating the flatness of the germanium silicide layer. Etching depressions reduce the process yield of germanium silicide heterojunction bipolar transistors (H) BTs. The cleaning on the surface of the zeolite layer can be achieved by using an organic solvent such as acrylic mesh '. However, contaminants cannot be effectively removed by organic solvents. Another problem is the germanium vapor from the germanium silicide layer caused by the heat treatment before the silicide layer is deposited. As described above, the rhenium substrate which is deposited on the silicide layer to the germanium silicide layer is heat-treated at a temperature of 800 ° C to 900 ° C to remove the contaminants on the surface of the germanium oxide layer. Heat treatment effectively reduces the concentration of oxygen and carbon on the surface of the germanium silicide layer to below the detection limit. However, thermal treatment causes germanium to evaporate from the germanium silicide layer. The germanium vapor deteriorates the flatness of the germanium silicide layer. The poor flatness of the germanium silicide deteriorates the flatness of the silicide layer provided thereon. It would be beneficial to provide a technique ' that effectively eliminates defects from heterojunction bipolar transistors (HBTs) and improves the flatness of the layers included in the HBTst. 200302579
發明概要 因此，本發明之目的在從包含鍺石夕化物/石夕化物接合面之 異質接合面雙極電晶體（HBT)中排除缺陷，以及改善包含於 HBT中之層的平坦度。 在本發明之一態樣中，一半導體基板包含一主要由矽所 形成的基板，一沈積以覆蓋石夕基板之鍺石夕化物，以及一實 質上由石夕化物所組成之保護石夕化物層。保護之石夕化物層係 沈積於錯碎化物層上。 保護層宜沈積以完全地覆蓋鍺矽化物層的上表面。 保護層的厚度宜等於或超過50埃，並如此限定，使保護 層在異質接合面雙極電晶體的運作上沒有實質上的效應。 基板可以包含一重摻雜的矽基板，以及少量摻雜的磊晶 石夕化物層。 在本發明之另一態樣中，一種製造用來生產異質接合面 雙極電晶體之半導體基板的方法，包括： 提供一主要由矽化物所形成之基板； 沈積一鍺矽化物層，以覆蓋該基板； 沈積一保護之矽化物層於鍺矽化物層之上表面上。 在本發明之又另一態樣中，一種製造異質接合面雙極電 晶體之方法，包括： 提供一半導體基板包括： 一主要由矽化物所形成之基板； 沈積以覆蓋該基板之鍺矽化物層； 一保護之矽化物層沈積於鍺矽化物層上，此一保護之 -10- 200302579 ⑺ 石夕化物層實質上由石夕化物所組成； 在保護之矽化物層的上表面上，沈積一矽化物層。 此一製造方法宜包括： 使用酸液化學清洗半導體基板。 化學清洗可以包含至少鹽酸溶液中的第一浸浴與由碳駿 與過氧化氫所組成之溶液中的第二浸浴兩者其中之一。 如果製造方法包括下列，是有益的： 將半導體體基板暴露於臭氧環境。 如果製造方法也包含下列，是有益的： 在沈積矽化物層之前，對半導體基板做熱清洗。 熱清洗宜以高於攝氏800度溫度之熱處理來達成。 圖式簡單說明 圖1顯示傳統異質接合面雙極電晶體（HBT)的剖面圖； 圖2顯示用來製造傳統異質接合面雙極電晶體（ΗΒτ)之傳 統CVD裝置； 圖3顯示在本發明之一具體實施例中.，用來製造異質接合 面雙極電晶體（HBTs)之半導體基板； ° 圖4顯示在本發明之一具體貫施例中，用來製造半導體美 板之CVD裝置； & 圖5至9係一剖面圖，顯示在此一具體實施例中，製造半 導體基板之製程； 圖10顯示在此一具體實施例中，用來製造異質接合面雙 極電晶體（HBTs)的另一 CVD裝置； 、 口 圖11至14係剖面圖，顯示在此一具體實施例中，製造異 (8) (8)200302579 質接合面雙極電晶體（HBTs)的製程； 圖1 5顯示所製造之異質接合面雙極電晶體（HB丁）的 圖。 。 較佳具體貫施例詳細說明 圖3顯示在本發明之一具體實施例中，用來製造異質接合 面雙極電晶體（HBTs)之半導體基板。如圖3所示，半導體^ 板包含一 η型矽基板9-1，一 ρ型鍺矽化物層9-2，以及一薄 的保濩矽化物層9-3。鍺矽化物層9-2係沈積於矽基板9_丨之 主（上）表面上，而保護矽化物層9-3則是沈積於鍺矽化物層 9-2上。保護矽化物層9_3完全地覆蓋鍺矽化物層9_2的上表 面。如下面將敘述的，矽化物層9-3係當作保護層之用。應 注意的是矽基板9-1可以包含重摻雜的η型基板，以及沈積 於重摻雜之η型基板上之少量摻雜的磊晶矽化物層（未顯示） 。在此一情況中，鍺矽化物層9-2係沈積於磊晶矽化物層上。 圖3所示之半導體基板係提供給異質接合面雙極電晶體 (ΗΒΤ)之製造。經由在保護矽化物層9_3上，沈積一具有適 當厚度之矽化物層，此一製造允許形成理想的結構化鍺矽/ 矽（SiGe/Si)接合面。 如果保護矽化物層9-3的厚度等於或超過5〇埃，則是有益 的。具有等於或超過50埃之厚度的保護矽化物層9_3有效地 在化學清洗期間，保護鍺矽化物層9-2免於化學損壞。 另一方面，如果保護石夕化物層9-3之厚度如此薄，以致於 允許保護矽化物層9-3在異質接合面雙極電晶體（hbTs)之 運作上不具實質上的效應，也是有益的。 200302579SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to eliminate defects from a heterojunction bipolar transistor (HBT) including a germanite / lithium joint and to improve the flatness of a layer included in the HBT. In one aspect of the present invention, a semiconductor substrate includes a substrate mainly formed of silicon, a germanium oxide compound deposited to cover the stone substrate, and a protective stone compound substantially composed of the stone compound Floor. The protective stone layer is deposited on the fragmented material layer. The protective layer should be deposited to completely cover the upper surface of the germanium silicide layer. The thickness of the protective layer should be equal to or more than 50 angstroms, and is so limited that the protective layer has no substantial effect on the operation of the heterojunction bipolar transistor. The substrate may include a heavily doped silicon substrate and a lightly doped epitaxial layer. In another aspect of the present invention, a method for manufacturing a semiconductor substrate for producing a heterojunction bipolar transistor includes: providing a substrate mainly formed by silicide; and depositing a germanium silicide layer to cover The substrate; depositing a protective silicide layer on the upper surface of the germanium silicide layer. In yet another aspect of the present invention, a method of manufacturing a heterojunction bipolar transistor includes: providing a semiconductor substrate including: a substrate formed mainly of silicide; and a germanium silicide deposited to cover the substrate A protective silicide layer is deposited on the germanium silicide layer, this protected -10- 200302579 ⑺ the stone oxide layer is essentially composed of stone oxide; on the upper surface of the protected silicide layer, deposit A silicide layer. The manufacturing method preferably includes: chemically cleaning the semiconductor substrate using an acid solution. The chemical cleaning may include at least one of a first immersion bath in a hydrochloric acid solution and a second immersion bath in a solution composed of carbon and hydrogen peroxide. It is beneficial if the manufacturing method includes the following: Exposing the semiconductor substrate to an ozone environment. It is beneficial if the manufacturing method also includes the following: Prior to depositing the silicide layer, the semiconductor substrate is thermally cleaned. Thermal cleaning should be achieved by heat treatment at a temperature higher than 800 degrees Celsius. Brief Description of the Drawings Figure 1 shows a cross-sectional view of a conventional heterojunction bipolar transistor (HBT); Figure 2 shows a conventional CVD apparatus for manufacturing a conventional heterojunction bipolar transistor (ΗΒτ); In a specific embodiment, a semiconductor substrate for manufacturing heterojunction bipolar transistors (HBTs); ° FIG. 4 shows a CVD device for manufacturing a semiconductor beautiful plate in a specific embodiment of the present invention; & Figures 5 to 9 are sectional views showing a process for manufacturing a semiconductor substrate in this embodiment; Figure 10 shows a process for manufacturing heterojunction bipolar transistors (HBTs) in this embodiment Another CVD device of Fig. 11 is a sectional view of Figs. 11 to 14 showing the manufacturing process of heterojunction (8) (8) 200302579 quality junction bipolar transistors (HBTs) in this embodiment; Fig. 1 5 This figure shows the fabricated heterojunction bipolar transistor (HB Ding). . Detailed Description of the Preferred Embodiments FIG. 3 shows a semiconductor substrate for manufacturing heterojunction bipolar transistors (HBTs) in a specific embodiment of the present invention. As shown in FIG. 3, the semiconductor substrate includes an n-type silicon substrate 9-1, a p-type germanium silicide layer 9-2, and a thin hafnium-preserving silicide layer 9-3. The germanium silicide layer 9-2 is deposited on the main (upper) surface of the silicon substrate 9_ 丨, and the protective silicide layer 9-3 is deposited on the germanium silicide layer 9-2. The protective silicide layer 9_3 completely covers the upper surface of the germanium silicide layer 9_2. As will be described below, the silicide layer 9-3 is used as a protective layer. It should be noted that the silicon substrate 9-1 may include a heavily doped n-type substrate, and a lightly doped epitaxial silicide layer (not shown) deposited on the heavily doped n-type substrate. In this case, the germanium silicide layer 9-2 is deposited on the epitaxial silicide layer. The semiconductor substrate shown in FIG. 3 is provided for the manufacture of a heterojunction bipolar transistor (HBT). By depositing a silicide layer of appropriate thickness on the protective silicide layer 9_3, this fabrication allows the formation of an ideal structured germanium-silicon / silicon (SiGe / Si) junction. It is advantageous if the thickness of the protective silicide layer 9-3 is 50 angstroms or more. The protective silicide layer 9_3 having a thickness equal to or more than 50 Angstroms effectively protects the germanium silicide layer 9-2 from chemical damage during chemical cleaning. On the other hand, if the thickness of the protective silicide layer 9-3 is so thin that it allows the protective silicide layer 9-3 to have no substantial effect on the operation of the heterojunction bipolar transistor (hbTs), it is also beneficial of. 200302579
(9) 下列是製造圖3所示之半導體基板的製程。 圖4顯示用來製造半導體基板之cvd裝置ίο-丨。鍺矽化物 層9-2與保護矽化物層9-3之沈積係藉由CVD裝置1〇-1來達 成。此一 CVD裝置10-1包含一沈積反應室卜丨。真空幫浦2-1 連接到沈積反應室1-1以將沈積反應室U抽真空。用來固 定基板6-1的基板支架3-1放置在沈積反應室1 —丨中。基板支 架3-1包含一加熱器4-1以加熱基板至理想的溫度。沈積反 應室1-1具有一來源氣體5-1。來源氣體5-1包含曱石夕烧與鍺 烧。當沈積摻雜η型或p型雜質的薄膜時，可以添加磷化氫 氣體與乙硼烷氣體到來源氣體5 -1中。安排承載搖動反應室 7-1與通道閥門8-1以將基板6-1載入沈積反應室1_丨中。基板 6-1係經由通道閥門8-1，從承載搖動反應室1載入沈積反 應室1 -1。 製k半導體基板的製程始於提供如圖5所示之碎基板9-1 。此一石夕基板9-1具有一 <100>之結晶方向，與4英忖（jn)的 直徑。在鍺矽化物層9-2的沈積之前，矽基板9-1的表面以 RCA清洗洗淨。如上所述，rcA清洗包含一系列步驟： (1) 純水清洗數分鐘； (2) 在攝氏75度下，浸浴於溶液中數分鐘，此一溶液由 氣氧化銨，過氧化氫，與水所組成； (3) 純水清洗數分鐘； (4) 於室溫下，浸浴於1%重量百分比的氟氫酸中數分鐘； (5) 純水清洗數分鐘； (6) 在室溫下，浸浴於溶液中數分鐘，此一溶液由鹽酸 200302579(9) The following is a process for manufacturing the semiconductor substrate shown in FIG. 3. FIG. 4 shows a cvd device for manufacturing a semiconductor substrate. The germanium silicide layer 9-2 and the protective silicide layer 9-3 are deposited by a CVD apparatus 10-1. The CVD apparatus 10-1 includes a deposition reaction chamber. A vacuum pump 2-1 is connected to the deposition reaction chamber 1-1 to evacuate the deposition reaction chamber U. A substrate holder 3-1 for fixing the substrate 6-1 is placed in the sedimentation reaction chamber 1-丨. The substrate holder 3-1 includes a heater 4-1 to heat the substrate to a desired temperature. The deposition reaction chamber 1-1 has a source gas 5-1. The source gas 5-1 contains vermiculite and germanium. When depositing a thin film doped with n-type or p-type impurities, phosphine gas and diborane gas may be added to the source gas 5-1. The load-bearing shaking reaction chamber 7-1 and the channel valve 8-1 are arranged to load the substrate 6-1 into the deposition reaction chamber 1_ 丨. The substrate 6-1 is loaded into the deposition reaction chamber 1 -1 from the load-shaking reaction chamber 1 via the passage valve 8-1. The process of manufacturing a k semiconductor substrate begins with providing a broken substrate 9-1 as shown in FIG. This stone substrate 9-1 has a crystal orientation of < 100 > and a diameter of 4 inches (jn). Prior to the deposition of the germanium silicide layer 9-2, the surface of the silicon substrate 9-1 is cleaned and washed with RCA. As mentioned above, rcA cleaning involves a series of steps: (1) pure water cleaning for several minutes; (2) immersed in a solution for several minutes at 75 degrees Celsius, this solution consists of gas ammonium oxide, hydrogen peroxide, and Water composition; (3) Wash with pure water for several minutes; (4) Soak in 1% by weight of hydrofluoric acid for several minutes at room temperature; (5) Wash with pure water for several minutes; (6) In the room At room temperature, immerse in the solution for several minutes. This solution is made of hydrochloric acid 200302579.
(ίο) ，過氧化氫，與水所組成； (7) 純水清洗數分鐘； (8) 在室溫下，浸浴於1%重量百分比的氟氫酸中數分鐘； (9) 純水清洗數分鐘； (1〇)在室溫下，浸浴於溶液中數分鐘，此一溶液由硫酸 ，過氧化氫，與水所組成； (11) 純水清洗數分鐘；及 (12) 自旋乾燥。 在RAC清洗之後，如圖6所示，矽基板9-1被載入沈積反 應室1-1中，接著固定於基板支架3-1。接著以真空幫浦2-1 將沈積反應室1 -1抽真空至1 x 1 〇-9托（T〇rr)。在抽真空之後 ，如圖7所示，矽基板9-1以攝氏8〇〇度9〇〇度之溫度熱清洗5 。熱處理有效地從石夕基板9-1的表面上移除氧與碳。 在熱清洗之後’矽基板9-1的溫度接著被調節到攝氏7〇〇 度。然後’如圖8所示，沈積鍺矽化物層9 — 2與保護矽化物 層 9-3。 沈積的詳細過程如下。包含乙矽烷與鍺烷的來源氣體5-1 供應到沈積反應室1 -1中。調整鍺烧的分壓到4 χ 1 托 (Torr)。來源氣體5-1之1〇分鐘的供應，在石夕基板上沈積 2000埃的鍺石夕化物層9-2。沈積的溫度超過攝氏5〇〇度，有 效地幫助曱矽烷的反應，因而改善了鍺矽化物層9-2的結晶 度。 鍺矽化物層9-2與保護矽化物層9_3的沈積係藉由下列反 應方程式所表示的反應來達成： 200302579(ίο), consisting of hydrogen peroxide and water; (7) washing with pure water for several minutes; (8) immersed in 1% weight percent hydrofluoric acid for several minutes at room temperature; (9) pure water Wash for several minutes; (10) immerse in a solution for several minutes at room temperature. This solution consists of sulfuric acid, hydrogen peroxide, and water; (11) pure water for several minutes; and (12) from Spin dry. After the RAC cleaning, as shown in FIG. 6, the silicon substrate 9-1 is loaded into the deposition reaction chamber 1-1, and then fixed to the substrate holder 3-1. Next, the deposition reaction chamber 1 -1 was evacuated with vacuum pump 2-1 to 1 x 10-9 Torr (Torr). After evacuation, as shown in FIG. 7, the silicon substrate 9-1 is thermally cleaned at a temperature of 800 ° C to 900 ° C5. The heat treatment effectively removes oxygen and carbon from the surface of the Shixi substrate 9-1. After the thermal cleaning, the temperature of the 'Si substrate 9-1 was then adjusted to 700 ° C. Then, as shown in FIG. 8, a germanium silicide layer 9-2 and a protective silicide layer 9-3 are deposited. The detailed process of deposition is as follows. A source gas 5-1 containing disilane and germane is supplied to the deposition reaction chamber 1 -1. Adjust the partial pressure of germanium to 4 x 1 Torr. The supply of the source gas 5-1 was 10 minutes, and a 2000 angstrom germanium oxide compound layer 9-2 was deposited on the Shixi substrate. The deposition temperature exceeds 500 ° C, which effectively assists the reaction of osmium silane, thereby improving the crystallinity of the germanium silicide layer 9-2. The deposition of the germanium silicide layer 9-2 and the protective silicide layer 9_3 is achieved by a reaction represented by the following reaction equation: 200302579
0000
Si2H6(氣體）+2Si — 2Si(吸收）+6H(吸收），Si2H6 (gas) + 2Si — 2Si (absorption) + 6H (absorption),
GeH4(氣體）+ 4Si — 2Ge(吸收）與4H(吸收），及 2H(吸收h2(氣體）。GeH4 (gas) + 4Si — 2Ge (absorption) and 4H (absorption), and 2H (absorption h2 (gas).
在鍺矽化物層9-2的沈積之後，停止鍺烷的供應，但持續 乙矽烷的供應。乙矽烷10秒鐘的供應沈積50埃的保護矽化 物層9-3。在保護矽化物層9-3的沈積之後，停止乙矽烷的 供應與矽基板9-1的加熱。半導體基板的製造過程便完成。 覆蓋鍺矽化物層9-2與保護矽化物層9-3的半導體基板，稱 為半導體基板13。接著半導體基板13從沈積反應室1-1卸下 ’並暴露於圖9所示的空氣中。 保護矽化物層9-3有效地避免鍺矽化物層9-2表面污染物 。保護矽化物層9_3覆蓋鍺矽化物層9-2，並當作保護層之 用。半導體基板13對空氣的暴露並不會導致鍺矽化物層9_2 表面的污染。After the germanium silicide layer 9-2 was deposited, the supply of germane was stopped, but the supply of disilane was continued. A 10 sec supply of disilane deposited a 50 angstrom protective silicide layer 9-3. After the deposition of the protective silicide layer 9-3, the supply of disilane and the heating of the silicon substrate 9-1 are stopped. The manufacturing process of the semiconductor substrate is completed. The semiconductor substrate covering the germanium silicide layer 9-2 and the protective silicide layer 9-3 is referred to as a semiconductor substrate 13. The semiconductor substrate 13 is then removed from the deposition reaction chamber 1-1 and exposed to the air shown in FIG. Protecting the silicide layer 9-3 effectively prevents the surface contamination of the germanium silicide layer 9-2. The protective silicide layer 9_3 covers the germanium silicide layer 9-2 and serves as a protective layer. Exposure of the semiconductor substrate 13 to air does not cause contamination of the surface of the germanium silicide layer 9_2.
半導體基板13對空氣的暴露可能污染保護矽化物層9_3 的表面。可是，很容易以化學清洗來移除保護矽化物層9-3 表面上的污染物。保護矽化物層9-3是抗酸的，其允許使用 化學清洗來清洗半導體基板13。 半導體基板13適合用來製造分別包含鍺矽/矽 異質接合面雙極電晶體（HBTs)。製造異質接合面雙極電晶 體（HBTs)製程敘述如下。 製造過程始於半導體基板13表面的化學清洗。首先，半 導體基板13放到鹽酸溶液中浸浴。此一溶液係以純水稀釋 45重量百分比的鹽酸來製備。浸浴於鹽酸溶液中有效地移 -15- 200302579The exposure of the semiconductor substrate 13 to the air may contaminate the surface of the protective silicide layer 9_3. However, it is easy to remove contaminants on the surface of the protective silicide layer 9-3 by chemical cleaning. The protective silicide layer 9-3 is acid-resistant, which allows the semiconductor substrate 13 to be cleaned using chemical cleaning. The semiconductor substrate 13 is suitable for manufacturing bipolar transistors (HBTs) containing silicon germanium / silicon heterojunction junctions. The process for manufacturing heterojunction bipolar transistors (HBTs) is described below. The manufacturing process begins with chemical cleaning of the surface of the semiconductor substrate 13. First, the semiconductor substrate 13 is immersed in a hydrochloric acid solution. This solution was prepared by diluting 45 weight percent hydrochloric acid with pure water. Effectively transfer in immersion in hydrochloric acid solution -15- 200302579
除半導體基板13表面上的天然氧化物。鹽酸溶液對純水的 體積比是1 : 49。 接著，半導體基板13放到由硫酸與過氧化氫所組成的溶 液中浸浴。硫酸與過氧化氫溶液的體積比是1 : 2。此一溶 液包含硫酸與過氧化氫，其有效地移除半導體基板13表面 上的污染物。 保護矽化物層9-3有效地保護鍺矽化物層9_2免於酸的化 子姓刻’因而保持錯碎化物層9 - 2的平坦度。化學清洗後的 光學微影照相已經證實沒有觀察到表面的不規則，如蝕刻 凹陷。 可經使用X射線光電子光譜儀來分析保護矽化物層9 _ 3表 面上之污染物的濃度。碳濃度少於5x 10u原子/平方公分 (atoms/cm2)，而金屬的濃度則少於偵測下限，也就是說， 少於lx 10"原子/平方公分（atoms/cm2)。已經證實碳與金屬 的濃度是足夠低。氧濃度是在1 X 1〇 Μ原子/平方公分 (atoms/cm2)的量級。約lx 10i5原子/平方公分（at〇ms/cm2) 的氧濃度不是一個問題，因為可以藉由下面敘述的熱清洗 來移除約lx 101：)原子/平方公分（at〇ms/cln2)的氧污染物。 在化學清洗前或後’半導體基板13暴露於臭氧的環境中 是有益的。臭氧環境可以藉由紫外線對空氣輻射來產生。 臭氧環境有效地降低半導體基板1 3表面的碳濃度。 在化學清洗之後，於保護矽化物層9-3上，沈積當作射極 之用的厚矽化物層。矽化物層的沈積係藉由圖丨〇所示之另 一 CVD裝置10-2來達成。此一 CVD裝置10-2的配置與cvd -16- 200302579 (13) 議薩賴rif 裝置10-1的配置完全相同。CVD裝置10-2包含一沈積反應 室1-2。真空幫浦2-2係連接到沈積反應室1-2以將沈積反應 室1-2抽真空。用來固定基板6-2的基板支架3-2包含一加熱 器4-2以將基板6-2加熱至理想的溫度。沈積反應室1-2具有 一來源氣體5-5。來源氣體5-2包含甲矽烷與鍺烷。當沈積 摻雜η型或p型雜質的薄膜時，可以添加磷化氫氣體與乙硼 烷氣體到來源氣體5-2中。安排承載搖動反應室7-2與通道 閥門8 - 2以將基板6 - 2載入沈積反應室1 - 2中。基板6 - 2係經由 通道閥門8-2，從承載搖動反應室7-2載入沈積反應室1-2。 厚的矽化物層的沈積始於將半導體基板13載入圖11所示 之沈積反應室1-2中。如圖12所示，在將沈積反應室1-2抽 真空之後，於攝氏800度〜攝氏900度的溫度，熱清洗半導體 基板13 5分鐘。熱清洗移除半導體基板13表面上的氧。 保護矽化物層9-3完全覆蓋鍺矽化物層9-2，避免熱清洗 期間鍺從鍺矽化物層9-2的蒸發。發明者的實驗已經證實具 有等於或超過50埃厚度的保護矽化物層、3，有效地抑制鍺 的蒸發。 在熱清洗之後，調整半導體基板13的溫度至攝氏7〇〇度， 接著將包含乙矽烧（ShH6)的來源氣體5·2引進圖13所示之 沈積反應至1-2中。乙石夕烧氣體的壓力調整至2 2χ 1〇·4托 (Torr)。可以添加碟化氫或乙爛院氣體到來源氣體5·2中。 乙矽烷氣體的反應沈積矽化物層9_4。矽化物層9-3與9-4 合起來形成厚的矽化物層9-6，而當作射極之用。矽化物層 9-6具有6000埃的厚度。在矽化物層的沈積之後，半導 -17- 200302579The natural oxide on the surface of the semiconductor substrate 13 is removed. The volume ratio of hydrochloric acid solution to pure water is 1:49. Next, the semiconductor substrate 13 is immersed in a solution composed of sulfuric acid and hydrogen peroxide. The volume ratio of sulfuric acid to hydrogen peroxide solution is 1: 2. This solution contains sulfuric acid and hydrogen peroxide, which effectively removes contaminants on the surface of the semiconductor substrate 13. The protection silicide layer 9-3 effectively protects the germanium silicide layer 9_2 from acidification, and thus maintains the flatness of the fragmentation compound layer 9-2. Optical lithography after chemical cleaning has confirmed that no surface irregularities, such as etching depressions, are observed. X-ray photoelectron spectroscopy can be used to analyze the concentration of contaminants on the surface of the protective silicide layer 9_3. The carbon concentration is less than 5x 10u atoms / cm2, and the metal concentration is less than the lower detection limit, that is, less than lx 10 " atoms / cm2. Carbon and metal concentrations have proven to be sufficiently low. The oxygen concentration is on the order of 1 X 10 M atoms / cm2. The oxygen concentration of about lx 10i5 atoms / cm2 (at0ms / cm2) is not a problem, because about lx 101 :) atoms / cm2 (at0ms / cln2) can be removed by the thermal cleaning described below. Oxygen pollutants. It is advantageous to expose the semiconductor substrate 13 to an environment of ozone before or after chemical cleaning. The ozone environment can be generated by ultraviolet radiation to the air. The ozone environment effectively reduces the carbon concentration on the surface of the semiconductor substrate 13. After the chemical cleaning, a thick silicide layer is deposited on the protective silicide layer 9-3 as an emitter. The silicide layer is deposited by another CVD apparatus 10-2 shown in FIG. The configuration of this CVD device 10-2 is exactly the same as the configuration of cvd -16- 200302579 (13) Ursaray rif device 10-1. The CVD apparatus 10-2 includes a deposition reaction chamber 1-2. A vacuum pump 2-2 is connected to the deposition reaction chamber 1-2 to evacuate the deposition reaction chamber 1-2. The substrate holder 3-2 for holding the substrate 6-2 includes a heater 4-2 to heat the substrate 6-2 to a desired temperature. The deposition reaction chamber 1-2 has a source gas 5-5. The source gas 5-2 contains silane and germane. When depositing a thin film doped with n-type or p-type impurities, phosphine gas and diborane gas may be added to the source gas 5-2. The load-bearing shaking reaction chamber 7-2 and the channel valve 8-2 are arranged to load the substrate 6-2 into the deposition reaction chamber 1-2. The substrate 6-2 is loaded into the deposition reaction chamber 1-2 from the load-bearing shaking reaction chamber 7-2 via the passage valve 8-2. The deposition of the thick silicide layer starts by loading the semiconductor substrate 13 into the deposition reaction chamber 1-2 shown in Fig. 11. As shown in FIG. 12, after the deposition reaction chamber 1-2 is evacuated, the semiconductor substrate is thermally cleaned at a temperature of 800 ° C to 900 ° C for 13 minutes. The thermal cleaning removes oxygen on the surface of the semiconductor substrate 13. The protective silicide layer 9-3 completely covers the germanium silicide layer 9-2 to prevent the germanium from evaporating from the germanium silicide layer 9-2 during the thermal cleaning. Experiments by the inventors have confirmed that a protective silicide layer, 3 having a thickness of 50 angstroms or more, effectively suppresses the evaporation of germanium. After the thermal cleaning, the temperature of the semiconductor substrate 13 was adjusted to 700 degrees Celsius, and then a source gas 5.2 containing silicon alumina (ShH6) was introduced into the deposition reaction shown in FIG. 13 to 1-2. The pressure of the Otsuishi Yugaya gas was adjusted to 22 × 10.4 Torr. You can add dished hydrogen or acetic acid gas to the source gas 5.2. The silicide layer 9_4 is deposited by the reaction of the disilane gas. The silicide layers 9-3 and 9-4 are combined to form a thick silicide layer 9-6, which is used as an emitter. The silicide layers 9-6 have a thickness of 6000 Angstroms. After the silicide layer is deposited, the semiconductor -17- 200302579
(14) 體基板13在下文中將稱為半導體基板14。應注意的是因為 經由薄矽化物層9-3的雜質擴散。保護矽化物層9-3的導電 類型可以變成與矽化物層9-4相同的導電類型。 矽化物層9-4的沈積宜在高於攝氏500度的溫度實施。低 於攝氏5 00度的沈積溫度降低沈積速率至低於1〇埃/分鐘， 而增加異質接合面雙極電晶體（HBTs)製造之整個流程的時 間（TAT)。 接著，如圖14所示，半導體基板14自沈積反應室1-2卸載 。光學微影照相已經證實半導體基板14在結晶與平坦度上 是極為優越的。在矽化物層9-6的表面上，沒有觀察到不規 則’同時結晶缺陷的濃度被將降低到低於1 〇〇〇/平方公分 (cm2)。 在石夕化物層9_6形成之後，便蝕刻部分矽化物層9-6，以 暴露出部分鍺矽化物層9-2。基極電極9_7係形成於鍺矽化 物層的暴露部分，而射極電極9-8係形成於矽化物層9_6上 集極電極係形成於石夕基板9-1的背面。石夕基板9-1當作集 二之用鍺石夕化物層9-2當作基極之用，而石夕化物層則 當作射極。應注意的是圖15中的矽基板、丨包含一重摻雜的 石夕基板9-la與一少量摻雜的磊晶矽化物層9_ 。 并入矽化物層9-6的保護矽化物層9-3，因為其薄的厚度 ，在=質接合面雙極電晶體（HBT)的運作上實質上不具效應。 的^執行比較性的實驗證實此一具體實施射製造過程 已經製造出第一個樣品基板，其具有完全等於此一具體 -18- 200302579(14) The bulk substrate 13 will be referred to as a semiconductor substrate 14 hereinafter. It should be noted that the impurities diffuse through the thin silicide layer 9-3. The conductivity type of the protection silicide layer 9-3 can be changed to the same conductivity type as the silicide layer 9-4. The silicide layer 9-4 is preferably deposited at a temperature higher than 500 degrees Celsius. A deposition temperature below 500 ° C reduces the deposition rate to less than 10 Angstroms / minute, and increases the time (TAT) of the entire process of manufacturing heterojunction bipolar transistors (HBTs). Next, as shown in FIG. 14, the semiconductor substrate 14 is unloaded from the deposition reaction chamber 1-2. Optical lithography has confirmed that the semiconductor substrate 14 is extremely superior in crystallinity and flatness. On the surface of the silicide layer 9-6, no irregularities were observed. At the same time, the concentration of crystal defects was reduced to less than 1,000 / cm 2 (cm2). After the stone oxide layer 9_6 is formed, a part of the silicide layer 9-6 is etched to expose a part of the germanium silicide layer 9-2. The base electrode 9_7 is formed on the exposed portion of the germanium silicide layer, and the emitter electrode 9-8 is formed on the silicide layer 9_6. The collector electrode is formed on the back of the Shixi substrate 9-1. The Shi Xi substrate 9-1 is used as a set 2 and the Ge Shi Xi material layer 9-2 is used as the base electrode, and the Shi Xi material layer is used as the emitter electrode. It should be noted that the silicon substrate in FIG. 15 includes a heavily doped Shi Xi substrate 9-la and a lightly doped epitaxial silicide layer 9_. The protective silicide layer 9-3 incorporated in the silicide layer 9-6, because of its thin thickness, has substantially no effect on the operation of the quality junction bipolar transistor (HBT). The implementation of comparative experiments confirms that this specific implementation of the manufacturing process has produced the first sample substrate, which has exactly the same as this specific -18- 200302579
(15) 實施例中之半導體基板13的結構，除了保護矽化物層9-3並 未整合其中。接著對第一個樣品基板實施上述熱清洗。在 熱清洗之後’便直接在鍺矽化物層9-2上沈積矽化物層（對 應於矽化物層9-4)。在沈積的矽化物層中，已經觀察到大 量的堆疊錯誤。堆疊錯誤的濃度是每一平方公分數十萬的 置級。已經考慮到堆疊錯誤係導因於鍺矽化物層9_2上所產 生的蝕刻凹陷。此外，矽化物層沈積之前的熱清洗，已經(15) The structure of the semiconductor substrate 13 in the embodiment is not integrated except for protecting the silicide layer 9-3. Then, the first sample substrate was subjected to the above-mentioned thermal cleaning. After the thermal cleaning ', a silicide layer is deposited directly on the germanium silicide layer 9-2 (corresponding to the silicide layer 9-4). A large number of stacking errors have been observed in the deposited silicide layers. The concentration of stacking errors is a rating of hundreds of thousands per square centimeter. It has been considered that the stacking error is due to the etch depressions generated on the germanium silicide layer 9_2. In addition, the thermal cleaning before silicide layer deposition has been
迫使鍺從鍺矽化物層9_2蒸發。鍺的蒸發已經降低鍺矽化物 層9-2中鍺的濃度。The germanium is forced to evaporate from the germanium silicide layer 9_2. The evaporation of germanium has reduced the germanium concentration in the germanium silicide layer 9-2.
一已經製造其他的樣品基板，其在鍺矽化物層9-2上分別包 含保護矽化物層。保護矽化物層的厚度少於5〇埃。一個樣 加基板包含一 3 0埃厚度的保護矽化物層，而另一個則是包 含40埃厚度的保護矽化物層、3。兩個樣品基板皆有化學清 洗。化學清洗後，在兩個樣品基板中皆觀察到蝕刻凹陷。 接著，在樣品基板上分別形成厚的矽化物層。在厚的矽化 物層沈積後，在兩個樣品基板中，皆觀察到每平方公分有 數千個堆疊錯誤。已經證實比50埃薄的保護矽化物層9_3使 沈積於保護矽化物層9-3上之矽化物層9_4的結晶性惡化。 雖然已經以其相當程度之特殊較佳形式敘述本發明，應 了解的是可以在建構細節中改變本發明之較佳形式，並採 取局部的組合與安排，而不脫離下文申請專利範圍之本發 明的精神與範圍。 -19· 200302579 (16) 圖式代表符號說明 102 s夕基板 103 磊晶矽化物層 101 鍺石夕化物層 104 重摻雜之矽化物層 105, 9-9 集極電極 106, 9-8 射極電極 107, 9-7 基極電極 109 沈積反應室 110 基板支架 111 承載搖動反應室 9-1 η型碎基板 9-2 ρ型鍺碎化物層 9-3, 9-4 保護矽化物層 10-1， 10-2 化學氣相沈積裝置 1-1， 1-2 沈積反應室 2-1，2-2 真空幫浦 3-1， 3-2 基板支架 4-1， 4-2 加熱器 6-1， 6-2 基板 5-1， 5-2 來源氣體 7-1， 7-2 承載搖動反應室 8-1, 8-2 通道閥門 13,14 半導體基板One other sample substrate has been manufactured, which includes a protective silicide layer on the germanium silicide layer 9-2, respectively. The thickness of the protective silicide layer is less than 50 angstroms. One sample substrate contains a protective silicide layer with a thickness of 30 angstroms, and the other contains a protective silicide layer with a thickness of 40 angstroms. Both sample substrates are chemically cleaned. After chemical cleaning, etched depressions were observed in both sample substrates. Next, a thick silicide layer is formed on each of the sample substrates. After the thick silicide layer was deposited, thousands of stacking errors per square centimeter were observed in both sample substrates. It has been confirmed that the protective silicide layer 9_3 thinner than 50 Angstroms deteriorates the crystallinity of the silicide layer 9_4 deposited on the protective silicide layer 9-3. Although the present invention has been described in its particular preferred form, it should be understood that the preferred form of the present invention can be changed in construction details, and partial combinations and arrangements can be adopted without departing from the scope of the present invention, which is under the scope of patent application Spirit and scope. -19 · 200302579 (16) Symbolic representation of the drawing 102 s substrate 103 epitaxial silicide layer 101 germanium oxide layer 104 heavily doped silicide layer 105, 9-9 collector electrode 106, 9-8 emitter Electrode 107, 9-7 Base electrode 109 Deposition reaction chamber 110 Substrate holder 111 Carrying shaking reaction chamber 9-1 η-type broken substrate 9-2 ρ-type germanium fragmentation layer 9-3, 9-4 Protective silicide layer 10 -1, 10-2 Chemical vapor deposition equipment 1-1, 1-2 Deposition reaction chamber 2-1, 2-2 Vacuum pump 3-1, 3-2 Substrate holder 4-1, 4-2 Heater 6 -1, 6-2 Substrates 5-1, 5-2 Source gases 7-1, 7-2 Carrying shaking reaction chambers 8-1, 8-2 Channel valves 13, 14 Semiconductor substrates
-20- 200302579 (17) 9-6 9-la 9-lb 厚的矽化物層 重摻雜之矽基板 少量摻雜之矽基板-20- 200302579 (17) 9-6 9-la 9-lb thick silicide layer heavily doped silicon substrate lightly doped silicon substrate
-21 --twenty one -
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| US7102205B2 (en) * | 2004-09-01 | 2006-09-05 | International Business Machines Corporation | Bipolar transistor with extrinsic stress layer |
| TW200705553A (en) * | 2005-06-28 | 2007-02-01 | Nxp Bv | Doping profile improvement of in-situ doped n-type emitters |
| JP5045095B2 (en) * | 2006-12-26 | 2012-10-10 | 信越半導体株式会社 | Manufacturing method of semiconductor device |
| JP7131835B2 (en) * | 2016-12-07 | 2022-09-06 | ビクトリア リンク リミテッド | Rare earth nitride structures and devices and method for removing passivation capping |
| CN113718257B (en) * | 2021-08-24 | 2023-11-07 | 安徽光智科技有限公司 | Method for etching germanium ingot |
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