TW200301008A - A shadow-creating apparatus - Google Patents

A shadow-creating apparatus Download PDF

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Publication number
TW200301008A
TW200301008A TW091133095A TW91133095A TW200301008A TW 200301008 A TW200301008 A TW 200301008A TW 091133095 A TW091133095 A TW 091133095A TW 91133095 A TW91133095 A TW 91133095A TW 200301008 A TW200301008 A TW 200301008A
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TW
Taiwan
Prior art keywords
wafer
recess
shadow
notch
patent application
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TW091133095A
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Chinese (zh)
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TW577163B (en
Inventor
Malcolm V Hawkes
Jon Stuart Wright
Robert S Burgoyne
Jeffrey L Fish
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Electro Scient Ind Inc
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    • GPHYSICS
    • G01MEASURING; TESTING
    • G01NINVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N21/00Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
    • G01N21/01Arrangements or apparatus for facilitating the optical investigation
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01NINVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N21/00Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
    • G01N21/84Systems specially adapted for particular applications
    • G01N21/88Investigating the presence of flaws or contamination
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01NINVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N21/00Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
    • G01N21/84Systems specially adapted for particular applications
    • G01N21/88Investigating the presence of flaws or contamination
    • G01N21/95Investigating the presence of flaws or contamination characterised by the material or shape of the object to be examined
    • G01N21/956Inspecting patterns on the surface of objects
    • G01N21/95684Patterns showing highly reflecting parts, e.g. metallic elements

Abstract

An apparatus for accurately locating a micro-electronic chip in a chip-holding cavity for visual testing, the chip having at least a front wall and a pair of opposed, spaced-apart side walls, wherein the front wall meets with each of the side walls to from opposed, spaced-apart first and second front edges, comprising a cavity side wall formed to juxtapositionally abut at least one of the side walls of the chip, the cavity side wall having formed therein a depression creating a shadow projecting forward from the depression, wherein the first front edge of the chip forms a border of the shadow to form an objectively measurable contrast in grayness between the shadow and the chip.

Description

200301008 玖、發明說明 【發明所屬之技術領域】 相關申請案之相互參照 本申請案主張美國臨時申請案第6 0/3 3 3,6 9 0 號之權益;該申請案於2 0 0 1年1 1月2 7日提出申請 0 發明所屬之技術領域 本發明係關於微電子晶片之視覺檢查及測試。本發明 尤係關於一種用於方便定位凹口內晶片以開始進行其表面 準確視覺分析之裝置。 先前技術 近來微電子晶片縮小尺寸及此等晶片的大量需求,已 使以快速、準確及具經濟效益的方式測試其物理及電子特 性之需求成爲必要。爲了更有效率地測試晶片,首先必須 從生產線上以視覺方式剔除有缺陷的晶片,使後續電子測、 試只需針對視覺可接受的晶片進行。視覺可觀察的缺陷實 例包括介電體剝離、晶片外部破裂、金屬終端的缺陷(例j 如污跡及外溢)以及不能接受之起伏。產業界使用視覺檢 查設備來測試此類物理特性。此等設備一般具有觀測晶片 所用的攝影裝置、偵測和記錄缺陷的軟體處理裝置,以及 用於照射晶片的明亮光源。 習知的視覺檢查裝置無法準確並有效率地觀測晶片, 因爲晶片和周圍材料的反光値過高。材料的反光値描述其 所反射的光之大小及亮度。平坦的反射物體具有小而亮的 200301008 亮光。不平坦的反射物體具有大而擴散(但仍很亮)的亮 光。反射性較低的物體(不論是否平坦)具有灰暗的亮光 。一般而言,製造視覺檢查處理期間用以包覆晶片的載輪 所使用的習知金屬材料一例如鋁、不銹鋼、鈦等,會因磨 損及金屬上累積的外來物質而產生大量反光。某些處理方 式及塗層可用來降低此等表面的明顯反光,但此類補救方 法屬暫時性,而且會隨著時間變差。以塑膠性或其它類似 材料來取代上述金屬並不有效,因爲塑膠材料固有較弱的 物理特性使其隨著時間磨損。 晶片所顯露的表面附近及其周圍環境的高度反光,使 其很難以電子視覺方式準確測定晶片位在晶片固定凹口內 的位置,以便讓軟體程式能開始針對晶片進行視覺測試。 周圍環境與晶片之亮度和反射光的混合效應會造成幾乎不 可能準確地區別晶片及其所處環境,尤其在高速處理狀態 下一晶片停留在凹口的時間以微秒計,情況更是如此。因 此,在缺乏參考點的情況下,軟體程式將無法在晶片上開 始進行視覺測試,或者在錯誤的參考點上開始進行視覺測 試。 發明內容 本發明係一種產生深色(基本上爲黑色)陰影的裝置 ,該陰影能策略性地鄰接一晶片邊緣之至少一部分,藉以 提供鄰接該陰影的晶片邊緣與該陰影之間的對比。鄰接陰 影的晶片邊緣部分形成一對比線,而此對比線能爲檢查裝 置提供開始進行視覺檢查的參考點。本發明能克服上述習 200301008 知光學檢查方法所伴隨的問題。本發明尤其適用於金屬化 直角平行六面體微電子晶片,此種晶片有至少兩相對且分 離的前邊緣,此等前邊緣係由一前壁與兩相對分離側壁個 別相交所形成。此種晶片係普遍使用於當前電腦業界的類 型。 本發明之裝置包含一凹口(較佳係爲複數個),該凹 口位在晶片搬運裝置之邊緣,例如晶圓搬運輪之周圍,用 以收納晶片。凹口之形狀及大小能收納單一晶片使其處於 垂直位置,並暫時固定晶片讓檢查設備能檢查和測試晶片 表面。凹口具有至少一凹口側壁,並可具有一凹口後壁; 凹口後壁形成垂直於凹口側壁,其協助將晶片固定在凹口 內。當晶片適當定位時,凹口側壁鄰接晶片側壁之至少一 部分。 在本發明之另一實施例中,一部分凹口側壁係形成於 一凹陷內;此凹陷具有一從凹口延伸的第一壁。凹陷位在 晶片側壁附近。此凹陷降低反光量及晶片前緣附近的反光 ,藉以降低檢查裝置偵測晶片邊緣時的干擾。 一個可視見的凹部至少形成於凹口側壁及第一壁。此 凹部之深度足以呈現非常暗(基本上爲黑色)的背景,並 在凹部與晶片之間產生能客觀測量的灰階對比度。晶片在 凹口中的位置上,晶片至少一前緣之至少一部分形成一黑 色陰影或背景之邊界(直線且垂直較佳),進而在晶片前 緣與暗色陰影凹部之間形成淸晰的對比線。此凹部可爲圓 形、橢圓形或從凹口延伸出的水平凹槽。凹部之形狀可由 200301008 不同因素來決定,例如固定晶片的凹口大小和晶片大小。 在本發明之另一實施例中,凹部可進一步沿著凹口側 壁及凹口後壁延伸,以在其內形成一陰影,且該陰影被晶 片之另一前緣遮蔽。產生的陰影在陰影與晶片之間形成可 客觀測量的灰階對比。在晶片另一前緣形成的淸晰對比線 會遮蔽凹口後壁內凹部的暗色陰影。 在光照情況下,對比於晶片與搬運輪的灰色,凹部呈 現爲黑色。晶片附近的凹陷亦會降低周圍環境的反光。對 比線能定位晶片。職是之故,由於凹部內的陰影與晶片之 間呈現明顯的對比,因此檢查裝置能方便且有效率地偵測 晶片邊緣,進而開始進行晶片的視覺測試。 在檢查過程中,晶片藉真空裝置在一位置上固定一段 足夠長的時間,以供檢查裝置進行測試;在此,檢查裝置 可包括電荷耦合元件、軟體檢查單元以及照射源。 因此,本發明之主要目的係提供一種陰影產生裝置, 此種裝置能協助軟體檢查裝置準確定位晶片,以便開始進 行視覺測試處理。本發明之其它目的係提供優於暫時表面 處理及塗層的裝置;在製造及維護方面,此種裝置較爲簡 易且符合經濟效益;此種裝置之製造方式適合任何形狀、 大小及結構的晶片;此種裝置能方便用於當前產業界所採 用的視覺檢查設備;此外,由於視覺檢查設備能迅速且準 確地定出晶片在凹口內的位置,因而此種裝置具高生產率 ,並能生產較佳的最終產品。 參酌較佳實施例之詳細說明連同後附圖式,當能明瞭 9 200301008 本發明之上述及其它目的。本發明人所尋求之保護可由歸 納本說明書的申請專利範圍經公平閱讀而推知。 實施方式 請參照各圖式,其中各元件或限制條件以數字標示; 在十二個圖式中,相同的元件或限制條件係以相同數字標 示。圖1與圖2顯示本發明所針對的微電子晶片2 ;微電 子晶片2槪括包含一矩形固體封閉體4,此封閉體由至少 一前壁5和一組相對分隔的側壁6和7所構成,其中前壁 5與各側壁6和7係相接而形成各自相對分隔的第一前緣 8與第二前緣9。搭配用於本發明的晶片2具有一對用於 連接電路板的金屬化分隔終端1 0。晶片2亦可爲角度大 於或小於9 0度的平行六面體,而且可爲其它形狀。然而 ,正矩形的平行六面體晶片爲工業標準,且爲本發明主要 針對的產品。 如圖3與圖8所示,本發明之設備1 2包含一形成於 晶片搬運裝置1 4 (例如晶片搬運輪1 6 )內的凹口或容 器1 3,用以收納晶片2供貨,以便能安排晶片2接受檢 查及測試。晶片搬運裝置1 4類似於美國專利第6,2 9 4, 7 4 7號所描述的晶片搬運裝置,其包含一晶片搬運輪1 6,尤指具外緣1 8的晶片載運輪。晶片搬運輪1 6有至 少一凹口 1 3 (但具複數個凹口較佳),其形成於外緣1 8用於收納晶片2 ;凹口 1 3之形狀及大小能將單一晶片 2收納於各凹口 1 3而成垂直位置。 如圖3、7a、7b和7c所示,凹口 13由至少一 200301008 凹口側壁2 4界定;當晶片2適當定位在凹口 1 3內時, 凹口側壁2 4與晶片2之至少一部分的側壁6並列鄰接。 凹口 1 3另由凹口後壁2 6界定;以較佳實施例而言,凹 口後壁2 6與凹口側壁2 4相互垂直。另形成與第一側壁 2 4分隔的凹口側壁2 8,以協助將晶片2放入凹口 1 3 內。凹口 13亦有一底面(圖中未顯示),且晶片2可靜 置於底面上。如圖4與圖5所示,本發明之另一實施例顯 示:凹口側壁2 4鄰接晶片2之側壁6,且部分形成於從 凹口13延伸出的第一壁30內。第一壁30從凹口13 延伸之處形成有一凹陷3 2。凹陷3 2位在晶片2之側壁 6的附近。 如圖4、5和7所示,一個凹部3 4係形成於凹口側 壁2 4內,且凹部3 4之寬度和深度足以從凹口 1 3側邊 投影出黑色陰影,並可在凹部3 4與晶片2之間產生可客 觀測量的灰階對比。晶片2在凹口 1 3中的位置上,前緣 8之至少一部分形成一黑色陰影或背景之邊界(直線且垂 直係較佳),進而在晶片2之第一前緣8與暗色陰影凹部 3 4之間形成淸晰的對比線。以較佳實施例而言,凹部3 4之高度高於底壁且低於晶片終端1 〇之頂壁。在較佳實 施例中,根據電子工業協會的灰階標準,凹部3 4內產生 的陰影與晶片2之前壁5的灰階差異程度高達1 5灰階單 位,或至少爲1 6灰階單位。從純白一端至純黑另一端, 灰階被客觀地區分成2 5 5個色度,並爲色彩工業所認可 。凹部3 4可切入或鑽入晶片搬運輪1 6,其深度取決於 11 200301008 各種因素,例如凹口 1 3之大小和深度以及晶片2之大小 。凹部34可爲圓形(圖7a)、橢圓形(圖7b)或從 第一壁30內凹口13延伸出的水平凹槽(圖7c)。在 本發明之另一實施例中,圖9顯示凹部3 4沿著凹口側壁 2 4及凹口後壁2 6延伸,並在其內形成一陰影,且該陰 影被晶片2之另一前緣9遮蔽。產生的陰影在後壁2 6內 的陰影與晶片2之間形成可客觀測量的灰階對比。 如圖10所示,設備12可包含固定裝置40,用於 將晶片2暫時固定在凹口 1 3內以供檢查。固定裝置4 0 包含一真空源(圖中未顯示)及真空傳輸通道4 2 ;真空 傳輸通道4 2從真空源通到開入凹口 1 3內的真空槽4 4 。在檢查過程中,真空有助於將晶片2固定在凹口 1 3內 〇 一個定位裝置(圖中未顯示)係用於定出放置在凹口 1 3內的晶片位置。定位裝置可包含電荷耦合元件攝影機 (圖中未顯示)及充足的光源(圖中未顯示);電荷耦合 元件攝影機可收集及聚焦晶片2之影像,並將此等影像傳 送到附近的檢查裝置一例如影像處理單元(圖中未顯示) ,光源可定出晶圓2之邊緣8位置,而邊緣8遮蔽具暗色 陰影的凹部3 4。凹部3 4與晶片2之間的對比線爲檢查 裝置提供定出晶片2位置的參考點,以便讓檢查裝置能開 始進行測試程序。 雖然本發明已參照其特定實施例加以說明,但熟習此 項技術者當能針對在此描述的本發明實施例進行各式變更 12 200301008 而仍不脫離本發明之實質精神及範圍。吾人當能預期,若 各式元件及步驟之所有組合方式以實質上相同的手段執行 實質上等效的功能而達成實質上相同的結果,則此等組合 方式均爲本發明之範圍所涵蓋。 圖式簡單說明 (一)圖式部分 圖1爲本發明之直角平行六面體微電子晶片之立體圖; 圖2爲晶片之前視圖,其顯示本發明所界定的第一和第二 前緣; 圖3爲形成於典型的晶片搬運輪內的典型的凹口之立體圖 ,其顯示凹口側壁,其中可視見陰影產生的凹部係根據本 發明之教示形成; 圖4爲另一凹口之立體圖,其顯示凹口側壁與第一壁內已 形成陰影產生的凹陷; 圖5爲另一凹口之立體圖,其顯示出凹口側壁與第一壁, 其中形成的水平凹槽進一步延伸至壁內; 圖6爲圖1所示晶片裝入凹口內之立體圖; 圖7 a爲晶片裝入圖6所示凹口內之前視圖,其顯示第一 前緣,該第一前緣形成由圓形凹部所產生的陰影界線; 圖7 b爲晶片裝入圖6所示凹口內之前視圖,其顯示第一 前緣,該第一前緣形成由橢圓形凹部所產生的陰影界線; 圖7 c爲晶片裝入圖6所示凹口內之前視圖,其顯示第一 前緣,該第一前緣形成由水平溝槽凹部所產生的陰影界線 13 200301008 圖8爲晶片搬運輪之立體圖,其中顯示一部分輪的分離視 圖,並顯示凹部、凹口、凹口側壁之關係,且晶片位在凹 口內; 圖9爲晶片位在凹口內的前視圖,其顯示第二前緣遮蔽沿 著凹口後壁形成的凹部所產生的陰影; 圖10爲典型的真空裝置之透視圖。 (二)元件代表符號 2 微電子晶片 4 封閉體 5 前壁 6 側壁 7 側壁 8 第一前緣 9 第二前緣 10 終端 1 2 本發明之設備 13 凹口 14 晶片搬運裝置 16 晶片搬運輪 18 外緣 2 4 凹口側壁 2 6 凹口後壁 2 8 凹口側壁 3 0 第一壁200301008 发明 Description of the invention [Technical field to which the invention belongs] Cross-reference to related applications This application claims the benefit of US Provisional Application No. 6 0/3 3 3, 6 90; this application was filed in 2001 1 Application was filed on January 2 0. TECHNICAL FIELD The present invention relates to visual inspection and testing of microelectronic wafers. More particularly, the present invention relates to a device for conveniently positioning a wafer in a recess to begin accurate visual analysis of its surface. Prior art Recent reductions in the size of microelectronic wafers and the large demand for these wafers have necessitated the need to test their physical and electronic characteristics in a fast, accurate and cost-effective manner. In order to test wafers more efficiently, defective wafers must first be removed from the production line visually, so that subsequent electronic testing and testing need only be performed on visually acceptable wafers. Examples of visually observable defects include dielectric peeling, external cracking of wafers, defects in metal terminations (such as smudges and spills), and unacceptable fluctuations. The industry uses visual inspection equipment to test such physical characteristics. These devices typically have a photographic device for observing the wafer, a software processing device for detecting and recording defects, and a bright light source for illuminating the wafer. The conventional visual inspection device cannot accurately and efficiently observe the wafer because the reflection of the wafer and surrounding materials is too high. The reflection of a material describes the magnitude and brightness of the light it reflects. Flat reflective objects have small, bright 200301008 light. Uneven reflective objects have large, diffused (but still very bright) bright light. Low-reflective objects (whether flat or not) have dim, bright light. Generally speaking, conventional metal materials such as aluminum, stainless steel, titanium and the like used to manufacture a carrier wheel for coating a wafer during a visual inspection process generate a large amount of reflection due to abrasion and foreign substances accumulated on the metal. Certain treatments and coatings can be used to reduce the apparent reflection of these surfaces, but such remedies are temporary and will deteriorate over time. Substituting plastic or other similar materials for these metals is not effective because plastic materials have inherently weak physical properties that cause them to wear out over time. The highly reflective light near the exposed surface of the wafer and its surrounding environment makes it difficult to accurately determine the position of the wafer in the wafer's fixed notch by electronic vision, so that the software program can start a visual test of the wafer. The mixed effects of the surrounding environment and the brightness and reflected light of the wafer will make it almost impossible to accurately distinguish the wafer and its environment, especially in the high-speed processing state, the time that the wafer stays in the notch is measured in microseconds, and this is especially true . Therefore, in the absence of a reference point, the software program will not be able to start a visual test on the chip or start a visual test on the wrong reference point. SUMMARY OF THE INVENTION The present invention is a device for generating a dark (substantially black) shadow that strategically abuts at least a portion of a wafer edge, thereby providing a contrast between a wafer edge adjacent to the shadow and the shadow. The edge portion of the wafer adjacent to the shadow forms a contrast line, which can provide a reference point for the inspection device to start the visual inspection. The present invention can overcome the problems associated with the above-mentioned conventional optical inspection method. The invention is particularly applicable to metallized rectangular parallelepiped microelectronic wafers. Such wafers have at least two opposed and separated front edges. These front edges are formed by the intersection of a front wall and two opposite separated sidewalls. This type of chip is commonly used in the current computer industry. The device of the present invention includes a notch (preferably a plurality of notches), which is located at the edge of the wafer handling device, such as around a wafer handling wheel, for receiving a wafer. The shape and size of the notch can accommodate a single wafer in a vertical position, and temporarily fix the wafer so that the inspection equipment can inspect and test the surface of the wafer. The notch has at least one notch side wall, and may have a notch back wall; the notch back wall is formed perpendicular to the notch side wall, which helps to secure the wafer in the notch. When the wafer is properly positioned, the notch sidewall abuts at least a portion of the wafer sidewall. In another embodiment of the present invention, a part of the side wall of the notch is formed in a recess; the recess has a first wall extending from the recess. The depression is located near the sidewall of the wafer. This depression reduces the amount of light reflection and the reflection near the leading edge of the chip, thereby reducing interference when the inspection device detects the edge of the chip. A visible recess is formed at least on the sidewall of the recess and the first wall. This recess is deep enough to present a very dark (basically black) background, and produces a grayscale contrast that can be objectively measured between the recess and the wafer. At the position of the wafer in the notch, at least a part of at least a leading edge of the wafer forms a black shadow or background boundary (straight and vertical is preferred), and a clear contrast line is formed between the wafer leading edge and the dark shadow recess. This recess can be round, oval or a horizontal groove extending from the notch. The shape of the recess can be determined by various factors such as 200301008, such as the size of the notch and the size of the wafer. In another embodiment of the present invention, the recess may further extend along the side wall of the recess and the rear wall of the recess to form a shadow therein, and the shadow is shielded by another leading edge of the wafer. The resulting shadow creates an objectively measurable grayscale contrast between the shadow and the wafer. A sharp contrast line formed on the other leading edge of the wafer can mask dark shadows in the recesses in the back wall of the notch. Under light, the recesses appear black compared to the gray of the wafer and the carrier wheel. Depressions near the wafer also reduce reflections from the surrounding environment. The alignment line can locate the wafer. Because of the obvious contrast between the shadow in the recess and the wafer, the inspection device can easily and efficiently detect the edge of the wafer, and then start the visual test of the wafer. During the inspection process, the wafer is held in place by a vacuum device for a period of time long enough for the inspection device to test; here, the inspection device may include a charge coupled element, a software inspection unit, and an irradiation source. Therefore, the main object of the present invention is to provide a shadow generating device which can assist a software inspection device to accurately position a chip so as to start a visual test process. Other objects of the present invention are to provide a device superior to temporary surface treatment and coating. In terms of manufacturing and maintenance, this device is relatively simple and economical. The manufacturing method of this device is suitable for chips of any shape, size and structure. ; This device can be conveniently used in the visual inspection equipment used in the current industry; In addition, because the visual inspection equipment can quickly and accurately determine the position of the wafer in the notch, this device has high productivity and can produce Better end product. The above and other objects of the present invention will be made clear by referring to the detailed description of the preferred embodiment together with the following drawings. The protection sought by the inventor can be inferred from the fairness of the patent application summarizing this specification. Implementation Please refer to the drawings, in which each element or restriction is indicated by a number; in the twelve drawings, the same element or restriction is indicated by the same number. Figures 1 and 2 show the microelectronic wafer 2 targeted by the present invention; the microelectronic wafer 2 includes a rectangular solid enclosure 4 which is composed of at least a front wall 5 and a set of relatively separated side walls 6 and 7. Structure, wherein the front wall 5 is connected to each of the side walls 6 and 7 to form a first front edge 8 and a second front edge 9 which are relatively separated from each other. The chip 2 used in the present invention has a pair of metallized separation terminals 10 for connecting circuit boards. The wafer 2 may be a parallelepiped with an angle greater than or less than 90 degrees, and may have other shapes. However, a regular rectangular parallelepiped wafer is an industry standard and is a product mainly targeted by the present invention. As shown in FIG. 3 and FIG. 8, the device 12 of the present invention includes a notch or container 13 formed in a wafer handling device 14 (for example, a wafer handling wheel 16) to accommodate the supply of wafers 2 so that Can arrange for wafer 2 to be inspected and tested. The wafer handling device 14 is similar to the wafer handling device described in US Patent Nos. 6, 2 94, 7 4 7 and includes a wafer handling wheel 16, particularly a wafer carrying wheel with an outer edge 18. The wafer transfer wheel 16 has at least one notch 13 (but it is better to have a plurality of notches), which is formed on the outer edge 18 for receiving the wafer 2; the shape and size of the notch 13 can accommodate a single wafer 2 The vertical positions are formed in each of the notches 13. As shown in FIGS. 3, 7a, 7b, and 7c, the notch 13 is defined by at least one 200301008 notch sidewall 24; when the wafer 2 is properly positioned within the notch 13, the notch sidewall 24 and at least a portion of the wafer 2 The side walls 6 adjoin one another side by side. The notch 13 is further defined by a notch rear wall 26; in a preferred embodiment, the notch rear wall 26 and the notch sidewall 24 are perpendicular to each other. A notch sidewall 28 is formed to be separated from the first sidewall 24 to assist in placing the wafer 2 into the notch 1 3. The notch 13 also has a bottom surface (not shown in the figure), and the wafer 2 can rest on the bottom surface. As shown in FIGS. 4 and 5, another embodiment of the present invention shows that the notch sidewall 24 is adjacent to the sidewall 6 of the wafer 2 and is partially formed in the first wall 30 extending from the notch 13. A recess 32 is formed in the first wall 30 where it extends from the notch 13. The depression 32 is located near the side wall 6 of the wafer 2. As shown in FIGS. 4, 5 and 7, a recess 34 is formed in the side wall 24 of the recess, and the width and depth of the recess 34 are sufficient to project a black shadow from the side of the recess 1 3, and the recess 3 There is an objectively measurable grayscale contrast between 4 and wafer 2. At the position of the chip 2 in the notch 1 3, at least a part of the leading edge 8 forms a border of black shadow or background (straight and vertical is preferred), and then the first leading edge 8 of the chip 2 and the dark shadow recess 3 4 forms a sharp contrast line. In a preferred embodiment, the height of the concave portion 34 is higher than the bottom wall and lower than the top wall of the wafer terminal 10. In a preferred embodiment, according to the gray scale standard of the Electronics Industry Association, the degree of difference between the shadow generated in the recess 34 and the gray scale of the front wall 5 of the wafer 2 is as high as 15 gray scale units, or at least 16 gray scale units. From one end of pure white to the other end of pure black, the gray scale is objectively divided into 255 chromaticities, and is recognized by the color industry. The recess 3 4 can be cut into or drilled into the wafer carrying wheel 16, and its depth depends on various factors such as the size and depth of the notch 13 and the size of the wafer 2. The recess 34 may be circular (Fig. 7a), oval (Fig. 7b) or a horizontal groove extending from the notch 13 in the first wall 30 (Fig. 7c). In another embodiment of the present invention, FIG. 9 shows that the recessed portion 34 extends along the recessed side wall 24 and the recessed rear wall 26, and forms a shadow therein, and the shadow is covered by another front of the wafer 2. Edge 9 is obscured. The resulting shadow forms an objectively measurable grayscale contrast between the shadow in the back wall 26 and the wafer 2. As shown in Fig. 10, the apparatus 12 may include a fixing device 40 for temporarily fixing the wafer 2 in the notch 13 for inspection. The fixing device 40 includes a vacuum source (not shown in the figure) and a vacuum transmission channel 4 2; the vacuum transmission channel 42 passes from the vacuum source to the vacuum groove 4 4 in the opening 13. During the inspection, the vacuum helps to secure the wafer 2 in the notch 13. A positioning device (not shown) is used to determine the position of the wafer placed in the notch 13. The positioning device may include a charge-coupled element camera (not shown) and a sufficient light source (not shown); the charge-coupled element camera can collect and focus the image of the wafer 2 and transmit these images to a nearby inspection device. For example, an image processing unit (not shown in the figure), the light source can determine the position of the edge 8 of the wafer 2, and the edge 8 covers the concave portion 34 with a dark shadow. The contrast line between the recess 34 and the wafer 2 provides a reference point for the inspection device to determine the position of the wafer 2 so that the inspection device can start the test procedure. Although the present invention has been described with reference to specific embodiments thereof, those skilled in the art can make various changes to the embodiments of the invention described herein without departing from the true spirit and scope of the present invention. We can expect that if all combinations of various elements and steps perform substantially equivalent functions and achieve substantially the same results by substantially the same means, these combinations are all covered by the scope of the present invention. Brief description of the drawings (1) Schematic part FIG. 1 is a perspective view of a right-angled parallelepiped microelectronic wafer of the present invention; FIG. 2 is a front view of the wafer showing the first and second leading edges defined by the present invention; 3 is a perspective view of a typical notch formed in a typical wafer conveying wheel, showing a side wall of the notch, in which the recessed portion where the shadow can be seen is formed according to the teaching of the present invention; FIG. 4 is a perspective view of another notch, which Shows that the depression caused by the shadow has been formed in the side wall of the notch and the first wall; FIG. 5 is a perspective view of another notch, showing the side wall of the notch and the first wall, and the horizontal groove formed therein further extends into the wall; 6 is a perspective view of the wafer into the notch shown in FIG. 1; FIG. 7a is a front view of the wafer into the notch shown in FIG. 6, which shows a first leading edge formed by a circular recess The generated shadow boundary; FIG. 7b is a front view of the wafer inserted into the notch shown in FIG. 6, which shows a first leading edge that forms a shadow boundary generated by an oval recess; FIG. 7c is a wafer Front view into the notch shown in Figure 6 , Which shows a first leading edge that forms a shadow boundary line created by a horizontal groove recess 13 200301008 FIG. 8 is a perspective view of a wafer carrying wheel, showing a separated view of a part of the wheel, and showing the recess, notch, The relationship between the side walls of the notch and the wafer is located in the notch; FIG. 9 is a front view of the wafer in the notch, which shows the shadow generated by the second leading edge shielding the recess formed along the back wall of the notch; FIG. 10 It is a perspective view of a typical vacuum device. (II) Symbols of component 2 Microelectronic wafer 4 Enclosed body 5 Front wall 6 Side wall 7 Side wall 8 First leading edge 9 Second leading edge 10 Terminal 1 2 Device of the present invention 13 Notch 14 Wafer handling device 16 Wafer handling wheel 18 Outer edge 2 4 Notch side wall 2 6 Notch back wall 2 8 Notch side wall 3 0 First wall

14 200301008 3 2 凹陷 3 4 凹部 4 0 固定裝置 4 2 真空傳輸通道 4 4 真空槽14 200301008 3 2 Depression 3 4 Depression 4 0 Fixing device 4 2 Vacuum transmission channel 4 4 Vacuum tank

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Claims (1)

200301008 拾、申請專利範圍 1 .一種準確定出微電子晶片在晶片固定凹口內位置以 利進行光學測試之裝置,該晶片具有至少一前壁及一組相 對且分隔的側壁,其中該前壁與各側壁相接而形成相對且 分隔的第一和第二前緣,該裝置包含: a .—凹口側壁,該凹口側壁與該晶片之至少一側壁並 列鄰接;且 b .該凹口側壁在其內形成一凹部,該凹部產生一陰影 ,該陰影從該凹部向前投影,其中該晶片之第一前緣形成 該陰影之邊界,藉以在該陰影與該晶片之間形成可客觀測 量的灰階對比。 2 .如申請專利範圍第1項之裝置,其中該晶片之第一 前緣形成該陰影之直線邊界。 3 .如申請專利範圍第1項之裝置,其中該晶片之第一 前緣形成該陰影之垂直邊界。 4 .如申請專利範圍第1項之裝置,其另包含一用於暫 時將該晶片固定在該凹口內的真空固定裝置,該真空固定 裝置包含一真空源及一真空傳輸通道,該真空傳輸通道從 該真空源通到該凹口,其針對該晶片施加真空作用以協助 將該晶片固定在該凹口內。 5 .如申請專利範圍第1項之裝置,其中該陰影化凹部 之灰階與晶片前緣之灰階的差異程度在2 5 5單位的工業 灰階上高達1 5灰階單位。 6 .如申請專利範圍第1項之裝置,其中該陰影化凹部 之灰階與晶片前緣之灰階的差異程度在2 5 5單位的工業 16 200301008 灰階上至少爲1 6灰階單位。 7 .如申請專利範圍第1項之裝置,其中該凹部爲圓形 〇 8 .如申請專利範圍第1項之裝置,其中該凹部爲橢圓 形。 9 .如申請專利範圍第1項之裝置,其中該凹部爲一水 平凹槽。 1 〇 .如申請專利範圍第1項之裝置,其中該凹口由一 凹口後壁界定。 1 1 .如申請專利範圍第1項之裝置,其中該凹部係沿 該凹口側壁與該凹口後壁延伸而產生一陰影,該陰影爲該 晶片之另一前緣所遮蔽,該凹口後壁之凹部內產生的陰影 在該陰影與該晶片之間形成可客觀測量的灰階對比。 1 2.—種準確定出微電子晶片在晶片固定凹口內位置 以利進行光學測試之裝置,該晶片具有至少一前壁及一組 相對且分隔的側壁,其中該前壁與各側壁相接而形成相對 分隔的第一和第二前緣,該裝置包含: a .—凹口側壁,該凹口側壁與該晶片之至少一側壁並 列鄰接,該凹口側壁部分地形成於第一壁之內,並沿該凹 口延伸而形成一凹陷,該凹陷位在該晶片之側壁與第一前 緣附近;且 b ·該凹口側壁與該第一壁在其內形成一凹部並產生一 陰影,該陰影從該凹部向前投影,其中該晶片之第一前緣 形成該陰影之邊界,藉以在該陰影與該晶片之間形成可客 觀測量的灰階對比。 200301008 1 3 .如申請專利範圍第1 2項之裝置,其中該晶片之 第一前緣形成該陰影之直線邊界。 1 4 ·如申請專利範圍第1 2項之裝置,其中該晶片之 第一前緣形成該陰影之直線垂直邊界。 1 5 .如申請專利範圍第1 2項之裝置,其另包含一用 於暫時將該晶片固定在該凹口內的真空固定裝置,其中該 真空固定裝置包含一真空源及一真空傳輸通道,該真空傳 輸通道從該真空源通到該凹口,其針對該晶片施加真空作 用以協助將該晶片固定在該凹口內。 1 6 .如申請專利範圍第1 2項之裝置,其中該陰影化 凹部之灰階與晶片前緣之灰階的差異程度在2 5 5單位的 工業灰階上高達1 5灰階單位。 1 7 .如申請專利範圍第1 2項之裝置,其中該陰影化 凹部之灰階與晶片前緣之灰階的差異程度在2 5 5單位的 工業灰階上至少爲1 6單位。 1 8 .如申請專利範圍第1 2項之裝置,其中該凹部爲 圓形。 1 9 .如申請專利範圍第1 2項之裝置,其中該凹部爲 橢圓形。 2 0 .如申請專利範圍第1 2項之裝置,其中該凹部爲 一水平凹槽。 2 1 .如申請專利範圍第1 2項之裝置,其中該凹口由 一凹口後壁界定。 2 2 .如申請專利範圍第1 2項之裝置,其中該凹部沿 該凹口側壁與該凹口後壁延伸而產生一陰影,該陰影爲該 200301008 晶片之另一前緣所遮蔽,該凹口後壁之凹部內產生的陰影 在該陰影與該晶片之間形成可客觀測量的灰階對比。 拾壹、圖式 如次頁200301008 Patent application scope 1. A device for accurately determining the position of a microelectronic wafer in a wafer fixing recess for optical testing, the wafer having at least one front wall and a set of opposite and separated side walls, wherein the front wall The first and second leading edges that are opposite to and separated from each other are formed by the device, and the device includes: a. A notch side wall that is juxtaposed adjacent to at least one side wall of the wafer; and b. The notch The side wall forms a recess therein, the recess generates a shadow, and the shadow is projected forward from the recess, wherein the first leading edge of the wafer forms a boundary of the shadow, thereby forming an objective measurement between the shadow and the wafer Grayscale contrast. 2. The device of claim 1 in which the first front edge of the wafer forms a straight line boundary of the shadow. 3. The device of claim 1 in which the first leading edge of the wafer forms a vertical boundary of the shadow. 4. The device according to item 1 of the patent application scope, further comprising a vacuum fixing device for temporarily fixing the wafer in the notch, the vacuum fixing device includes a vacuum source and a vacuum transmission channel, and the vacuum transmission A channel passes from the vacuum source to the notch, which applies a vacuum to the wafer to assist in fixing the wafer within the notch. 5. The device according to item 1 of the scope of patent application, wherein the difference between the gray scale of the shaded recessed portion and the gray scale of the leading edge of the wafer is as high as 15 gray scale units over the industrial gray scale of 255 units. 6. The device according to item 1 of the scope of patent application, wherein the difference between the gray scale of the shaded recessed portion and the gray scale of the leading edge of the wafer is at least 16 gray scale units in the industrial scale of 255 units of industrial 16 200301008. 7. The device according to item 1 of the scope of patent application, wherein the recessed portion is circular. 8 The device according to item 1 of the scope of patent application, wherein the recessed portion is oval. 9. The device according to item 1 of the patent application, wherein the recess is a horizontal groove. 10. The device according to item 1 of the patent application scope, wherein the notch is defined by a rear wall of the notch. 1 1. The device according to item 1 of the patent application scope, wherein the recess extends along the side wall of the recess and the rear wall of the recess to create a shadow, the shadow is masked by the other leading edge of the wafer, and the recess The shadow generated in the recess of the rear wall forms an objectively measurable gray scale contrast between the shadow and the wafer. 1 2.—A device for accurately determining the position of a microelectronic wafer in a wafer fixing recess for optical testing, the wafer has at least one front wall and a set of opposite and separated side walls, wherein the front wall is in phase with each side wall The first and second leading edges, which are relatively spaced apart, are formed next to each other. The device includes: a. A notch side wall adjoining at least one side wall of the wafer side by side, the notch side wall being partially formed on the first wall Within, and extending along the notch to form a depression, the depression is located near the sidewall and the first leading edge of the wafer; and b. The notch sidewall and the first wall form a recess in it and produce a A shadow, which is projected forward from the recess, wherein the first leading edge of the wafer forms the boundary of the shadow, thereby forming an objectively measurable grayscale contrast between the shadow and the wafer. 200301008 1 3. The device according to item 12 of the patent application scope, wherein the first leading edge of the wafer forms a linear boundary of the shadow. 14 · The device according to item 12 of the patent application range, wherein the first leading edge of the wafer forms a straight vertical boundary of the shadow. 15. The device according to item 12 of the scope of patent application, further comprising a vacuum fixing device for temporarily fixing the wafer in the notch, wherein the vacuum fixing device includes a vacuum source and a vacuum transmission channel, The vacuum transmission channel leads from the vacuum source to the recess, which applies a vacuum to the wafer to assist in fixing the wafer in the recess. 16. The device according to item 12 of the scope of patent application, wherein the difference between the gray scale of the shaded recess and the gray scale of the leading edge of the wafer is as high as 15 gray scale units over the industrial gray scale of 255 units. 17. The device according to item 12 of the scope of patent application, wherein the difference between the gray scale of the shaded recessed portion and the gray scale of the leading edge of the wafer is at least 16 units in the industrial gray scale of 255 units. 18. The device according to item 12 of the patent application scope, wherein the recess is circular. 19. The device according to item 12 of the scope of patent application, wherein the recess is oval. 20. The device according to item 12 of the patent application scope, wherein the recess is a horizontal groove. 2 1. The device according to item 12 of the patent application scope, wherein the notch is defined by a rear wall of the notch. 2 2. The device according to item 12 of the scope of patent application, wherein the recess extends along the side wall of the recess and the back wall of the recess to create a shadow, the shadow is masked by the other leading edge of the 200301008 chip, and the recess The shadow generated in the recess of the back wall of the mouth forms an objectively measurable gray scale contrast between the shadow and the wafer. Pick up, schema as the next page 1919
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AU2002346400A1 (en) 2003-06-10
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KR20040062572A (en) 2004-07-07
WO2003046510A9 (en) 2004-03-25
DE10297486T5 (en) 2004-12-02
WO2003046510A2 (en) 2003-06-05
CN1575513A (en) 2005-02-02
TW577163B (en) 2004-02-21
JP2005523424A (en) 2005-08-04
WO2003046510A3 (en) 2003-11-27
AU2002346400A8 (en) 2003-06-10
WO2003046510B1 (en) 2004-04-29
CN1328775C (en) 2007-07-25

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