TH5526B - Serial data link - Google Patents

Abstract

The serial data link is used to circuit additional devices that receive or transmit data over the data bus to the required data bus. Use criteria that allow delivery to additional equipment circuits attached to them.This invention includes a data memory (4), a comparison circuit (5), a control circuit (6), an internal reset / reset circuit (7), and a generator. Internal clock signal (8) where the input The input of the data memory (4) can be connected to the data line (9) of the data memory (3) and the comparison circuit (5) installed at the output part of the data memory (4), the comparison circuit (5). Followed by the control circuit (6), the internal reset / reset circuit input (7) can be connected to the release line (10) and the clock signal cable (11), try the data biss (3) and the output of the reset / reset circuit Internal new (7) connected to the input. Set / reset. Of the data memory (4), the comparison circuit (5) and the control circuit (6). The input of the body Generate internal clock signal (8), can be connected to emitter (10) and data line (11) of bis data (3) and generator output. The internal clock signal (8) is connected to the input clock signal. Of the data memory (4), the comparison circuit (5), and the control circuit (6). Ideal for connecting additional circuits using bis Information that meets the requirements of

Claims (7)

1. Serial data link (1) for connection of known data bus (3) to peripheral circuit (2), here one group of peripheral circuits is connected to a group of interfaces. Coherent data lines and data bus consisting of data lead (9), open lead (10) and clock pulse lead (11), characterized by: - the storage (4) provides Connect to the data lead for Sequential storage of long terms. Of equal or different words transmitted on the data lead / - comparator circuit (5), which detects the address for the cycle Beside that can be contained in words containing information and comparison With the address of the currently connected peripheral circuit, it is connected to the storage-control circuit, which compares the length of the package words. The data with the pre-defined word length and then, is taken to determine the signal transmitted on the open lead, which allows only the further transfer of the data word to the cycle cycle. Connected side, if the length of the two words are the same, then connect to the comparison circuit - Internal clock pulse generator (8), which sends clock pulses to the storage (4), the comparison circuit (5) and the control circuit (6), is connected to the open lead. Way and connected to the clock pulse lead wire. - Internal circuit for setup / reset (7) will keep connected. With an open lead and with a clock pulse lead, whose output will be connected to the input for setting and / or Reset the storage (4), the comparator (5) and the control circuit (6) and leave it to these outputs of the command. Corresponding setup and / or reset tasks. Caused by the signal For external setting or by using the sum of the transmitted signals. Go out on the lead, open the path with on the clock pulse lead. 2. Data link, in accordance with claim 1, characterized by that, storage (4) consists of a scroll register. Which has (25) n storage cells, where the number n corresponds to the number of twists of the word. Contains information that is included with the surrounding traffic (2) 3. The data link, in accordance with claim 2, makes it unique whereby, the storage unit (4) can place the setup / reset circuit (7) in a state which, when viewed From the input, the first storage cell (25) has a logical value of I, and the remaining storage cell (25) is logically 0, or vice versa. 4. The data link, corresponding to claim 2 or No. 3, is characterized by that, where, the last storage cell of the storage (4) when viewed from the input is a circuit component. Compare (5), herein the comparator (5) also contains the logic of collation (27) where the output of the cell storage cell. Finally, on the other side, and the output of the module, which has an address number. Of the surrounding circuit (2) in the opposite way are connected together 5. Linking section which complies with any claim One of the claims 2 to 4, makes it unique where, the control circuit (7) forms a sliding register. Data which contains a group of storage cells (28), here the storage cells (28) are connected to each other by Through the logical grouping elements (29,30,31), the comparator circuit output (5) and the setting circuit output. The new value / value (7) will be connected to the element's input. Logical combination (29, 30, 31) and the LATCH storage transfer signal and the WRITE record / read signal can be received at the output of the control circuit (6). 6.The data link, in accordance with claim 5, makes it unique whereby, the control circuit (6) can be adjusted with the setup / reset circuit (7) to the state which, when Looking from the input The first storage cell (28) has a logical value of I, and the remaining storage cell (28) has a logical value of O or reverses. 7. The data link, corresponding to claim 5 or No. 6, is characterized by that, the output which transports the WRITE record / read signal of the control circuit (6) is connected to the control logic ( 29) of the comparative cycle (5) by means of this method The storage cell (26) of the comparator (5) in the recording mode can be further added to the counter, and the counter output is connected to the counter element. Compose one of the logical elements of the combination (29), which is between the storage cells (28) of the control circuit (6) (7 clauses, 3 pages, 10 fig.).