TH48624A - Phase control for oscillators - Google Patents

Abstract

DC60 (18/05/44) A phase locked loop containing a controllable oscillator (50, 20) that is required. There is a control signal with bi-pressure. Assyr as assigned to generate a clock signal; Integrate (16) for generating such control signals; Origin of External synchronization signal (HOR. SYNC.); Pressure source The first and second (+15 VPC, GND), which determine the voltage potential relative to the bias voltage as specified; The first switch (A) is connected to the aforementioned first and second voltage sources and responds to the signal. The above clock (CTRL A) to generate the generated signal. New arrival, which has the peak-to-peak voltage as determined by the voltage potential; And the second switch (B) which responds to Such an external synchronized signal (CTRL B) to sampling the segments of the clock being re-generated. The components that are sampled are intermittently connected to the integrate, where the sampled parts charge and discharge the integrate. Said to generate control signals Such a large enough Provide a bias voltage as specified above Where the first switch and Such a second (A, B) will cause a phase detector. A phase locked loop containing a controllable oscillator (50, 20) that is required. There is a control signal with bi-pressure. Assyr as assigned to generate a clock signal; Integrate (16) for generating such control signals; Origin of External synchronization signal (HOR, SYNC.); Pressure source The first and second (+15 VPC, GND), which determine the voltage potential relative to the bias voltage as specified; The first switch (A) is connected to the first and second voltage source and responds to the signal. The above clock (CTRL A) to generate the generated signal. New arrival which has the peak-to-peak voltage as determined by the voltage potential; And the second switch (B), which responds to Such an external synchronized signal (CTRL B) to sampling the segments of the clock being re-generated. The components that are sampled are intermittently connected to the integrate, where the sampled parts charge and discharge the integrate. Said to generate control signals Such a large enough Provide the specified bias voltage Where the first switch and Such a second (A, B) will cause a phase detector.

Claims (1)

1. A phase locked loop consisting of a path (50, 20) that is required to have a strong control signal. Push bias as required to Generate clock signal (Hor, OSC OUTPUT); Integrate (16) for generating such control signals; The source of the external synchronization signal (HOR, SYNC.); First (+15 VPC) and second (GND) voltage sources, which determine the voltage potential at Relative to the bias voltage as required; One of the switches (A) that has been connected to the tag source: