KR970004644A - Clock Generator Synchronized to Vertical Sync Signal - Google Patents

Clock Generator Synchronized to Vertical Sync Signal Download PDF

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Publication number
KR970004644A
KR970004644A KR1019950017925A KR19950017925A KR970004644A KR 970004644 A KR970004644 A KR 970004644A KR 1019950017925 A KR1019950017925 A KR 1019950017925A KR 19950017925 A KR19950017925 A KR 19950017925A KR 970004644 A KR970004644 A KR 970004644A
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KR
South Korea
Prior art keywords
vertical sync
phase
clock generator
signal
synchronized
Prior art date
Application number
KR1019950017925A
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Korean (ko)
Inventor
박준석
Original Assignee
배순훈
대우전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 배순훈, 대우전자 주식회사 filed Critical 배순훈
Priority to KR1019950017925A priority Critical patent/KR970004644A/en
Publication of KR970004644A publication Critical patent/KR970004644A/en

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Abstract

본 발명은 수직 동기 신호에 강제 동기된 클럭 발생 장치에 간한 것으로서, 입력된 복합 영상 신호로부터 수직 동기 신호를 분리해내는 동기 분리부(10)와 상기 동기 분리부(10)에서 분리된 수직 동기 신호에 동기된 클럭을 발생시키는 위상 동기 루프(20)로 구성되어 있고, 상기와 같이 구성된 본 발명은 각 수직 동기 신호의 주기마다 정해진 갯수의 클럭이 발생되므로 회로의 오동작을 방지할 수 있다는데 그 이점이 있다.The present invention relates to a clock generator forcibly synchronized with a vertical synchronization signal, and includes a synchronization separator 10 separating a vertical synchronization signal from an input composite video signal and a vertical synchronization signal separated from the synchronization separator 10. It is composed of a phase-locked loop 20 for generating a clock synchronized with the above, and the present invention configured as described above can prevent a malfunction of the circuit because a predetermined number of clocks are generated for each period of the vertical synchronization signal. have.

Description

수직 동기 신호에 동기된 클럭 발생 장치Clock Generator Synchronized to Vertical Sync Signal

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도의 (가)는 수평 귀선 소거 기간을 나타낸 파형도, (나)는 수직 귀선 소거 기간을 나타낸 파형도.1A is a waveform diagram showing a horizontal blanking period, and (B) a waveform diagram showing a vertical blanking period.

Claims (2)

입력된 복합 영상 신호로부터 수직 동기 신호를 분리해 내는 동기 분리부(10)와 상기 동기 분리부(10)에서 분리된 수직 동기 신호에 동기된 클럭을 발생시키는 위상 동기 루프(20)로 구성된 수직 동기 신호에 동기된 클럭 발생 장치.Vertical sync consisting of a sync separator 10 for separating the vertical sync signal from the input composite video signal and a phase sync loop 20 for generating a clock synchronized with the vertical sync signal separated by the sync separator 10. Clock generator synchronized with the signal. 제1항에 있어서, 상기 위상 동기 루프(20)는, 두 입력 신호의 위상 차이에 대응하는 전압을 발생시키는 위상 비교기(22)와; 상기 위상 비교기(22)에서 생기는 고주파 성분을 제거하는 루프 필터(24)와; 상기 루프 필터(24)에서 출력된 제어 전압에 의해서 발진 주파수가 변화하는 전압 제어 발진기(26); 및 상기 전압 제어 발진기(26)의 출력 주파수를 정수 N으로 나눈 후 상기 위상 비교기(22)로 보내주는 N분주기(28)로 구성된 것을 특징으로 하는 수직 동기 신호에 동기된 클럭 발생 장치.2. The apparatus of claim 1, wherein the phase locked loop (20) comprises: a phase comparator (22) for generating a voltage corresponding to a phase difference between two input signals; A loop filter (24) for removing high frequency components generated by the phase comparator (22); A voltage controlled oscillator 26 whose oscillation frequency is changed by a control voltage output from the loop filter 24; And an N divider (28) for dividing the output frequency of the voltage controlled oscillator (26) by an integer N and sending it to the phase comparator (22). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950017925A 1995-06-28 1995-06-28 Clock Generator Synchronized to Vertical Sync Signal KR970004644A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950017925A KR970004644A (en) 1995-06-28 1995-06-28 Clock Generator Synchronized to Vertical Sync Signal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950017925A KR970004644A (en) 1995-06-28 1995-06-28 Clock Generator Synchronized to Vertical Sync Signal

Publications (1)

Publication Number Publication Date
KR970004644A true KR970004644A (en) 1997-01-29

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950017925A KR970004644A (en) 1995-06-28 1995-06-28 Clock Generator Synchronized to Vertical Sync Signal

Country Status (1)

Country Link
KR (1) KR970004644A (en)

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