NO953288D0 - Method of synchronizing the output frequencies of a clock generator - Google Patents

Method of synchronizing the output frequencies of a clock generator

Info

Publication number
NO953288D0
NO953288D0 NO953288A NO953288A NO953288D0 NO 953288 D0 NO953288 D0 NO 953288D0 NO 953288 A NO953288 A NO 953288A NO 953288 A NO953288 A NO 953288A NO 953288 D0 NO953288 D0 NO 953288D0
Authority
NO
Norway
Prior art keywords
frequency
output
synchronizing
dpll
clock generator
Prior art date
Application number
NO953288A
Other languages
Norwegian (no)
Other versions
NO953288L (en
Inventor
Jochen Egbers
Rainer Goerge
Karl-Eckardt Huhn
Nikolaus Riehm
Original Assignee
Deutsche Telephonwerk Kabel
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Deutsche Telephonwerk Kabel filed Critical Deutsche Telephonwerk Kabel
Publication of NO953288D0 publication Critical patent/NO953288D0/en
Publication of NO953288L publication Critical patent/NO953288L/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

The method involves using a relatively inaccurate working frequency generator (FWORK) whose output is converted by frequency synthesiser (FSYN) to a more accurate frequency. An external reference signal (FE) is input to an operational frequency estimation circuit (FB) which frequency-normalises the signal before outputting it to a digital phase locked loop (DPLL). The DPLL output frequency (SIP) is synchronised with (FNOR), and is fed to an analogue phase locked loop (APLL), whose output is divided by a frequency divider (FT) which is included in its feedback loop to provide the final output (FA).
NO953288A 1994-08-24 1995-08-22 Method of synchronizing the output frequencies of a clock generator NO953288L (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE4431415A DE4431415C2 (en) 1994-08-24 1994-08-24 Method for synchronizing the output frequencies of a clock generator

Publications (2)

Publication Number Publication Date
NO953288D0 true NO953288D0 (en) 1995-08-22
NO953288L NO953288L (en) 1996-02-26

Family

ID=6527342

Family Applications (1)

Application Number Title Priority Date Filing Date
NO953288A NO953288L (en) 1994-08-24 1995-08-22 Method of synchronizing the output frequencies of a clock generator

Country Status (7)

Country Link
EP (1) EP0698968B1 (en)
AT (1) ATE192612T1 (en)
CZ (1) CZ286319B6 (en)
DE (2) DE4431415C2 (en)
FI (1) FI953991A (en)
NO (1) NO953288L (en)
SK (1) SK281836B6 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5960331A (en) * 1996-07-01 1999-09-28 Harris Corporation Device and method for maintaining synchronization and frequency stability in a wireless telecommunication system
DE19722114C2 (en) * 1997-05-27 2003-04-30 Bosch Gmbh Robert Clock signal providing device and method
DE60331698D1 (en) 2003-04-02 2010-04-22 Christopher Julian Travis A numerically controlled oscillator and method for generating an event clock

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4131861A (en) * 1977-12-30 1978-12-26 International Business Machines Corporation Variable frequency oscillator system including two matched oscillators controlled by a phase locked loop
DE2938228C2 (en) * 1979-09-21 1982-02-25 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Method and circuit for synchronization
US4598257A (en) * 1983-05-31 1986-07-01 Siemens Corporate Research & Support, Inc. Clock pulse signal generator system
US4672299A (en) * 1986-05-23 1987-06-09 American Telephone And Telegraph Co. Clock control circuit for phase control
US4953185A (en) * 1988-10-05 1990-08-28 Motorola Inc. Clock recovery and hold circuit for digital TDM mobile radio
DE4001065A1 (en) * 1989-01-23 1990-08-02 Siemens Ag Redundant block encoded serial data signal synchroniser - stores alternate bits in antiphase clocked shift registers to assemble new codeword bitwise in parallel register
DE4018911A1 (en) * 1990-06-13 1992-01-02 Ant Nachrichtentech Frame synchronisation procedure for phase keying and AM - recognising symbol position of sub-alphabet in symbol train by selection of signal alphabet lower quantities
US5184350A (en) * 1991-04-17 1993-02-02 Raytheon Company Telephone communication system having an enhanced timing circuit
US5144254A (en) * 1991-09-30 1992-09-01 Wilke William G Dual synthesizer including programmable counters which are controlled by means of calculated input controls
US5353311A (en) * 1992-01-09 1994-10-04 Nec Corporation Radio transmitter
DE4218132C2 (en) * 1992-06-02 1994-05-19 Ant Nachrichtentech Process for clock recovery and synchronization

Also Published As

Publication number Publication date
FI953991A0 (en) 1995-08-24
EP0698968B1 (en) 2000-05-03
DE59508248D1 (en) 2000-06-08
DE4431415A1 (en) 1996-02-29
ATE192612T1 (en) 2000-05-15
FI953991A (en) 1996-02-25
NO953288L (en) 1996-02-26
CZ286319B6 (en) 2000-03-15
EP0698968A1 (en) 1996-02-28
CZ215895A3 (en) 1996-04-17
SK281836B6 (en) 2001-08-06
DE4431415C2 (en) 1997-01-23
SK103495A3 (en) 1996-05-08

Similar Documents

Publication Publication Date Title
EP0193273A3 (en) Improvements in or relating to synthesisers
KR920704411A (en) Voltage controlled oscillator circuit and phase locked circuit
SE9504165D0 (en) Frequency standard generator
KR960012737A (en) Phase Locked Circuit (PLL) System Clock Generators that Instantly Shift Clock Frequency
ATE308159T1 (en) DIRECT DIGITAL FREQUENCY SYNTHESIS THAT ALLOWS INTERFERENCE ELIMINATION
KR890005990A (en) Sample rate conversion system
SE8603552D0 (en) MICROWAVE NOISE MEASURING APPARATUS
SE8804461L (en) CIRCUIT FOR MAINTAINING A CLOCK SIGNAL
WO2005002055A3 (en) Fractional-n synthesizer and method of programming the output phase
KR910007267A (en) How to generate two reference signals of the same frequency as the time base generator circuit
GB1545922A (en) Method for controlling frequency of electrical oscillations and frequency standard for electronic timepiece
GB1447418A (en) Frequency synthesiser
NO953288D0 (en) Method of synchronizing the output frequencies of a clock generator
CA2192881A1 (en) PLL Circuit and Noise Reduction Means for PLL Circuit
WO2002009290A3 (en) Analog phase locked loop holdover
SE9600726L (en) Digital phase locked loop
JPS5550191A (en) Electronic timepiece
ES8306299A1 (en) Frequency converter and phase locked loop circuit
JPS6412691A (en) Video signal sampling circuit
JPS6413833A (en) Frame synchronizing clock generating circuit
JPS54148410A (en) Timing extracting pll circuit
KR19980080410A (en) Digital Clock Synthesizer
ATE388523T1 (en) METHOD AND DEVICE FOR GENERATING A VARIABLE FREQUENCY VIBRATION
KR960006299A (en) Phase locked loop device
JPS5620355A (en) Clock signal forming circuit

Legal Events

Date Code Title Description
FC2A Withdrawal, rejection or dismissal of laid open patent application