SK103495A3 - Synchronizing method of clock generator output frequencies, devices with external input frequencies - Google Patents

Abstract

Frequency generator (FGEN) produces relatively inaccurate working frequency (FWORK) into the frequency synthetiser (FSYN), into the frequency estimation circuit (FB) and into digital phase locked loop (DPLL), that frequency synthetiser (FSYN) together with digital phase locked loop (DPLL) and control microprocessor evaluates working frequency (FWORK) comparing accurate external input frequencies (FE), while external input frequency (FE) is transformed to standard frequency (FNOR) and signal frequency (SIP) sent by digital phase locked loop (DPLL) is regulated synchronously with standard frequency (FNOR), and that frequency divider (FT) creates internal output frequencies (FA) of the system, while preliminary analogue phase locked loop (APLL) realises corrections of the signal frequency (SIP) which are used to prevent time jumps of the output frequencies (FA). Device contains frequency synthetiser (FSYN), frequency estimation circuit (FB), digital phase locked loop (DPLL) and frequency divider (FT) integrated into the circuit of clock generator (TG-ASIC). the final output (FA).

Description

A method for synchronizing the output frequencies of a clock generator of an apparatus with external input frequencies

Technical field

The invention relates to a method of synchronizing the output frequencies of a clock generator of a device with high precision external input frequencies.

BACKGROUND OF THE INVENTION

In digital communication networks, network synchronization is performed in a master and slave manner (master glory). The clock generator controls all intermediate workstations directly or via intermediate stages. These referral sites are also responsible for synchronizing connected branch networks and PBXs. That is, the network, e.g. The clock pulses transmitted by the ISDN network are connected synchronously to the necessary clock pulses with the connected telecommunication switchboard. If rapid oscillations occur, the phase shifts of the devices of the slow oscillations of the input signals then decrease to a corresponding extent.

SUMMARY OF THE INVENTION

SUMMARY OF THE INVENTION It is an object of the present invention to provide a method for synchronizing / input frequencies, phase shifting and power failures corresponding to a range to design an output which would reduce phase jitter for extreme clock frequencies and provide transmitted clock pulses. extensive integration of these components.

This task is solved by a combination of characters:

The relatively inaccurate operating frequency serves as the base frequency for the clock generator, which is converted by the frequency synthesizer to the exact frequency.

The external input frequencies are converted to a standard frequency using an adjustable evaluation circuit.

The phase frequency signal transmitted by the phase control circuit is controlled to be synchronous to the normalized frequency and the frequency divider produces system internal output frequencies, the upstream analogue control circuit correcting the signal frequencies to avoid time jumps of the output frequencies.

Advantages of such a clock generator are the use of a non-expensive quartz oscillator with low accuracy requirements, low space requirements due to the possibility of integrating large parts of the circuit into one component and utilizing the existing microprocessor of the device, which is only slightly loaded. In addition, a suitable external switching circuit can enable feedback for the self-frequency traveling evaluation.

Further advantageous measures are the subject of the subclaims.

Drawing overview · /

The invention will be explained in more detail below with reference to the three figures shown in the drawings.

Fig. 1 shows a block diagram of a clock generator.

Fig. 2 shows an example of integrating parts of a clock generator.

Fig. 3 shows a diagram of the events of the clock generator.

DETAILED DESCRIPTION OF THE INVENTION

The clock generator of FIG. 1 of a frequency generator FGEN, a frequency evaluation circuit FB, a digital control circuit DPLL phase, an analog control circuit APLL phase, a frequency divider FT. The clock generator generates multiple output frequencies FA with reduced vibration and high precision synchronization with the input frequency FE.

The setting of the clock generator is controlled by, for example, an existing microprocessor in the telecommunications switchboard from which FIG. 1 to 3, only the reporting inputs or the reporting outputs are indicated.

The FGEN frequency generator serves FWORK frequencies with relatively inaccurate operating frequency generation, e.g.

typical 32 MHz +/- 100 ppm. This FWORK operating frequency is the basic frequency for the entire clock generator connection. It is fed to frequency evaluation circuit FB, frequency synthesizer FSYN and digital control circuit DPLL of phase. For the use of cost-effective silicon oscillators, only temperature conditions need to be considered.

their short-term aging

The FSYN frequency synthesizer is connected to the digital control circuit of the DPLL phase and the control microprocessor to the digital control

Frequency synthesizer FSYN working frequency FWORK circuit DPLL phase.

e.g. telecommunication switchboard, ensures from. in terms of accuracy correction values for

The correction value information is e.g. by the microprocessor of the telecommunications exchange is memorized as an initial value for the FSYN frequency synthesizer.

If the input frequency FE fails, or if initiates eg. The last stored value is fed to the FSYN synthesizer via a microprocessor. This procedure ensures that the previously achieved accuracy of the output frequency FA is maintained by the clock generator without frequency and phase jumps.

The adjustable frequency FE in the FB recovery circuit examines each new connection of others or observes the frequency limitation beyond e.g. 2 ms and normalizes for the next FE frequency to the normal frequency kHz. The introduction of the standardized frequency FNOR is independent of the input

input frequency stepping ch pulse a certain period of time e entry FIFG, e.g. . 8 kHz. clock generator frequency i i FE, e.g. 2.04S MHz.

For the clock generator, valid input frequency bands FE are predetermined by the microprocessor e.g. a telecommunications exchange and programmed by the FB Frequency Recovery® circuit.

The digital control circuit of the DPLL phase regulates its own so that it is always. This reduces the phase signal frequency by the transmitted signal frequency FNOR · / synchronous with the normalized frequency FNOR. input frequency oscillation FE. Change

The SIP of the digital control circuit DPLL is achieved by introducing or deleting the output bit stream pulses. For this purpose, the FSYN synthesizer information and the DPLL digital control circuit information are collected and used to control the bit stream. The filtering properties and filter bandwidth of the digital control circuit of the DPLL phase are programmable by a microprocessor, e.g. telecommunication switchboard i.

The APLL phase analog control circuit is used to prevent time jumps of the output frequencies FA by correcting the SIP signal frequency of the DPLL phase digital control circuit. Turning on the clock generator after resetting is the task of the APLL phase analog control circuit for the output frequency FA, unless the DPLL phase digital control circuit is still operational.

The frequency divider FT converts the high VCO frequency of the APLL analog phase control circuit to the desired internal output frequencies of the FA system, e.g. at CLKA1 = 2.048 MHz and CLKA2 = 8.192 MHz.

As can be seen in FIG. 2, the frequency recovery circuit FB, the digital control circuit DPLL, the frequency synthesizer FSYN and the frequency divider FT can be integrated into the TG-ASC clock generator circuit in an economical manner.

As mentioned above, a high frequency silicon oscillator with low accuracy serves as the FGEN frequency generator.

A cost-effective standard switching circuit is used as the APLL analog phase control circuit.

/

The TG-ASIC clock generator, the FGEN frequency generator, and the APLL analog control circuit may also be integrated into a customer-specified design element.

In FIG. 3 is a diagram showing the progress of the clock

Also, the information of the generator in the form of a flow chart 2 shows its function. Upon its return to the initial position, the filtering properties and bandwidths are reported to the MPLL phase control circuit MP.

are reported to the FSYN frequency synthesizer of the last achieved output frequency or initial value at first connection. The microprocessors MP are then notified to the frequency evaluation circuit FB of the valid frequency bands for the incoming input frequencies FE. After start-up by the microprocessor MP, regulation is performed as shown in FIG. 3. The evaluation of the shift of the input frequency FE by taking into account the external switching circuit feedback and reducing the oscillation is also taken into account.

Once the synchronized state is reached, the control band limits are checked by the clock generator. The input frequency drop FE is recognized by the clock generator. If the clock generator is synchronous, the current set values are detected by the microprocessor MP, used as a new start value for the FSYN frequency synthesizer by a new start or power failure FE.

regularly

Claims (7)

PATENT CLAIMS frequency i output i A method of synchronizing a device clock output generator with external high-frequency frequencies, characterized in that the relatively inaccurate operating frequency (FWORK) serves as the base frequency for the frequency synthesizer frequency, an external input clock generator that (FSYN) is converted to the exact frequencies ( FE) are converted by the frequency adjustment circuit (FB) to the standard frequency (NOR) by the digital phase control circuit (DPLL), the transmitted signal frequency (SIP) is regulated synchronously with the standard frequency (FNOR), and the frequency divider (FT) Frequency (FA) of the system, while the analog phase control (APLL) of the phase generates signal frequency corrections (SIPs) to prevent time jumps of the output frequencies (FA). Method according to claim 1, characterized in that any, e.g. in the telecommunication exchange existing moprocessor. Method according to claim 1 and 2, characterized in that in the event of an input frequency failure (FE), the clock generator maintains the previously obtained output frequency accuracy (FA) without phase jumps by means of the last frequency synthesizer (FSYN). frequency / / denote Method according to claims 1 and 2, characterized in that the operating frequency (FWORK) is generated by a silicon oscillator of low precision frequency generator (FGEN). Method according to claim 1 and 2, characterized in that when the operating frequency (FWORK) is converted to a precise frequency, the correction values detected by the frequency synthesizer (FSYN) are stored in the microprocessor used. Method according to claims 1 and 2, characterized in that the frequency evaluation circuit (FB), when the clock generator is switched on again, examines the input frequency (FE) for a certain period of time to observe predetermined frequency limits. Method according to claims 1 and 2, characterized in that the frequency synthesizer (FSYN) and digital control information are combined to synchronize the signal frequency (SIP) with the standard frequency (FNOR). circuit (DPLL) phases and used for control. 8th equipment for carrying out the method according to claims 1 to 7 v y 2 n and no taking into account that frequency the synthesizer (FSYN), the frequency recovery circuit (FB), the digital phase control circuit (DPLL), and the frequency divider (FT) are integrated in the clock generator circuit (TG-ASIC). · / List of reference numbers used FVORK FSYN FE FB FIFG DPLL SIP FT FA APLL FGEN TG-ASIC MP working frequency frequency synthesizer input frequency frequency evaluation circuit standard frequency digital control circuit phase signal frequency frequency divider output frequency analog control circuit frequency generator circuit clock generator n i croprocessor