TH4674EX - Frequency stabilization circuit in digital phase locked loop system. - Google Patents

Abstract

Digital TV receivers consist of a phase lock loop, part one that provides a sampling clock signal which locks on the sync signal portion of the horizontal scan line of the video signal. The second digital loop-locked phase is fed to a clock signal with a sampling clock signal and produces a digital signal with a phase. Is sampling, which will lock the sync signal portion of the The horizontal scan line of the digital phase-locked loop video signal, the second part is fed to a clock signal with a sum-of-the-clock signal, and a digital signal with phase-locked to a color-burn signal. This psychol is used as a reconstituted transducer signal to sync (heat to each other), chemotherapy, the chrominance portion of the video signal in the contrast signal. I and (chemical letter) to compensate for the frequency changes of the newly generated sub-carrier signal caused by the replacement Converts the frequency of the locked clock signal to the digital scan line, the third locked-loop phase provides a phase-locked output signal with the phase of the reference signal obtained from a crystal-controlled oscillator. The control signal from the third locked-loop phase is fed to the second segment locked-loop phase to firmly compensate for the frequency change of the newly-generated samcarrier signal. The frequency is induced by the clock signal.

Claims (1)

1. A circuit that includes the source of a clock signal, a frequency that changes with a fixed clock frequency, and the first digital silencer that responds to such a clock signal and responds to a frequency controlled signal. The first part is to obtain an output signal with a predetermined frequency that such a change in clock frequency will cause a change in the frequency of that output signal at Asynchronous, circuit for eliminating the change The frequency of the said output signal consists of a section for