SU995320A1 - Code-to-time interval converter - Google Patents

Description

The invention relates to automation and computing and can be used in automated control systems for converting digital information of a VM into a time interval, as well as as a self-designed device, a precision pulse delay is formed.

A known code converter so is a time interval using the following method of converting and containing a pulse generator, a range switch, an OR element, a gating element, two valves, two triggers, a comparison element, a decoder, a pulse counter l J.

The disadvantages of this device are low operational efficiency of the converter due to the necessity of switching the tapes of the delay lines with each change of the value of the converted code, the complexity of setting the generator due to the need for precise adjustment of each feedback circuit specifying a certain range of generated pulses, starting from the minimum discrete conversion step, limited conversion range due to the cxeNH feature

A transducer that does not allow code conversion for a number in which the code of the minor bits written to the comparison element is greater than the number determined by the code of the higher bits of the pulse counter. .

Also known converter code in the time interval, contains -.

10 a generator of pulses, the first outputs of which are respectively connected to the inputs of a range switch, outputs respectively connected with the first inputs of the first and second element OV I, outputs

15 of which through the OR element are connected to the second input of the pulse generator, the second output connected to: the counting input of the pulse counter, the setup inputs of which are connected to the high-order code bus, the ELECTRONIC higher-order bits to the inputs of the third element and the lower ones to the first inputs of the element compare, second inputs

25 code connected to the low-order bus, and the output is to the second input of the quad-. of the right element And, four triggers, the first inputs of the first and second triggers and the second inputs of the third and

30 quarter-triggers of the triggers are connected to the Start bus, the second input of the first trigger is connected to the output bus, its output is connected to the first input of the pulse generator, and the outputs of the second one to the second inputs of the first and second elements AND, respectively, the first and third inputs of the AND-OR element connected to the first outputs of the third and fourth triggers, the second outputs of which are respectively connected to the first inputs of the fourth and fifth elements AND, the outputs respectively associated with the first inputs of the fourth and third triggers and the first and second inputs The second OR element whose output is connected to the second input of the second trigger, the second, the fourth input of the AND element is connected to the second input of the AND-OR b element, the output of which is connected to the output bus and through the second delay element to the second input of the fifth trigger, and the fourth input - with the second input of the fifth element I and the output of the comparison element, the second input of which is connected to the second output of the pulse generator through the first delay element, and the third input to the output of the fifth trigger, the first input connected to the third output For IV element of the code conversion during the interval in hydrochloric known devices used for main and additional conversion frequencies which are set range of the converter is carried yuschem switching hydrochloric defined pairs of taps of delay line chain feedback generator G2. A disadvantage of the known device is the low speed, due to the fact that the user needs to analyze the code being converted before each conversion of the code into the time interval and depending on its value, by switching off taps of the delay lines in the generator feedback circuit, set the main and additional conversion frequency, which requires a considerable amount of time. In addition, it is difficult to tune the device during manufacturing due to the need to fine-tune each generator feedback circuit due to the spread of parameters of the elements used, specifying a certain range of generated pulses, based on the minimum discrete conversion step. The purpose of the invention is to increase the conversion speed. The goal is achieved by the fact that in a code converter in a time interval containing a pulse generator, the input of which is connected to the output of the first trigger, the first input of which is connected to the Start bus and the first inputs of the second and third triggers is connected to the output of the first element And, the first 1 INPUT of which is connected to the reverse output of the third trigger, and the second input to the first input of the AND-OR element and the output of the pulse counter, the setup inputs of which are connected to the high-order bus code , the high-order outputs to the corresponding inputs of the second element I, the output of which is connected to the first input of the fourth trigger, and the outputs of the lower bits to the corresponding first inputs of the comparison element, the second inputs of which are connected to the low-level bus of the code, the third input to the output of the fourth trigger, the fourth input through the first delay element to the counting input of the pulse counter, and the output to the second input of the AND-OR element and the first one. The third element I, the second input of which is connected to the reverse output of the second trigger, the direct output of which is connected to the third input of the element J-OR, the fourth input of which is connected to the direct output of the third trigger, and the output to the output bus and the second input of the first trigger, the second delay element and the fifth trigger, the second pulse counter, the decoder, the second AND-OR element and the pulse distributor are entered, the output of the pulse generator is connected to the first input of the pulse distributor, the outputs of which are connected to the first a group of inputs of the second AND-OR element, the second group of inputs of which is connected to the corresponding outputs of the decoder, the first input of which is connected to the output of the fifth trigger, and the second inputs to the corresponding outputs of the second pulse counter, the installation inputs of which are connected to the control code bus, the output of the second AND-OR element is connected to the counting input of the first pulse counter and through the second delay element to the second input of the pulse distributor and the first input of the fifth trigger, the second input of which is connected the first input of the second flip-flop, a direct output of which godklyuchen to the first count input of the second pulse counter, a second counter input coupled to an output of the comparison element, and the second input of the fourth flip-flop coupled to bus Start. The drawing shows a block diagram of the converter code in the time interval.

The code converter contains a stable frequency power generator 1, trigger 2, pulse distributor 3, delay 4 element, AND-OR element 5, decryptor b, counters 7, and 8 pulses, element 9, trigger 10, comparison element 11, trigger 12, elements And 13 and 14, triggers 15 and 16, the AND-OR 17 element, aadrji element 18, tires 19-23.

The output of the stable frequency generator 1 is connected to the first input of the distributor 3 pulses, the outputs associated with the first, a group of inputs of the AND-OR element 5. The outputs of the decoder b are connected to the second group of inputs of the AND-OR element 5, the output of which is connected to the counting input of the counter 8 pulses and through the delay element 18 with the first input of the comparison element 11. The output of the element AND-OR 5 through the element 4 of the delay is also connected with the first input of the trigger 12. And the second input of the distributor 3..

The input of the pulse counter 8 across the bus 20 receives the reverse code of the high-order bits, and via the bus 23 to the second inputs of the reference element, the forward code of the lower bits. The outputs of the higher bits of the counter 8 pulses are connected through the element 9 to the first input of the trigger 10, the outputs connected to the third input of the comparison element 11, the fourth inputs of which are connected to the output of the lower bits of the counter 8 pulses.

The output of the comparison element 11 is connected to the third input of the AND-OR element 17, to the first inputs of the AND 13 element and the counter 7, to the second inputs of which, via the bus 22, the control code arrives. The output of the counter 8 is connected to the first inputs of the AND-OR element 17 and the AND 14 element, the second input connected to the reverse output of the trigger 15, and the output to the first input of the trigger 16, the reverse output of which is connected to the second input of the AND element 13, output connected to the first input of the trigger 15. The direct output of the trigger 15 is connected to the second input of the element AND-OR 17, the fourth input connected to the direct output of the trigger 16 and the third input of the counter 7, the outputs connected to the decoder 6. The output of the element AND-OR 17 zana with output bus 19 and the second input t rigger 2. The forward output of trigger 12 is connected to the first input of the decoder. b. At the first input of the trigger 2 and the second inputs of the trigger 10,12,15 and 16 on the input bus 21 receives a start pulse.

The device works as follows.

Before starting the converter, the inverse code of the higher bits

m on bus 20 is written to the pulse counter 8, the direct code of the lower bits k on bus 23 to the reference element 11, the control binary code N to the pulse counter 7.

Triggers 2 and 12 are set to zero. The distributor of 3 pulses is in the initial state and at its outputs (channels)

- there are no signings. The number of channels of the pulse distributor is equal to the maximum value of the control code N. Each channel of the distributor of 3 pulses at the input of the AND-OR element 5 corresponds to a resolution level coming from a certain output of the decoder 6 i.e. for the first channel of the distributor of 3 pulses, the resolving level comes from the first output of the decoder corresponding to the binary code ... 000, for the second channel - c. the second output of the decoder corresponding to the code ... 001, etc.

The binary code N of the counter 7 is fed to the input of the decoder b. The start of the conversion is determined by the start pulse (FROM) coming through the bus 21. The FR pulse sets the trigger state 2 to one, and the trigger l 10,12,15 and 16 sets it to the zero state. A high level from the forward output of the trigger 2 is fed to the generator 1 stable frequency. The appearance of the first pulse of the generator 1 is rigidly connected with the leading edge of the voltage level of the trigger 2. The pulse l from the output of the stable frequency generator is fed to the input of the distributor

3 pulses. In this case, if the period of the pulse generator is t, then at the output of the distributor 3 pulses its value corresponds to t for the first channel, 2t for

the third, 3t for the third, etc.

Since the low level of trigger 12 is applied to the control input of the decoder, the AND-OR 5 element receives a signal from the first output of the decoder, corresponding to the code. ... 000 Therefore, at the output of the AND-OR element 5, regardless of the value of the control code N, the first pulse corresponds to the first generator pulse i. The output pulse of the AND-OR element 5 sets the distributor 3 pulses to the initial state and the trigger 12 to the one state. The delay time of the element 4 does not exceed the duration of the generator pulses. By the high level of the trigger 12. The control code N is decrypted with a decryptor 6 from the binary code into the decimal.

A pulse from the (N + 1) -th output of the decoder, corresponding to code N, is delivered to the input of element 5 to allow the passage of a pulse N of channel of distributor 3. The output pulse of element 5 with a period of Nt through delay element 4 sets the distributor 3 pulses to the original condition. Thus, at the output of the AND-5 element, pulses are generated with a conversion frequency set by the control code N.

The pulses from the output of the AND-OR element also arrive at the counting input of the counter 8 pulses and through the delay element 18 to the comparison element 11. .

The operation of the converter circuit depends on the value of the code being converted (m and k).

If the number determined by the code of the higher bits is greater than the number determined by the code of the kshadai bits of k (), then counter 8 counts the pulses received at the frequency Nt from the IL-5 element. When in the lower bits of the counter 8 a number will be set equal to the number determined by the code of the least significant bits written in the comparison element 11, and in the rest of the bits -. If counter 8 is set to one unit, which is detected by trigger 10 through AND 9, then a pulse is generated at the input of the comparison element 11, arriving at the third input of the AND-OR element 17, the first input of the AND element 13 and the first counting input of the counter 7. Since the second input of the element And 13 is fed a high level corresponding to the zero state of the trigger 16, then the output impulse of the comparison element 11 through the element And 13 switches the trigger G5 to a single state. At the same time, in the counter 7, Working on subtracting the output element of the comparison element, the unit is subtracted from the previously recorded control code-N. In the decoder, the N-1 code is decrypted into the nythic and arrives at the input of the element I-ILC 5 to disperse the passage of pulses from the (Nl) -ro channel of the distributor 3. Thus, the output of the element AND-OR 5 prohibits the formation of pulses with frequency Nt pulse generation with a frequency (N-1) t is allowed,

In the pulse counter 8, the pulse counting continues at the (N-l) -t frequency. An overflow pulse is generated on the overflow in the counter 8, arriving at the first input of the AND-OR element 17, to the second input of which a high level of the single state of the trigger 15 is applied. The output pulse determines the end of the converter time interval. According to this impulse

installation in

trigger 2, thereby preventing the operation of generator 1.

The time interval for a given case corresponding to a given conversion code is defined by the following expression:

() -N t + (N-k). (N-l) t,

where t is the period of the main frequency

following generator pulses; m - the number defined by the code

most significant bits (, 1,2, .. k is a number determined by the code

most significant bits (, l, 2, t. (n-1);

. N is the number given by the N code, defining the base conversion frequency.

Consider code conversion, when the number determined by the code of the least significant bits is less than the number determined by the code of the least significant bits (). The output pulse from the AND-OR 5 element with the frequency specified by the control code N, enters the count of 8 pulses and through the delay element 18 to the comparison element 11. The delay time in the delay element 18 must not be less than the switching time of the counter 8 pulses. The presence of all units in the old bits is detected through the element AND 9 by the trigger 10, the overflow pulse of the counter 8 is switched to the single state of the trigger 1 via the element 14. The high level from the direct output of the trigger 16 enters the second input of the counter 7 impulses and resets to the zero state of the previously recorded control code N. The output pulse from the first output of the decoder b, corresponding to the code ... 000, goes to the AND-OR 5 element to enable the passage of the pulses of the first channel of the distributor 3 sec oi t.

Impulses with the element AND-OR 5 at the frequency t arrives at the counting input of the counter 8, When the number determined by the low-order code written in the reference element 11 is equal to the number determined by the low-order code of the low bits of the counter 8, and at the output of the trigger 10 there is a high level , then a comparison pulse is generated at the output of the comparison element 11. This pulse arrives at the third input of the AND-OR element 17, the output of which is the end of the time conversion of a given code. This signal sets the trigger state to zero.

The time interval in this case is determined by the expression

0 m.N "t + kt, where m is a number determined by the code

senior raar: dov; k is the number determined by the code of the younger bits; t is the frequency of the generator; N is the number given by the code N,

defining the basic frequency of transformation. The proposed converter is characterized by the ability to quickly change the frequency of operation, which makes it possible to increase the speed by reducing the conversion time of preparation for conversion of a given code.

Claims (2)

Invention Formula The Converter code in the time interval, containing, a pulse generator, the input of which is connected to the output of the first trigger, the first input of which is connected to the Start bus and the first inputs of the second and third trigger, the second input of the second trigger is connected to the output of the first element And, the first input of which is connected with the reverse output of the third trigger and the second input with the first input of the element and the output of the counter-pulses, the installation inputs of which are connected to the bus of the higher bits of the code, the outputs of the old bit of discharge - to the corresponding the moves of the second element I, the output of which is connected to the first input of the fourth trigger, and the output of the lower bits, to the first inputs of the comparison element, the second inputs of which are connected to the lower code bus, the third input to the output of the fourth trigger, the fourth input through the first the delay element to the counting input of the pulse counter, and the output - to the second input of the element is AND-OR and the first input of the third element AND, the second input of which is connected to the reverse output of the second trigger, the direct output of which is connected to the third input of the element AND-YLI, the fourth and right input of which is connected to the direct output of the third trigger and the output is to the output bus and the second input of the first trigger, the second delay element and the fifth trigger, characterized in that, in order to improve performance, a second pulse counter is entered into it, the decoder, the second element 5 AND-OR and pulse distributor, while the output of the pulse generator is connected to the first input of the pulse distributor, the outputs of which are connected to the first group of inputs 0 of the second element AND-OR, the second group of inputs of which are connected to the corresponding outputs of the decoder, the first input of which is connected to the output of the fifth trigger, and the second 5 inputs - to the corresponding outputs of the second pulse counter, the installation inputs of which are connected to the control code bus, and the output of the second AND-OR element is connected 0 with the counting input of the first pulse counter and through the second delay element with the second input of the pulse distributor and the first input of the fifth trigger, the second input of which is connected to the first input of the second trigger, the forward output of which is connected to the first counting input of the second pulse counter, the second counting the input of which is connected to the output of the reference element, and the second input of the fourth trigger is connected to the Start bus. Sources of information taken into account during the examination 1. USSR Author's Certificate No. 547969, cl. H 03 K 13/20, 1976. 2. USSR author's certificate in application 3251294 / 18-21, cl. H 03 K 13/20, 1981 (prototype). J