SU995311A1 - Multichannel digital-analogue converter - Google Patents

Description

The invention relates to computing, in particular to code-voltage converters, and can be used in systems for outputting information from digital computers.

A multi-channel digital-to-analog converter (DAC) is known, which contains a code-common voltage converter for all channels, the output of which is connected to the inputs of analog storage elements made on integrators £ 1 through a comparison circuit and keys].

The disadvantage of this device is the low speed.

Also known is a multichannel digital-to-analog converter containing a digital memory unit, a control unit, first keys, analog memory units and a single-channel code-voltage converter, the inputs of which are connected to the input code buses through the digital memory unit, and the outputs are connected to the inputs of the analog memory blocks through the first keys / the control unit input is connected to the channel number code bus, the outputs of the control unit are connected to the control inputs of the first keys and the digital memory unit (2).

The disadvantage of this device is the long time it takes to record analog information into an analog storage element on integrators and the inability to quickly change analog information in any channel of the converter, both due to the fundamentally low speed of analog storage elements on integrators and because the channels are served by the converter. _ code - voltage alternately and. For ’® to record new information, it is necessary to wait for the moment when the queue is suitable for servicing this channel. Changing the order of service of 2Q channels does not solve the problem, since it is possible that in some channels the next information recovery (regeneration) will be skipped several times in a row, which can lead to the output of signals beyond the reliable values due to the natural drift of the output voltage of the integrators.

_ The purpose of the invention is to increase the speed of the device.

This goal is achieved 'by the fact that in a multi-channel digital-to-analog converter containing a digital memory unit, a control unit, first keys, analog memory units and a single-channel converter 5 code is the voltage whose inputs are ₍ through the digital memory unit connected' to the input code buses, and the outputs through the first keys are connected to the inputs of the analog memory blocks, the input of the control unit 1 is connected to the channel number code bus, the outputs of the control unit are connected to the control inputs of the first keys and the digital memory block, we have the second keys and the second single-channel | code-voltage converter (PCN), the inputs of which are connected to the buses of the input Code and the corresponding inputs of the digital memory block, the output of the second single-channel code-voltage converter is connected through the second keys to the corresponding inputs of the analog memory blocks and outputs first keys.

The drawing shows a functional diagram of the device.

The channel number code bus is connected to the input of the control unit 1, and the input code buses through the digital memory unit 2 are connected to the input of the first single-channel PCN 3, the outputs of which are connected through the first keys 4 to the inputs of the analog memory units 5. The input code buses are also connected to the input of the second PKN 6, the output of which is connected via the second keys 7 to the inputs of the analog memory blocks 5. The outputs of the control unit 1 are connected to the control inputs of the digital block 2, the first 4 and second 7 keys.

Each conversion channel of the multi-channel DAC in block 2 of the digital memory is allocated one storage cell in which the current conversion code is stored.

The device operates as follows.

The control unit 1, in turn, reads the codes from the cells of the digital memory unit 2 to the inputs of the first PCN 3, while simultaneously opening the key 4 of the corresponding channel. In this mode, cyclic regeneration of analog information in blocks 5 of the analog memory is provided, and the regeneration period is chosen so as to guarantee the reliability of the analog information at the outputs of blocks 5 of the analog memory. Upon receipt of a new code for recording in the channel, but 60 of which is fed to the individual inputs of the control unit 1, the latter opens the analog key 7 in accordance with the specified channel number, thereby providing an immediate 65-second record of the new signal value through the second control panel 6 in corresponding block 5 of the analog memory. At the same time, the control unit 1 writes a new conversion code to the cell of the digital memory unit 2 allocated for this channel. Thus, the regeneration process is not slowed down, and the new code value is immediately converted to an analog signal at the output of the corresponding channel.

In the case when the recording of a new signal value and the regeneration of analog information should be carried out on the same channel, the regeneration process on this channel is blocked and the control unit 1 immediately proceeds to regenerate the information on the next channel. The recording of a new signal value through the converter 6 code - voltage in this channel passes in the usual way.

The device allows using two PCNs to organize almost any number of high-speed 25 channels of digital-to-analog conversion. Their number depends only on the quality of work of the analog memory blocks, in particular, on the decay rate and voltage in these elements. For existing analogue storage elements, the typical value of the decay rate is 10–100 mV / s, which, with an accuracy of 10 bits. bits, the amplitude of the output voltage of -10 V and 35 times, allocated to one digital-to-analog conversion, 10 μs allows you to organize, respectively, 50,000-5,000 channels of digital-to-analog conversion with an error, the 40 circuitry shown in the drawing, less than 0.5 least significant digit and conversion time on any channel 10 μs. When performing such a converter according to a well-known functional block diagram, 5000-50000 expensive 10-bit code-voltage converters would be required.

Claims (2)

The goal is achieved by the fact that a multichannel digital-to-analog converter containing a digital memory block, a control block, first keys, analog memory blocks and a single-channel converter code is voltage, the inputs of which are connected to the input code buses through the digital memory block and the outputs through the first keys are connected to the inputs of the analog memory block, the control unit input is connected to the channel number code bus, the control unit outputs are connected to the control inputs of the first keys and the digital memory block, entered the second keys and the second single-channel converter code — voltage (PKN), whose inputs are connected to the input code buses and the corresponding inputs of the digital memory block, the output of the second single-channel converter code — voltage is connected through the second keys to the corresponding inputs of the analog memory blocks and out the first keys. The drawing shows a functional diagram of the device. The channel number code bus is connected to the input of the control unit 1, and the input code buses are connected via the digital memory block 2 to the input of the first single-channel PCN 3, whose outputs are connected via the first keys 4 to the inputs of the analog memory blocks 5. The input code buses are also connected to the input of the second PKN b, the output of which is connected via the second keys 7 to the inputs of blocks 5 of the analog memory. The outputs of the control unit 1 are connected to the control panel to the inputs of the unit 2 digital memory, the first 4 and second 7 keys. Each channel of a multi-channel DAC conversion in block 2 of the digital memory is assigned one storage cell in which the current conversion code is stored. The device works as follows. The control unit 1 alternately reads the codes from the cells of the digital memory block 2 to the inputs of the first PKN 3, simultaneously opening the key 4 of the corresponding channel, in this mode the analog information is cyclically regenerated in the analog memory blocks 5, and the regeneration period is chosen so that to guarantee the accuracy of analog information at the outputs of blocks 5 of analog. When a new code arrives for recording in the channel whose number is fed to the individual Inputs of control unit 1, the latter opens analog key 7 in accordance with the specified channel number, thereby ensuring that the new signal value of the new PCN 6 is immediately recorded in the corresponding analog memory block 5 . At the same time, the control unit 1 writes a new conversion code into the cell of the digital memory unit 2 allocated for this channel. Thus, the regeneration process is not slowed down, and the new code value is immediately converted into an analog signal at the output of the corresponding channel. In the case when the recording of a new signal value and the regeneration of analog information must be performed on the same channel, the regeneration process on this channel is blocked and the control unit 1 immediately proceeds to the regeneration of information on the next channel. As a result, a new value of the signal through the converter 6 code - the voltage in this channel passes in the usual way. The device allows using two PKNs to organize virtually any number of high-speed digital-analog conversion channels. Their number depends only on the quality of operation of the analog memory blocks, in particular, on the decay rate, voltage in these elements. For existing analog storage elements, the typical value of the decay rate is 10-100 mV / s, which, with an accuracy of 10 bits. bits, the magnitude of the output voltage is -10 V and time, a tap for one digital-analog conversion, 10 µs, allows you to organize respectively 50000-5000 channels of digital-analog conversion with the error introduced by the circuit shown in the drawing is less than 0.5 of the least significant digit and conversion time over any channel is 10 µs. When such a converter was executed according to a known functional scheme, 5000-50000 expensive 10-bit converters would require a code-voltage. A multi-channel digital-to-analog converter containing a digital memory block, a control block, first keys, analog memory blocks, and a single-channel converter voltage code whose inputs are connected to input code buses through the digital memory block and the outputs are connected to the first keys via inputs analog memory blocks, the control unit input is connected to the channel number code bus, the control unit outputs are connected to controllers in,} the first keys and the digital memory block, which differs from Strongly increasing bystrodeystvk, it entered the second keys, and the second one-channel code converter - voltage inputs of which are connected to the buses and the input code corresponding to the digital inputs of the memory unit, output of the second one-channel code voltage converter is connected through the second keys to the corresponding inputs of the block. analog memory and first key outputs. Sources of information taken into account during the examination 1. Copyright certificate. CCC1 340077, cl. H 03 K 13/03, 29.06.70 2. Patent IT and 358308, cl. 179-15, 15.06.71 (prototype). / feff, / fOAfff ff Juw: /