SU974592A1 - Ring counter - Google Patents

Description

(5) RING COUNTER

one

The invention relates to automation and computing technology and can be used in the implementation of technical means of automation and computing technology.

A ring counter is known, which contains an input bus, an installation bus, bits on the Drtrigger, the first and second And elements in all bits, the additional And element and the HECl element.

However, this device is distinguished with not sufficiently high reliability of operation, resetting any O-flip-flop to O leads to transferring 1 to the first output, and a small recalculation factor n + 1, i.e. only one unit more than the number of p-triggers.

The closest in technical essence is a ring counter containing bits on series-connected O-flip-flops, O-input

The O-flip-flop of the first bit is connected to the inverse output of the O-flip-flop of the last bit, clock inputs. all D-flip-flops are connected to the input J bus G2 |.

A disadvantage of the known device is its limited functionality, since it does not have positional outputs, and the reliability of its functioning is low — malfunctions in the form of excess waves of zeros and ones are possible. The purpose of the invention is to enhance the functionality and increase the reliability of operation.

The goal is achieved by the fact that in a ring counter containing bits on series-connected D-flip-flops, the D-input of the O-flip-flop M of the first bit is connected to the inverse output of the O-flip-flop of the last bit, clock inputs of the 0-flip-flops from the second to the last the bit is connected to the input bus, entered into each bit except the first, first, second, third, and fourth elements AND, for the first bit the first, second and third elements AND the first bit, two elements NOT, three elements OR, first the inputs of the first, third and second fourth elements And each time a row, except the first, are connected respectively to the inverse and direct outputs of the D-flip-flop, and the second inputs of the first, second and third fourth elements And the same bits are connected respectively to the inverse and direct outputs of the O-flip-flop the first bit Yes, and the outputs of the first and fourth elements of the previous bits, the first inputs of the first and second elements of the first discharge and the first discharge are connected to the inverse and direct outputs of the first flip-flop, respectively, their second inputs through the first element are NOT connected to the output ohm of the first element OR whose inputs are connected to the outputs of the first and fourth elements AND of the last bit, the third inputs of the first and fourth elements of the first and second bits are NOT connected to the installation bus, the third inputs of the first and fourth elements of the last the bits are connected respectively to the fourth and direct outputs of the D-flip-flop of the first bit, the inputs of the installation to zero D-triggers of all the bits, except the second, are connected to the outputs of the first elements of their bits, the input of the installation to zero O-trigs The second bit of the bit is connected to the output of the second OR element, the inputs of which are connected to the installation bus and to the output of the first element AND of the second bit, the installation inputs to the unit D-flip-flops of all the rails, KpoMei first, are connected to the outputs of the fourth elements AND their bits the input of the unit to the unit of the first bit is connected to the output of the third element OR, the inputs of which are connected to the bus of the unit and the output of the third element AND to the first bit, the clock input. The D-flip-flop of the first bit is connected to the output of the third element AND the first bit, the first input of which is connected to the output of the first OR element, the second - to the input bus. The drawing shows a circuit of a ring counter. The device contains D-flip-flops 1 "1, 1-2, ..., elements, 2-3 ,. , .... ,,, .... tn; ,, ..., 6-8 AND, elements 9, 10 NOT, elements 11-13 OR, installation bus H, clock bus 15. Structurally, the proposed device consists of a Johnson n-bit ring counter, D-triggers, 1-2 , ... with a cross-connection between the last and first bits of the decoder of Johnson's counter codes into positional signals taken from the outputs, And,, .-., 3-2,,.:., 4-2,, ... elements -P; ..., feedback elements 8, 7 AND, control elements of the feedback elements - elements 9, 10 NOT, clocking elements of the D-flip-flop of the first bit - elements OR 13 and AND 8, elements of the initial state setting - elements OR 11, 12. The ring counter operates as follows. First, logical 1 of all bits is sequentially filled, starting from the first, and then the first bit goes to state O and the reverse occurs: sequential filling of all bits of the counter with logical 0. Scale factor 2 p. The outputs of the ring counter are the element outputs And the decoder 2, ..., 5,,, ...,. The initial state is set by feeding 1 to the installation bus 14. The installation signal through element 10 does NOT disconnect elements 7, 6 of the IS-feedback to the inputs of the installation in O and 1 0-flip-flops of the first and second bits 1-1, and sets them to 1 and.O. At the output of the AND 4x2 element, the first positional output, 1 appears, which corresponds to the initial state. After the first clock pulse at the outputs of the D-flip-flop 1I,, 3 state 110 and 1 at the output of the element. The state that follows, after the first O-trigger with a zero state, 0-m {eiggers does not matter - the decoder generates a match signal (logical 1) of the single states of the P-flip-flops from the first zero bit with the first zero bit and the second signal cannot be matched. After the second clock pulse at the outputs of the D-flip-flops

, 1 2, 1 "3, Ui state 1110 and 1 at the output of the .4 element, and so on, after the (n-2) -th clock pulse at the outputs of the D-flip-flops 1H.1, ... state 11 ... 10 and 1 at the output 5 of the LSM1, after (nl) -ro of the clock pulse, the D-triggers of all bits are set to 1 and H- at the output of the element. During the first half of the counting — sequential filling with logical 1 all bits — the signals (logical 1) from the outputs of the elements of the decoder — ele gmentes ,,... Prohibit the false switching from 1 to O 0-tri1-ger of their bits, blocking the false transfer, as a result of a failure, the output positional signal back to previous bits. False switching from 1 to O D-flip-flops is forbidden by AND-element feedback - element 6. False switching of D-flip-flops subsequent from the output signal does not affect the outputs of the ring counter. False switching from O to 1 of the first R-flip-flop with zero state leads to automatic transition of the output signal to the next bit. False switching from O to 1 at the same time of the first P-flip 30 jerk with zero state and subsequent leads to transfer of the output SIRnal through one or more bits Thus, only a false switch from O to 1 subgroup of two and more than 35 D-flip-flops, and necessarily, together with the first O-flip-flop with zero state, leads to transfer of the output signal to one or more bits .40

Claims (2)

1. USSR author's certificate of ho for registration No. 2831 13/18 21, cl. H 03 K 23/00, 1980. 2. Gutnikov V.S. Integral electronics in measuring devices. L., Energie, 1980, p. 211; rice .