SU974570A1 - Analogue-digital converter - Google Patents

Description

54) ANALOG-DIGITAL CONVERTER

The invention relates to information technology and is intended to convert analog values to digital equivalents.

The analog-to-digital converter is known, which contains an operational amplifier, an analog switch, a storage capacitor, a buffer amplifier, a comparator, a logic device, a two-position switch, a resistive circuit, a voltage converter, a reference voltage source, an output code register, and a synchronization circuit.

The disadvantages of such a converter include the complexity of the circuit and the inability to measure the amplitude values of alternating voltages, since this requires an additional device for determining the extremum of the input voltage.

A analog-to-digital converter is known, which contains a binary counter, the counting input of which is connected to the output of the pulse generator through a logic gate, and the outputs to the inputs of the code-voltage converter, the output of which is connected to the first input of the comparison device.

the output of which is connected to the first input of the trigger, the second input of which is connected to the start-up busf2.

The known converter is less complex, but has narrow functionality.

The purpose of the invention is to expand the functionality of the device.

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This goal is achieved by the fact that an analog-to-digital converter containing a binary counter, the counting input of which is connected to the output of the pulse generator through a logic gate, and the outputs to the inputs of the converter, is connected to the first input of the comparator, the output of which is connected with the first entrance

20 flip-flops, the second input of which is connected to the trigger bus, entered the elements And the key, and the binary counter: made in the form of a combinational adder with a register, the outputs of which 25 are connected to the first inputs of the combinational adder, the inputs to the outputs of the combinational adder, the second inputs are connected to installation tires through the elements, and controlling

Claims (2)

The 30 inputs of which are connected to the forward output of the trigger, the inverse output of which is connected to the transfer input of the lower bit of the combinator slot, and the control input of the logic valve is connected to the output of the comparator device, the second input of which is connected to the input bus through a key. FIG. 1 shows the block diagram of the device of FIGS. 2 and 3 —time diagrams explaining its operation. The analog-to-digital converter contains a pulse generator 1, a logic gate 2, an n-bit register 3, a n-ary combinational adder 4, a code-to-buck converter 5, a comparison device 6, a trigger 7, and 8 elements, 9, key 10. The device operates as follows. In the initial position, the state of the direct output of the trigger 7 corresponds to a zero-low potential. At the time of arrival on the bus Trigger pulse, the unit is set to the forward exit of the trigger and the code L is set at the outputs of the elements L, which is attached to the mounting buses 9, the register 3 and 0 are zeroed. At the output of the combinational adder 4, and therefore, at the outputs of the register 3 and the converter, the voltage code 5 also sets the code A. At the output of the converter, the voltage code 5 is at the level of the minimum quantum of the voltage increment from the output of the converter 5. The card is ready to receive information. If the conversion of constant levels is performed, then when the key 10 is closed, the input bus voltage is applied to the input of the comparator device 6 and, moreover, if the voltage Ug is greater than the voltage output from the code-voltage converter 5, then the output device is compared 6, a high potential acts, which opens the logic gate 2 n to the input of the register 3, pulses are received from the pulse generator 1 to record the state at the input of the register 3. Thus, the state of the register 3 code is increased by A on the outputs, since pulses are continuously summed up by the newly recorded code from register 3 with the code on the installation tires 9 on the combinational cyNiMator 4. A monotonic numeric sequence with discreteness A is formed at the input of the converter 5, and a discrete saw with discreteness of voltage U U is output at the output of the transducer 5 (Fig. 2). ). As the voltage rises, there comes a time when the voltage at k DUA, where K is the sequence number of the write pulse, becomes greater than the input, then a low potential is formed at the output of the comparator 6, which closes the logic gate 2. a negative jump comes along the direct exit to the zero state and closes the AND elements, and a unit appears at the transfer input of the lower bit. At the output of the combinational adder 4, a number is formed equal to (k-1) A + 1, and the voltage at the output of the converter 5 and ...... uU T (k-1) 1 is less than Uft and at the output of the comparison device 6 the unit is set again, which facilitates the passage of pulses to the register 3. But since the installation buses 9 are disabled and the outputs of the elements AND have zero, and the transfer input of the lower bit is one, a number 4 is formed at the output of the combinational adder, and at the output of the converter 5 a stupa A night saw with discreteness d U. The counting continues until the ir is greater or equal, zero is set at the output of the comparator 6, locking the logic gate 2. Conversion complete. Thus, if you choose the value of A greater than one, then the formed equilibration mode is realized. The value of A can be selected from various conditions according to the needs of the consumer. If, however, the approximate value of the input voltage is not known, then A must be taken such that the discreteness of the voltage at the output of the converter 5 with the generated mode is equal to the maximum limit of the more sensitive meter scale. At the same time, an analog-to-digital converter allows measuring the amplitudes of alternating voltages. The principle of the converter is similar to the previous one, but it has some features due to the fact that the input voltage is oscillatory. Thus, at an intermediate stage, when the input voltage decreases and becomes less than the voltage from the output of converter 5, a zero potential is set at the output of the comparison device, which blocks the fuzzy valve 2 and the information recorded in register 3 is stored until the next half-wave of the input signal arrives (Fig. 3) The balancing process is resumed if the condition Ug arrives. 7, but already in small steps until the voltage from converter 5 reaches the amplitude value of the input signal. The invention / analog-to-digital converter contains a binary counter, the counting input of which is connected to the output of the pulse generator through a logic gate, and the outputs — with the code-voltage converter inputs, the output of which is connected to the first input of the comparison device, the output of which is connected to the first input of the trigger, the second input of which is connected to the trigger bus, characterized in that Iren funktsionsshnyh features incorporated into it and the AND key, and a binary counter is formed as a combination of the adder with register, whose outputs are connected to first inputs of Raman sum 10Zapuskf ) The output of the device, the inputs to the outputs of the combinational adder, the second inputs of which are connected to the installation buses via AND elements, the control inputs of which are connected to the forward output of the trigger, the inverse output of which is connected to the transfer input of the lower bit of the combinational adder, and the control input the logic valve is connected to the output of the comparison device, the second input of which is connected to the input bus through a key. Sources of information taken into account in the examination of 1- USSR Copyright Certificate No. 498732, cl. H 03 K 13/02, 1976. 2. USSR author's certificate No. 400022, cl. H 03 K 13/20, 1971 (prototype). Adlt FIG. 3 IO output S output