SU869022A1 - Voltage-to-parallel type code converter - Google Patents

Description

(54) VOLTAGE CONVERTER — PARALLEL TYPE CODE

The invention relates to automation and computer technology and can be used as a voltage converter - code (NCP) in information-measuring devices. A PIC is known that contains a reference voltage source, a discrete reference voltage divider, a comparison device block, a decoder, a code distribution block, a key, an output code uncertainty uncertainty circuit, and a read resolution circuit 1. The disadvantage of this NCP is the conversion accuracy limited by the sensitivity threshold of the comparators. The purpose of the invention is to improve the accuracy of the conversion. Jt1o set target is achieved by the fact that a parallel-type code containing a source of reference voltage, block-matching devices, the first inputs of which are connected to the input busbar, and the outputs are connected to the input of the decoder, the input signal inverter is added to the voltage converter; while the inverter input of the input signal is connected to the input bus, and the output is connected to the first inputs of the level shift unit, the second inputs of which are connected to the source of reference voltage, voltage, and the outputs to input block rows slice level, the outputs of which are connected to second inputs of comparators block. FIG. 1 shows a functional diagram of the PNK parallel type. PNK contains an inverter 1 of the input signal, a source 2 of the reference voltage, a block 3 for level shifting, a block 4 for limiting the level, a block 5 for the comparing device, the input of the inverter 1 for the input signal being connected to the input bus and the first inputs for the block 5 for comparing devices, and an output for with the first inputs of the level shifting unit 3, the second input of which is connected to the source 2 of the reference voltage, and the output to the inputs of the level limiting unit 4, the output of which is connected to the second inputs of the comparison device unit 5, the outputs of which are connected to input ode decoder. FIG. 2 shows timing diagrams explaining the work of the NCP,

at the same time, the signal is measured; and - the signal at the output of the inverter; Xj is the signal at the output of the level offset unit; U (jrp limit levels; t.- ti is the response time of the comparing device; V .. is the maximum allowable value of the differential signal of the comparing device; UA is the threshold of comparing the comparing device.

The proposed NCP works as follows.

When the input measured signal arrives at the output of the inverter 1, an inverted measured signal appears with a constant scale. Using a level shifting unit .3 fed from a source of reference voltage 2, a signal is generated that changes the level of operation of the block of comparison devices 5. At the same time, the level of constant voltage at the outputs of the level shift unit is equal to twice the value of the voltage of the corresponding comparison device of the unit 5 comparing devices (Fig. 2). In this case, the operation of the aforementioned comparing device occurs at the level of the input signal corresponding to the level UA.

Due to the change in voltage (opposite to the input signal), at the second inputs of the block of comparative devices, the sensitivity threshold is halved, i.e.

SGP

where c is the sensitivity threshold of the proposed PNA,

d is the PNA sensitivity threshold when a constant reference voltage is applied to the reference inputs.

The decoder b converts a single code received from the outputs of the block 5 comparing devices into a parallel binary code. Level limiting unit 4 is designed to protect the inputs of the comparison devices against overvoltage.

The proposed PNA structure significantly improves the accuracy of the converter, which improves metrological characteristics.

Claims (1)

1. USSR author's certificate No. 445981, cl. H 03 K 3/17 1974 (prototype). . ta t .Z