SU599349A1 - Voltage-to-code converter - Google Patents

Description

I

The invention relates to measuring and computing technology and can be used in various information-measuring systems.

Izv, natural voltage converters in kofl parallel-sequential equilibration, cyclic, in which several digital code bits containing a differential amplifier, a voltage converter into a code, comparison circuits, an encoder, and registers are determined in parallel for each conversion cycle. In them, the sizes and position of the reference voltage scale (SCEN) are set under the assumption that during the time from the moment of the previous comparison of the signal with the SCEN to the moment of the current comparison, the input signal changed slightly l.

However, in these converters, the voltage is converted into code in a limited frequency range. With the expansion of the frequency range of the converted signals to the bottom of the dynamic errors increase.

A parallel-to-serial balancing analog-to-digital converter with an uncompensated difference scale conversion is known, consisting of a differential

an amplifier, one input of which is connected to the input terminal of the device, another input - with the output of a code to voltage converter, the third input - with an output of the control unit, a reference unit, a differential amplifier connected to the output, a decoder connected to the output of the comparison unit, valves and registers 2. The differential amplifier is made with a variable gain, the value of which is determined by the balancing ticks in accordance with the ratio

is No. AL- (A

Rde m is the number of comparison circuits;

oL - the base of the number system The process of converting a voltage into a code consists of three clock cycles, each of which performs a quantization of the signal into eight levels.

However, such a converter converts voltages varying at a rate not exceeding 0.5 quantum of the least significant bit during the conversion time. For this reason, the frequency range of the stresses it converts is limited. As the permissible rate of change of the transforming signal increases, dynamic errors increase in them. The purpose of the invention is to increase the permissible rate of change of the input signal by changing the scale conversion factor of the uncompensated difference in the balances of the equilibrium in order to exclude the output of the converted signal from the scale of the reference voltages. This is achieved by converting a variable gain amplifier with a variable gain factor, one input of which is connected to the input terminal of the device, another input — to the output of the converter L code to voltage, the third input — to the output of the control unit, a comparison unit connected to the output differential amplifier and to the output of the control unit; an encoder connected to the outputs of the comparison unit; valves and a register; some of the inputs are connected to the outputs of the control unit; the other inputs of the register are connected to the outputs valves, and the register outputs are connected to inputs of a code-to-voltage converter; an adder, elements of the OR / code scale bias code, and additional valves, whose synchronization inputs are connected to the outputs of the control unit, are entered; the encoder, the other inputs of the adder are connected respectively to the outputs of some elements, and the inputs of which through the corresponding additional valves are connected to the encoder turns, the inputs of the adder digits through each other e OR gate and additional flaps are connected to the busbars scale offset code, and the adder outputs are joined by through valves with the register inputs. The drawing shows a block diagram of the proposed voltage to code converter. The voltage converter in the code contains a differential amplifier 1, one input of which is connected to the input terminal of the device 2, another BXO with the output of the code converter to voltage 3, the third input - to the output of the control unit 4. Differential amplifier. 1 is made with a variable gain factor, the MI value of which is determined by the equalization cycles of 1. according to the ratio. where AND is the number of comparison circuits; the permissible signal increment at the i-th cycle, referred to the quantum of the lowest bit of the code. The device also consists of a comparison unit 5 connected to the output of the differential amplifier 1 and to the output of the control unit 4, an encoder 6 connected to the outputs of the comparison unit 5, valves 7 and the register 8. Some inputs of the valves 7 and the register 8 are connected to the outputs of the control unit 4 , the other inputs of the register 8 are connected to the outputs of the valves 7, and the outputs of the register 8 are connected to the inputs of the converter 3 codes to voltage. The device is also equipped with an adder 9, additional valves 10, 11, 12, 13 and 14, the synchronization inputs of which are connected to the outputs of the control unit 4, and the elements OR 15, 16, 17, 18, 19 and 20, and some inputs of the adder 9 through additional valves Yu connected to the outputs of the encoder 6. Other inputs of the adder 9 are connected respectively to the outputs of the elements OR 15, 16, 17, 18, 19 and 20, the inputs of which through the corresponding additional valves 10, 11, 12 and 13 are connected to the outputs of the encoder 6. Inputs the lower bits of the adder 9 through the additional valves 14 and elements OR 19 and 20 are connected to the buses of the offset code of the scale 21. The outputs of the adder 9 through the valves 7 are connected to the inputs of the register 8. The voltage-to-voltage converter works as follows. On signal At block 4 of control, the gain M of differential amplifier 1 is set to 1, then register 8 is reset to zero, and zero is entered into adder 9. Next, in adder 9, through valve 14, the scale offset code is inserted, which is introduced to exclude the output of the converted signal from the range of the reference voltage scale at the next balancing cycle. - After establishing transients in the code converter to voltage 3 and differential amplifier 1, the voltage to be converted is fed into comparison unit 5, where it is compared with a set of reference voltages. The result of the comparison is recorded in the comparison unit 5. According to the comparison result indicating the voltage U to be converted, to a certain quantum of the reference voltage scale, the encoder 6 generates the binary code of the number of this quantum. Then the binary code of the quantum number is fed through the valves 10, to the inputs of the adder 9, which forms, by adding the offset voltage code, to the previously shifted scale code. Next, the compensating voltage code through valve 7 is entered into register B. In accordance with this code, converter 3 generates a compensating voltage JK / this one cycle of balancing the transformed voltage Ux ends.

In the second equilibration cycle, the gain of the differential amplifier 1 is changed to Mg / equal to, for example, 6. The difference ULI UX-UK is amplified 6 times and is fed to the input of the comparison unit 5.

According to the comparison result recorded in the comparison block 5, the encoder 6 generates the next three bits of the binary code of the voltage to be converted, which through the valves 11, the OR elements 15 and 16 arrive at the inputs of the adder 9, the contents of which are previously changed to the offset value of the scale. Binary codes defined on the first and second cycles of the equation are summed in adder 9 with their overlapping in bits.

Next, the binary code from the output of the adder 9 through the valve 7 is transmitted to the register 8, the signals from the output of which initiate the production of a compensating voltage UKJ The process of determining the next bits of the binary code of the voltage being converted in the third and fourth cycles goes in a sequence similar to that described, so that the difference is that the gain of the differential amplifier 1 is set to 4 6 4 24 and 24 2 48. In the fourth cycle, the scale offset code is not applied to the inputs of the adder 9, because the compensating voltage It is not generated ..

Increasing the permissible rate of change of the input signal while maintaining a given level of dynamic error in the device is provided by setting the operating conditions that prevent the output voltage from being converted due to its change in the conversion process from the reference voltage scale.

Claims (1)

1. USSR author's certificate  213616, M.kl.N 03 E 13/17, 16.07.7 2, Digital Electrical Instruments. Ed. V.M.Shp Ndina, M., Energie, 1972, p.298.