SU966848A1 - Pulse repetition frequency multiplier - Google Patents

Description

 The invention relates to pulsed

technology.

Known pulse frequency multiplier, Soler 1 Amply pulse shaper, trigger, AND and OR elements, reference frequency generator, frequency dividers, switch, delay elements, multiplexers, coincidence element, short pulse shaper, counters, reference element, storage blocks, partitioned delay line , transfer unit f1.

This multiplier does not provide a sufficient multiplication factor.

The closest in technical essence to the proposed is a multiplier containing a control unit connected via a driver to an input bus, the outputs of which are connected respectively to the inputs of the correction and multiplication blocks, the input of the error correction block and the input of the dynamic correction block, the reference frequency generator, the output of which dinene with the inputs of the key, the correction unit and the input of the dynamic correction unit, the output of which is connected to the key input, the second input of which is connected to the output of the correction unit, and the output of the cell Here - with the input of the multiplier, the output of which is connected to one of the inputs of the block, error correction, a frequency divider connected to the output of the reference frequency generator and to the corresponding inputs of the correction block and the multiplication unit, as well as the delay element, AND, OR elements and triggers G2}.

However, this multiplier is distinguished by an insufficient dynamic range of frequency variations and a perceptible dynamic error.

The purpose of the invention is to expand the dynamic range of frequency variations of the output signal and reduce the dynamic error.

The goal is achieved. By the fact that, in the frequency multiplier, the following pulses, containing a control bucket, the input of which is connected to the input bus, the first output is connected to the first inputs of the multiplication unit and the error correction unit, and the second output is connected to the first input of the frequency divider, second and third inputs of the multiplication unit and the second input of the error correction block, the third input of which is connected to the output of the multiplication unit, the fourth input of which is connected to the output of the frequency divider, and the fifth input is connected to the output of the key, the first input of which is connected to the output a generator of qnop frequency and a second input of the frequency divider, a counter whose outputs are bitwise connected to the inputs of the IGW element I, a reversible counter. The OR element, the delay element, the trigger and the three elements of the two-input AND, a register, three delay elements, the three AND elements, the OR element, the one-shot, the trigger, the unit for determining the sign and the period increment code, and two binary multipliers, the first inputs of which are connected to the first output the control unit, the first and second inputs of the sign determining unit and the increment code of the period and the first input of the register, the remaining inputs of which are connected to the bit outputs of the sign determining unit and the increment code of the period, and the outputs of the register are connected to RRM with counter inputs and reversible counter inputs, the outputs of which are bitwise connected to the remaining inputs of the multiplication unit, the outputs of the bits of which are connected to the corresponding inputs of the bits of the sign determining unit and the period increment code, the third input of which is connected to the output of the reference frequency generator, The fourth input is connected to the second output of the control unit and the second input of the first binary multiplier, the third input of which is connected to the first inputs of the first and second two-input elements And, to the input of the first the delay element and the output of the error correction block, the input inputs of the first binary multiplier are connected one bit to the outputs of the frequency divider), and the output of the first binary multiplier is connected through the first element OR, the second input of which is connected to the output of the third element AND, and the single-oscillator connected to the second input of the key, the third input of which is connected to the first output of the first trigger, the first input of which is connected to the h; And the second input is connected to the first input of the counter and through serially connected second and third delay elements connected to the output of the second element And, the first input of which is connected to the first input of the fourth element And "whose output is connected to the first input of the reversible counter directly and with the first input of the second element OR through the fourth delay element, the second input of the second element OR is connected to the output of the third element of the backplane, and the output of the second element OR is connected to the second m input of the second binary multiplier, the output of which is connected to the first inputs of the third and fifth And elements, the second inputs of which are connected to the second inputs of the second and fourth And elements and to the corresponding outputs of the sign definition and period increment code, and the fifth output element I is connected to the second input of the reversible counter and / the first input of the second trigger, the second input of which is connected to the output of the first delay element, and you -. the stroke is connected to the second input of the first element I, the output of which is connected to the third input of the reversible counter, while the second input of the counter is connected to the output of the sixth element I, whose inputs are connected to the output of the reference frequency generator and the second output of the first trigger. The block for determining the sign and the period increment code contains a bit-connected reversible counter and a multi-input element And, and two flip-flops, the inputs of the first of which are connected to the output of the multi-input element And and the fourth input of the block for determining the sign and code of the period, and the first output is connected to the first the second trigger input and the first input of the reversing counter, the second input of which is connected to the second output of the first trigger, and the third and fourth inputs of the reversing counter are connected respectively to the first and t etim inputs sign increments and a code determining unit period, a second input coupled to a second input of the second flip-flop, the outputs of which are connected to the outputs of the sign determining unit and increments the code period. Each binary multiplier contains a counter and a register whose outputs are bit-wise connected to the inputs of the AND elements, the outputs of which are connected to the inputs of the OR element, the output of which is the output of the binary multiplier, whose inputs are connected respectively to the inputs of the counter and register. The drawing shows a structural electrical multiplier circuit. The multiplier holds the control block 1, the generator 2 of the reference frame TMJ the multiplication block 3, the frequency divider k, the error correction block 5, binary multipliers 6, 7, the key 8, the sign and code definition block 9 when the period increases, the one-shot 10, the register 11, counter 12 is reversible counter 13, multi-input element AND AND elements 15, 16 OR, triggers 17, 1B, delay elements 19 ... 22, elements 23 ... 28 I. First and second binary multipliers contain counters 29 and 30, respectively, registers 31 and 32; epemets 33-1 ... 33-N and ... 34-N AND, elements 35 and 3B OR. The multiplication unit contains counters 37, 38, the storage register 39, the multi-input element 0 AND, the element 1 OR, the elements 42-1 ... I. The error block contains the element k3 AND, the element OR, the trigger kS. The unit for determining the sign and increment code consists of a reversible counter 6, a multi-turn element 7 And and triggers and 49. The output signal is fed to the input bus 50. The input signal is removed from the output bus 51. The principle of operation of the multiplier is as follows. Pulses from generator 2 of frequency fg are fed to the input of divider k, the division factor of which is equal to the multiplication factor of the device, and the reversible counter 6 of block 9 into which the code N. output recorded in divider C and first counter 37 of block 3 is output from block 1 after the first period f. A reversible counter 6 is turned on for operation in the pulse subtraction mode. The pulses from the output of the divider k, the frequency of which is equal to fp / K, are fed to the input of the counter 37 of the block 3. For the period b. of the input signal HF generated by block 1, in: the counter 37 records the number of pulses N equal to the integer part of the division N / K, the remainder of the pulses uN N-NK is fixed in divider k, and the Ngy 8X2 code in the reversing counter b is fixed to the code difference, obtained in the first and second periods. At the end of the period, JX from block 1 first rewrites the obtained UN code values from divider k to register 31 multiplier 6, N from counter 37 to register 39, DMh (from a reverse counter to multiplier 7 and to register 11. In the register of multiplier 7, the width of which is on the frequency divider k frequency, rewritten the contents of the 4th bits of the BP code, and in register 11 - the older ones, and the N code from the splitter and counter 37 to the reversible counter 46, then with a delay of i; the second signal from the block is .O 1 through Element P1 rewrites the code from the memorized register 39 to the account 3B of block 3 and resets the divisor k and counter 37 to zero, preparing the latter for a new filling in the next period T, If period J from the period does not change to the period, i.e. d, then the correction of the dynamic error in the arrangement of the output pulses in the device is not performed, while the inputs of the 2-N elements and the input of the key 8 contain signal levels that freely pass signals from the lower bits of the second counter 38 to the input of the element 39 and not prohibit the passage of pulses from generator 2 through key 8. The output pulses of block 3 appear at the output of element Q each time, as soon as the counter 38 goes into the zero state, the subtracting input of which through the key 8. pulses are sent from the generator. 2 . With each output pulse of block 3, code N is rewritten from register 39 to counter 38 and the subtraction process is repeated. The output pulses are spaced uniformly only at N multiple of K, i.e. PryDM 0. When the elements 33-N are closed and the frequency of the signal at the output of the multiplier 6 (the output of element 35) is zero, as often. the output of the multiplier 6 determines the ratio r - f AV o output frequency of the signal at the output of the multiplier 6, the code value in the register is the frequency applied to the input of the counter 29, the counter size 29. While the one-shot 10 does not produce the inhibitory pulse and pulses from the generator 2 freely go through the key 8 to the input of the counter 38. For & N (., 0, to increase the multiplication accuracy, multiplier 6 corrects the arrangement of the output pulses of the block 3 over the time period 7p. It is necessary to correct the period of the pulse AN for the output This correction should be carried out evenly over time T. If, for example, the magnitude of the multiplication factor and, then every eighth pulse at the output of the device is corrected. Correction is to increase the follow-up period of each eighth pulse by T. The counters or, p1 D 29 and register 31 have the same width as divisor 4; therefore, when arriving at, the counter 29 K pulses are output at the output of the multiplier AN pulses (with and this is the 4th, 12th, 20th , ..., bo th pulses). Each of the pulses from the output of the multiplier b triggers a single vibrator, a raster 10, which produces a single pulse of duration T, prohibits the passage through the key 8 of the next pulse from generator 2 to the input of the second counter 38 of block 3, which leads to an increase in the output pulse period at the output of multiplier TQ value. As a result, the displacement of real-life pulses relative to ideally spaced ones does not exceed the value J, Reset of the counter 29, as well as divider 4, is performed from the second output of control unit 1. Output pulses are spaced evenly at. If the period (0) is applied to the device, then the dynamic error of the arrangement of the output pulses within the period Tg is corrected. The correction is made as follows. If TA is a GRU, then the reversible counter t6 of block 9 will have time to be reset, and the signal from the output of the element sets the trigger B of block 9 to one state, thereby switching the reversible counter k (for operation in tracking mode. For the remaining period of time, the reversing counter 46 will lock the code of Ysli Tpp), the JP is not reset, the trigger remains in the initial state, and the dM g code remains in the reversible counter i? 6. At the end of the period dM in this way, the signal from the first output of the control unit 1 is rewritten. It enters the multiplier register 7 and the register 11. By the same signal, the state of the trigger 48 is stored on the trigger 49. Thus, the increment sign of the input period determines the state of the trigger 49, the output levels of which are used to control the correction of the dynamic error of the output pulses. By the signal from the second output of block 1, the trigger 48 is reset to the initial state and the circuit is ready for i. i.,., i -г «« «number, j. Thus, block 9 determines the period increment code AN / i and its sign. / In order to reduce the dynamic error of frequency multiplication, it is necessary to carry out a uniform during the correction of the following periods, the pulses at the output of the device depending on the UN. If / AM, I K, then such correction can be made using a binary multiplier. In this case, with a positive sign LM, which corresponds to an increase in the period IW / i, the correction consists in increasing the period of the output pulses by TQ with a negative sign dN (T., T -), the correction consists in reducing the period of the bN output pulses by Tj , If f D N, (K then, obviously, a correction depending on the sign of uN by the value of + T needs to be subjected to the output pulses of the device every period. If, where m l, 2.3 ... then each period To the output pulses of the output curve also Depending on the sign of AN-i, it is necessary to correct for. If, has intermediate values of CC (t + 1) K, then the correction can be represented as two components:

a constant correction that increases or decreases, depending on the sign of the DM of each of the output multiplier periods during time T1 by a constant value of tTo, and the variable correction, which is uniform, uniform for the time Tp51. correction of the following periods / d1, - | -TK pulses at the output of the device by the value of T depending on the sign of LCC If, for example, 7 then a correction by a constant value Td, since m t t is subject to each output pulse at the device output, and the output correction is subject to variable correction. In this case, the correction should occur evenly over time, i.e. every eighth impulse at the output of the device,

The variable correction in the device is carried out with the help of the multiplier 7, the register from the low bits of the reversible counter 6, corresponding to the number, is written to the register. The constant correction is carried out using a register 11, in which a code from the higher bits of the reversible counter is written, corresponding to the number t. If the current and inverse outputs of the trigger 9 of block 9 are set to levels, respectively, the opening elements 2k, 25 and the closing elements 2b, 27. The impulses from the output of the device pass through the element 2k, 21 and 16 to the input of multiplier 7, at the output of which AN-tK pulses are formed (for AK, and, this, the 12th, the 20th, ... 60th impulses). These pulses through the open element 25 and 15 are fed to the input of the one-shot 10, which generates a single pulse with a duration TQ prohibiting passage through the key. 8 one pulse from the generator 2 to the input of the counter 38 of the block 3, which leads to an increase in the period of the output pulse of the device by the value TO. The delay time of the element 21 is selected in such a way that the variable correction over the dynamics is carried out after performing the correction for the remainder of the pattern.

The pulses from element 21 through element 20 arrive at the synchronous input of counter 2, rewriting into it the code from register 11, corresponding to the number m, and to the second input of trigger 17, which

switches over and closes key 8 on the direct output, and opens element 28 via the inverse output, through which counts 12 are received from the generator 12. Pulses from generator 2 are reset. When counter 12 is reset, which: , which will return the trigger 17 to the initial state, in which the key 8 will open, and the element 28 will close, not passing to the input of the counter 12 pulses of the reference frequency. Thus, the key: 8 for each output pulse of the device is closed at the time of PTT, after the passage to the counter 38

reference frequency pulses, which will lead to an increase in the next

each output pulse device; at a constant value of tT, since at the second inputs of elements 42-N there are permissive levels from the output outputs of the reversible counter 13. The delay time of element 20

is selected in such a way that the constant correction over the dynamics is performed after the variable correction. If trigger E of block 9 closes the 2k and 25 elements and opens elements 26 and 27. Pulses from the output of the device pass through the element 26 on the sync reverse version of the counter, rewriting into it the code from register 11, corresponding to the number m, and through element 22 and element 16 to the counting input of the multiplier 7. If A N, then, at the output of multiplier 7, the signal frequency is zero and there is no pulse at the output of element 27. Therefore, the unit is not added or subtracted to the code of the reversible counter 13, since the summing input of the counter 12 does not receive pulses, and the trigger 18 is in the initial state and closes the element 23 that the device’s output pulses do not pass to the subtracting input of the reversible counter 13 .

Claims (3)

In accordance with the code of the number m in the reversible counter 13, the corresponding elements are closed, forbidding) | (signals from the corresponding least significant bits of the counter 38 of the block 3) As a result, the pulse at the output of the element kQ follows the tto value. does not change, then the cycle time of each output pulse of the device is reduced by a constant value of mTr. If ANj, -mK pulses are generated at the output of the multiplier 7 when the output pulse YctportcTsa arrives at its input K, Each output pulse through the elements m AND 27 is added to the code of the reversible counter 13, increasing it by one, and switches the trigger 18, which opens element 23. When an output impulse of the device appears through the open element 23, one is subtracted from the code of the reversible counter 13, then determined by the delay time of element 19, trigger 18 returns to the initial state by closing element 23. Thus, when a pulse appears at the output of multiplier 7, the code in the reversible counter 13 corresponds to the number rc-1, and in the absence of a pulse, to the number t. When the code is mon-1, the corresponding elements 42-N are closed, as a result the period of the output pulse of the device is reduced by the value of {m + DTc. Thus, the device performs a constant and variable correction. The device inspects the piecewise linear extrapolation of the period, the corrected value of the period f is determined by the expression Toy. T4) U + () Allowable change in uT, not limited to I (K-1) That (- that does not limit the dynamic range of the frequency of the input signal. The correction of the dynamic error in the distribution of output pulses occurs evenly over the period determined by extrapolation, Tgy. As a result, the dynamic component of the error arrangement of the output pulses does not exceed the value of HE}), which reduces the dynamic error of frequency multiplication. The combination of two corrections, for the remainder jCiN and noukN, taking into account the dynamic change of the input signal frequency, in the device gives the maximum displacement of the pulses really following at the device output relatively ideally spaced no more than I2To (within the period T, Absolute period error J is equal to Atg, Tg, -T, y, T, C2Te -, + T, and Tbt 5gLtvh.When exceeding / ltgy l of T, the output of the device may lose one last pulse at the end of the generation period or may generate two times impulse that mind The device is designed for error correction block 5, which works as follows. The output pulses of block 3 from the output of element 0 pass through element 44 to the output of the device and to the counting input of the trigger 5 set by E the zero state of the pulse from the second output of the control unit 1 at the beginning of the period - if by the end of the Tjjy period to the output, the device has passed an even (odd) number;;; pug;.; at even (odd) coefficients, the multiplication factor, then the zero cHrrsiji;,; The direct (inverse) output trigger 5 will close the element k3 and will not miss the signal from the first output of block 1 to the output of the device. Otherwise, element 3 is opened with a single signal from trigger 5 and an additional pulse is inserted into the output pulse sequence from the first output of block 1 of the control place lost as a result of the reduced period to the period by an amount greater than T. Thus, the described technical the solution allows the dynamic range of the input signal frequency to be expanded and the dynamic error of frequency multiplication to be reduced. Claim 1. A pulse multiplying frequency multiplier comprising a control unit, the input of which is connected to the input bus, the first output is connected to the first inputs of the multiplication unit and the error correction unit, and the BOT ... course is connected to the first input; the second and third inputs of the multiplication unit and the second input of the error correction block, the third input of which is connected to the output of the multiplication unit, the fourth input of which is connected to the output of the frequency divider, and the fifth input is connected to the output of the key whose first input is connected to Exit of the reference oscillator and WTO eye input frequency divider, a counter which outputs bitwise soeyinen; with inputs of the multi-input element AND, reversible counter, element OR, delay element, trigger and three two input elements AND, and so on, and with that, Mto, in order to expand the dynamic range of changes in the frequency of the output signal and reduce the dynamic error, a register, three delay elements, three AND elements, an OR element, a one-shot, a trigger, a block for determining the sign and code of the increments of the period, and two binary multipliers, the first inputs of which are connected to the first output of the EH control block, the first and second block inputs The definitions of the sign and the code of the increments of the period and the first input of the register, the remaining inputs of which are connected to the bit outputs of the block for determining the sign and the code of the period conversions and the outputs of the register are connected bitwise with the inputs of the counter and the inputs of the amplifiers whose outputs are bitwise connected with the rest of the inputs of the multiplication unit, the outputs of the bits of which are connected to the corresponding inputs of the bits of the block for determining the sign and the increment code of the period, the third input of which is connected to the output of the reference generator often O, the fourth input is connected to the second output of the control unit and the second input of the first binary multiplier, the third input of which is connected to the first inputs of the first and second two-input elements And, with the input of the first delay element and the output of the error correction block, j frequency divider outputs, and the output of the first binary multiplier through the first element OR connected in series, the second input of which is soy: dinene with the output of the third element AND, and the single-oscillator is connected to the second key input, the third input of which is connected to the first output of the first trigger, the first input of which is connected to the output of the multi-input element I, and the second input connected to the first input of the counter and connected to the second and third delay elements through sequentially connected And, the first input of which is connected to the first input of the fourth element AND, the output of which is connected to the first input of the reversible counter directly and to the first input of the second element OR through the fourth delay element, second the input of the second element OR is connected to the output of the third element for support, and the output of the second element OR is connected to the second input of the second binary multiplier, the output of which is connected to the first inputs of the third and fifth elements AND, the second inputs of which are connected to the second inputs of the second and fourth respectively And elements and with cooTBef.the exits - i dami of the block for determining the sign and the period increment code, the output of the fifth element I is connected to the second, the input of the reversible counter and n pBhiM input of the second trigger, the second input o is connected to the output of the first delay element, and the output is connected to the second input of the first element AND whose OUTPUT is connected to the third input of the reversible counter, while the second input of the counter is connected to the output of the sixth And element whose inputs are connected to the output of the general; the torus of the reference frequency and the second output of the first trigger. 2. The multiplier of claim 1, about 1 and 4, and with the fact that the block for determining the sign and code of the period increments contains a bit connected reversible counter and a multi-input element And two triggers, the inputs of the first of which are connected to the output of the multi-input element And and the fourth input of the block for determining the sign and increment period, and the first output is connected to the first input of the second trigger and the first input of the reversible counter, the second input of which is connected to the second output of the first trigger, and the third and fourth inputs of the reversing account The chick is connected respectively to the first and third inputs of the sign definition block and the period increment code, the second input of which is connected to the second input of the second trigger, the outputs of which are connected to the outputs of the sign definition block and the period increment code. 3. The multiplier according to claim 1, characterized in that each binary multiplier contains a counter and a register, the outputs of which are bitwise connected to the inputs of the AND elements, the outputs of which are connected to the inputs of the OR element, the output of which | 59668 816 The output of the binary multiplier, 1, USSR Author's Certificate, the inputs of which are connected according to No. 82lt i 0, cl, H 03 K 23/00, .79. with counter and register inputs. 2. USSR author's certificate Sources of information, according to application number 2725988 / l8-21, taken into account during the examination, $ cl. H Q3 K 23/02, 1,02.79.