SU705657A1 - Pulse recurrence rate multiplier - Google Patents

Description

(54) MULTIPLE OF FREQUENCY FOLLOWING PULSES

one

The present invention relates to a pulse technique.

A known multiplier for the frequency of the following pulses, containing a pulse shaper, pulse counters, comparison units, a memory register, a control unit and a trigger 1.,

The disadvantage of the frequency multiplier is a decrease in its accuracy at high multiplication factors.

A pulse frequency multiplier is known that contains a pulse frequency reference divider, input and output pulse shapers, a pulse counter and a reference frequency pulse counter, a control unit, a memory register and a block, of And 2 elements.

The disadvantage of this multiplier is also reduced accuracy with large multiplication factors.

The aim of the invention is to improve the accuracy of multiplication.

For this purpose, a pulse multiplying frequency multiplier, containing an input pulse generator, the first input of which is connected to the input bus, a reference frequency generator, the output of which is connected to the input of a frequency divider, a memory register, whose inputs are connected to the outputs of the pulse counter, and the first output through the transfer unit is connected to the first input of the pulse counter of the reference frequency, the output of which is connected to the second input of the transfer unit through the output pulse shaper, an adder, a sum storage register and The prohibition element, the output of which is connected to the second input of the reference frequency counter, the first input is connected to the second output of the output pulse shaper, and the second input - to the output of the reference frequency generator and the second input of the output pulse shaper, the third input of which is connected to the first output of the adder, first. move ko- the second input is connected to the second INPUT of the storage register, and the second to the output of the sum storage register, the first input of which is connected to the second output of the adder, and the second input to the third output of the output pulse shaper, while the second input of the input shaper is connected to the output of the frequency divider, the third input is with the code of the reference frequency generator, the first output is with the first input of the register register, the second and third outputs are with the inputs of the pulse counter. The drawing shows a structural electrical circuit for multiplying the frequency of the trace | No pulses. It contains a reference frequency generator 1, a divider 2 successive and pulses frequency, an input driver 3, a pulse counter 4, a second register 5, a parallel code transfer unit 6, a reference frequency pulse counter 7, an output pulse driver 8, a sum storage 9, 10, element NOT 11 (prohibition element). Circuit 12 is the input bus of the device. A string of 4 pulses per p binary bits consists, for example, of an (n-mr) -discount scaling circuit and serially connected to it, the m itself, m g-bit counts, which are controlled by the switch. The integer r, which determines the modulus width, is determined from the relation. g logjd (for example, with d 10, g 4, and npH.d 2,) - ,. Reference Frequency Counter 7, also. is made up of serially connected (p-gpg) bit-type scaling circuit and mr-bit counting modules, which are controlled through switching blocks. The adder 9, consisting of identical summing modulo d blocks connected in series to the transfer in series, can be switched by the switch to sum up numbers with oversized but fixed (for a given code position comma) word width. The switches are controlled by the length, the code state of which corresponds to the required position of the comma in the required multiplication factor. The input driver 3-, synchronized by the reference frequency generator 1, processes the input signal arriving at the input- bus and the signal from the output of the splitter 2k of the pulse frequency with a variable fractional division factor. In addition to forming a pulse sequence arriving at the input of the counter of 4 pulses, it also generates a census pulse of the content of this counter in the storage register 5 and a reset pulse, the pulse counter to its original state. The output (| puller 8 pulses, also synchronized by the generator I of the reference frequency and processing the overflow signal of the counter 7 and fflyly at the reference frequency and the transfer signal from the adder 9, forms the output pulse sequence of the device and generates the following control signals: a parallel code rewriting pulse from the memory register: 5 counts 7 pulses of the reference frequency through the transfer unit 6, the pulse records the result of the summation from the adder 9 to the register stores w 10 and the signal to prohibit the passage of impulses ows from the generator 1 through the element NOT 11 to the input of the counting pulse of the reference frequency 7. The principle of operation of the frequency multiplier is as follows: Suppose you want to implement multiplication by some arbitrary coefficient K, which can be represented in the numbering system based on d i - (,. ii. nO. K ,,.,,, ...-. a.; where (I -I- 1); is the maximum word width with which the divider with peregagshim fractional division factor 2 can operate, then, learn the limitations, imposed on the integer part, the division coefficient 2 "-, d - v. with 5 -ci-j --- 6 g a g --j. Therefore, a state must be established on the control bus 2 of the frequency divider 2. the corresponding code combination in the AND-and-Required additional factor, multiplying in this case, is equal to d. The code corresponding to this additional multiplication factor, through control tines and switches, prepares the depot counter 4, adder 9 and counter 7 impulses of the reference frequency to implement the specified multiplication factor. In the counter, 4 pulses with the first 1 g-bit counting modules being switched to. the modulo d count, and the remaining (m-f) modules and the scaling circuit are included in the target so that they form a single (n-ir) -bit binary counter. In addition, the switch of this counter is connected to the output of the input shaper of the installation inputs of the triggers of this counter in such a way that its initial loading will correspond to the number code (2-2d). At the same time, the adder 9 switches to a third-party modulo d number. 5 .. This operation is carried out due to the fact that the transfer signal over the switch the sum of the switch to the torus 9 C1 is withdrawn only from the output of the ith to the row of the summing block. In counter 7, the pulses of the reference frequency are switched by internal switches in such a way that the first i moduli of the mercury circuit and the signal from the output of the NOT element il are fed directly to the counting input (i + i) -rp of the counting modulus. As a result, a binary (p-ir) bit counter is generated. The operation of the frequency multiplier occurs as follows. At the moments when the next pulse of the multiplied signal arrives at the input pin 12, the input driver 3 binds each imx to a clocked series of oscillator 1 of the reference frequency f. At the same time, the signal of overwhelming the contents of the counter is sequentially generated in turn sequentially expanded in time. 4 (P numbers) in the storage register 5, and then, with an interval of half the period of the reference frequency To / 2 -. pulse reset counter 4 to the state corresponding to the code number (2 - 2d). Simultaneously with the generation of the census signal, the input driver 3 prohibits the passage of the next pulse from the output of divider 2 to the counting input of counter 4. If at the time of generating control signals (A pulse appears at the output of the divider, the input driver 3 remembers this, and reset signal is set by the counter 4 to the corrected state corresponding to the number code (2d + 1). After that, the prohibition of the pulse sequence from the output divides 2 to the input of counter 4 is removed, and during the next period of the input signal Tg, the next counting of pulses takes place, those fd stepping with frequency 1d frequency of the pulse sequence at the output of divider 2 with variable fractional division factor, Cd division factor of divider 2. The number P recorded during this time in scrTtraw 4 and determined the expression -5c. Vi:, after the census in memorizing regaster 5, is used by subsequent blocks to convert into a sequence of uniformly distributed output pulses of the required frequency fjj,. Such a conversion is It follows as follows. The number P stored in the storage register 5 is divided into two components; a whole P vJ.H fractional Pjl- I VjfWJ; ... means the integer part of the number enclosed in D. brackets. In this case, the part P is fed in the inverse binary code to the transfer unit 6, and the fractional part P is used by the adder 9. The output driver 8 pulses as the overflow signal from the output of the counter 7 pulses of the reference frequency вы periodically generates, besides the output signal of the multiplied frequency f ,), the pulse of the census of the initial Code; aP (f is the inverse binary code of the 1-digit Pi) to counter 7, the pulse recording the result of the next summation from the adder 9 to the storage register 10, and also bans the passage of one pulse output from the reference frequency oscillator 1 through the element input on schegshka 7 NOT P. Thus, the output signal of the multiplier shzirovan sync signal counter overflow 7. The pulse sequence output period is determined sootnoscheniem; , T „2 --- C2 --- P, .. (P, .2. If at the moment of the occurrence of the overflow signal from counter 7 there is a transfer signal from the output of adder 9, then the output driver 8 pulses prohibits to perform hedoldeg one and two pulses from the generator I to the input of the counter 7, which allows to obtain a new value of the period of the output signal h-ii-: -T „C2 -P, -Z7-T CP 2- iV 9 directly depends on the order of the fractional part. Of the P number, and thus the proper alternation of the output pulses, put on the time stool which is given intervala1 / w T.ts, | -,, sredshsh determines the period of the output pulses Vt - Q V -Pz- ..cg-). Since the number P is determined by 1O1em n, TBIJ. „, 1, р - 2d .. о -Tr-J-M 2: d.„ 1 where d K. is the required coefficient multiplied. . . Let us consider the methodical method of the guest in the arrangement of the output pulse sequence. Since the measurement of the period of the multiplied frequency is made as a result of memorizing a discrete sequence of reference pulses of the time interval equal to the input period, the maximum error in determining the P number does not exceed the unit of the youngest bit.

/ P-TI51

where P is the real derived value in the preliminary 4 expression

/ 11M.,

GAL

At the same time, the maximum phase shift in the output multiplied sequence during the next period of the input signal will deliver T,

L Taht

Bi;

BbDS, Bb

 aic

I21G

  out

in frequency multipliers, implemented according to the principle of a half-head multiplication factor, equal to the delegate coefficient, the maximal value of the phase increment in the output sequence is determined by

That (T.

T To (

mavc-2JC L BtoW

ъъ

2 t.

Bbia hj in this way because of

.sl ay j

one

it can be seen that the greater the multiplication factor multiplication, the more precisely the required multiplier factor is implemented in relation to the compared devices.

If the value is limited to 2iT, then for a given range of changes in the integer part of the multiplication factors from 1 to 1000, the top order: high frequency frequencies is determined from the expression: ..,.

 . one

Y OUT K U (for the declared device), .V

Have

,, 1о

-e

(for prototype),

above d 10;

With a generator frequency fg equal to 4-10 Hz,

The following values of the limiting frequencies are respectively:

about / g.

 mqy. VK - 10) 360kHz

(for the application of its object) ..;

Mch

2K

. mc IK 10 j prototype)

Claims (2)

1. USSR author's certificate No. 354546, cl. H 03 K 5/00, 1971. 2. USSR author's certificate No. 357668, cl. H 03 K 5 / 01,1972 (prototype). n S IV- Ik L Ti . ti C -... M S