SU957228A1 - Device for extraction square root from the sum of two value squares - Google Patents

Description

one

The invention relates to automation and computing and can be used in analog computing and modeling devices, in automation devices when solving problems of coordinate transformation, determining the components of a vector, etc. It is known a device for extracting the square root of the sum of the squares of two voltages, containing a module allocation module, a block separating the maximum signal, a three-input adder with transmission coefficients K, K, K, with the outputs of the module allocation modules connected to the first 5 and third inputs of the adder with a factor To Kj and with the inputs of the maximum allocation unit, the output of which is connected to the second input of the adder with a factor K. Relative at -20. The error of calculating this device is -k% l.

The closest technical solution to the present invention is a device for extracting the square root of the sum of the squares of two SRIs, containing two module allocation units, whose inputs are device inputs, and the outputs are connected to the inputs of the first selection module of the maximum signal, the output of which is connected to the first the input of the three-input adder, the second input of which is connected to the output of the second signal extraction unit, the output of the three-input adder is the output of the device 2.

The disadvantage of the device is low accuracy (1.5%).

The purpose of the invention is to improve accuracy.

This goal is achieved by the fact that the device for extracting the square root of the sum of squares of two quantities, contains two allocation modules of the module, whose inputs are the inputs of the device, and twelve inputs are connected to the inputs of the first selection module of the maximum signal whose output is connected to the first input of a three-way adder , the second input of which is connected to the output of the second maximum signal extraction unit, the output of the three-input adder is the device output, the minimum signal extraction unit is entered, and a voltage divider, wherein the inputs of the minimum signal allocation unit are connected respectively to the outputs of the module allocation units, and the output of the minimum signal allocation unit is connected to the third input of the three-input adder and to the first input of the second signal extraction unit whose second input is connected via the voltage divider to the output of the first block selection maximum b | - nala. , The drawing shows a block diagram of the device. The device contains the first and second blocks 1, 2 allocation module, the first and second blocks 3 | 5, the selection of the maximum signal, the block k, the allocation of the minimum signal, the voltage divider 6, a three-input adder 7. The device operates as follows. Input inputs and X and Uy are supplied to the inputs of the first and second allocation modules of the module. Voltages (/ Uh) are respectively removed at the outputs of these blocks, which are fed to the inputs of the minimum and maximum 3 output selection blocks. At the output of the block C, the value mi p (7i, (y, / Uij /) is allocated, and at the output of block 3, max (/ Ujf /, f Uy /) is extracted, which are fed to the input of the block 5 for extracting the maximum signal, and block 3 is fed to the input of block 5 through voltage divider 6. At the output of block 5, a voltage proportional to the value (/ Ux /, / U9 /), min (/ Ux /, / 1Ц) is formed. The outputs of blocks 3-5 go to input dam adder 7 with coefficients K, (, Kp, Kj, respectively. Thus, the voltage at the output of the adder 7 with equal scales of input and output values is equal to

Uj-K, mo (xlfUJ, / Uy /) tKjniin | Ux /, / Uyf) v v jwaxf (.max (/ U, /, / Uy /), min (/ Ux /, / Uy /),

2. USSR author's certificate “W itit2 / 487, class, G 06 G 7/20, 1973 (prototype). WHAT corresponds to the approximate U -fuJ-Tuy. The coefficients K, K2, K, K4 are selected from the condition of minimizing the error. Q, Bk; K2 0.3b2; Cs 0.197; K4 0, P5, the methodological error of the implementation of the equation Z - y does not exceed 1; The implementation of the proposed device does not present technical difficulty when using standard elements. The positive effect of increasing the calculation accuracy to 1% is due to the design features presented above.

Claims (1)

 The invention The device for extracting the square root of the sum of squares of two quantities, containing two modules of the module allocation, the inputs of which are device taps, and the outputs are connected to the inputs of the first block of the maximum signal, the output of which is connected to the first input of the three-input adder, the second input of which is connected With the output of the second maximum signal extraction unit, the output of the three-input adder is the output of the device, which is. Of course, with the aim of increasing the accuracy of the device, a minimum signal extractor and a voltage divider are entered into it, with the highlights of the minimum signal highlighting connected to the outputs of the modulus selection blocks, and the output of the minimum signal extracting unit connected to the third input of the three-input adder and to the first input of the second selection unit of the maximum signal, the second input of which through the voltage divider is connected to the output of the first selection unit of the maximum signal. Sources of information taken into account during the examination 1. USSR Author's Certificate No., cl. G 06 & 7/20, 1972.