SU796837A1 - Decimal-to-quinary fraction converter - Google Patents

Description

. (54) DETERMINAL CRUSHED TRANSFORMER IN FIFTH

one

The invention relates to automation and computing and can be used in the construction of decimal converters.

A decimal-to-binary converter is known that contains a shift register, correction blocks, and a control block ij.

The disadvantage of this converter is great complexity and low conversion speed.

The closest in technical essence to the present invention is a converter of a decimal code to pythic, containing a binary-decimal shift register, a decoder of a binary-decimal code, the inputs of which are connected to the outputs of a binary shift register, and a decipher of the decimal code into a binary one. , the first group of inputs of which is the group of inputs of the converter, and the outputs are connected to the inputs of the binary-decimal shift register 2.

The disadvantage of this converter is the impossibility of converting fractional numbers and the low conversion speed associated with the passage of the resulting notebook.

output code through the shift register before it enters the output register.

The purpose of the invention is to increase speed.

This goal is achieved due to the fact that the converter of decimal fraction into pythic, containing binary-decimal shift

O register, decoder of binary-decimal code, the inputs of which are connected to the output of the 1st binary-decimal shift register, encoder of the decimal code into binary-decimal, the first group of inputs of which is a group of inputs of the converter, and outputs are connected to the inputs of the binary shift register, dividing block and register

0 of the hex code, the control input of which is connected to the control output of the dividing unit by two, the bit outputs of the register of the hex code are outputs of the converter,

5, the information outputs of the division unit into two are connected to the second group of inputs of the encoder; decimal code to binary decimal, information inputs of the register of the ctric code

0 connected to information boards

older bits of block allocation by two.

The drawing shows the block diagram of the proposed Converter.

The device consists of an encoder 1 of a decimal code in a binary-decimal, a binary-decimal shift register 2, a diffuser 3 of a binary one, a block of 4 divisions into two, a register of five five-fold code.

The algorithm for converting the decimal number to the pentameter system consists in successively dividing the decimal number and intermediate quotients by 0.2; Starradium discarded bits of intermediate quotients, taken in direct order, are a polyric equivalent; the number of division procedures (the number of digits of the fiveth equivalent is determined by the specified accuracy of the calculations. In the hardware implementation, the decimal division by 0.2 is replaced by the division by 2.

Example. Transfer of decimal fraction 0,4624 to the pyrite system: t 4624

1ShZG212

Ш 2

The converter works as follows.

From the binary-decimal shift register, the 2nd kth bit of the translated (intermediate private), represented in the code, is received through the decoder 3. The block 4 is divided into two, which forms the private bit according to the rules of the decimal table division and stores the bit the remainder according to the rules of the decimal table of division, which is used for the receipt of the (K + 1) -th digit of the number being transferred when forming the next partial quotient. The generated Qth private bit from block 4 is transmitted via encoder 1 to register 2. The best partial intermediate bits are not transferred to the register. The five-digit equivalent bits go into register 5, which is prepared before each division by 2 of the number itself or intermediate quotient.

The advantage of the converter is that the process of converting decimal fractions into a pyrite system is reduced to performing only two arithmetic operations — division and addition (the multiplication of the translated number by 0.5 is replaced by the operation of division by 0.2). The proposed converter allows to increase the speed due to the fact that the generated bits of the output code go directly to register 5, not

5. pre-pass through the register 2.

Claims (2)

1. USSR author's certificate number 311474, cl. Q 06 P 5/02, 1969. 2. USSR author's certificate 645150, .kl. G 06 F 5/02, 1976. Ti ni gi code