SU949658A1

SU949658A1 - Device for driving modulo three check code

Info

Publication number: SU949658A1
Application number: SU792778165A
Authority: SU
Inventors: Валерий Павлович Глынин; Сергей Михайлович Кобзев; Владимир Федорович Тараев
Original assignee: Предприятие П/Я Г-4677
Priority date: 1979-06-08
Filing date: 1979-06-08
Publication date: 1982-08-07

Description

Изобретение относитс к вычислительной технике, в частности к устройствам формировани контрольного кода по модулю три и может е5ыть использовано в цифровых вычислительных машинах.The invention relates to computing, in particular to devices for generating a control code modulo three and can be used in digital computers.

Известно -устройство дл формировани и хранени вычетов чисел по модулю три, содержащее элементы ИЛИ, НЕ, св занные друг с другом соответствующим образом Г13.A known device for forming and storing modulo-three residue of residues containing the elements OR, NOT, are associated with each other in an appropriate manner G13.

Недостатком устройства вл етс малое быстродействие.The disadvantage of the device is low speed.

Наиболее близким к предлагаемому по технической сущности и .достигае7 мому результату вл етс устройство дл формировани контрольного кода по .модулю три, содержащее узел свертки по модулю три и логические элемерты И, ИЛИ, НЕ, св занные соответственно друг с другом .23.The closest to the proposed technical essence and the achieved result is a device for generating a control code using a module three, containing a convolution node modulo three and logical elements AND, OR, NOT, associated respectively with each other. 23.

Недостатком этого устройства вл етс то, что при увеличении разр дов контролируемого кода в устройство добавл ютс логические элементы И, ИЛИ, НЕ, образующие последующие логические уровни, что приводит к снижению быстродействи .A disadvantage of this device is that with an increase in the bits of the code being monitored, logical elements AND, OR, NOT are added to the device, forming subsequent logic levels, which leads to a decrease in speed.

Цель изобретение - повышение быстродействи устройства.The purpose of the invention is to increase the speed of the device.

Поставленна цель достигаетс тем, что в устройство, содержащее узел свертки ло модулю три, первый и второй входы которого вл ютс соответственно первым и вторым входс1ми устройства , введены два .мультиплексора и элемент ИЛИ-НЕ, причем входы устройства , начина с третьего до последнего , соединены с адресньми вхо10 дами первого и второго мультиплексоров , входы которых соединены соответственно с первым и вторым выходами устройства, выход элемента ИЛИ-НЕ вл етс третьим выходом устройства, The goal is achieved by the fact that the device containing the convolution node of module three, the first and second inputs of which are the first and second inputs of the device, respectively, has two multiplexers and an OR NOT element, and the inputs of the device, starting from the third to the last, connected to the address inputs of the first and second multiplexers, the inputs of which are connected respectively to the first and second outputs of the device, the output of the OR-NOT element is the third output of the device,

15 первый выход узла свертки по модулю три соединен со входами, начина с первого по (l+Sk), первого мультиплексора и со входами, начина со второго по (, второго мульти20 плексора, второй выход узла свертки по модул1д три соединен со входами, начина со второго по (2+3k), первого мультиплексора и со входами, начина с третьего по (З+ЗК), второго 15, the first output of the convolution node modulo three is connected to the inputs, starting from the first through (l + Sk), the first multiplexer and to the inputs, starting from the second to (, the second multi 20 plexer, the second output of the folding node modulo1d three is connected to the inputs, starting from the second to (2 + 3k), the first multiplexer and with the inputs, starting from the third to (S + SQ), the second

25 мультиплексора, третий выход узла свертки по модулю три соединен со входами, начина с третьего по (3+3k), первого мультиплексора и со входами, начина с первого по (1+ЗК), второго 25 multiplexer, the third output of the convolution node modulo three is connected to the inputs, starting with the third through (3 + 3k), the first multiplexer and with the inputs, starting from the first through (1 + 3K), the second

Claims

30 miniplexer, where k takes the number of integers from 0 to the number of address inputs of the multiplexer. The drawing shows a block diagram of a device for generating a control code modulo three. The device contains a node 1 convolution, multiplexers 2 and 3, and the element OR NOT 4. The device operates as follows. The first and second inputs of the convolution device 1 modulo three receive information from the two most significant bits of the monitored code. At the outputs of the convolution node, signals are formed, respectively. residues 1, О, 2. The signal corresponding to residue 1 is fed to the information inputs, starting from the first through (1--3k, multiplexer 2 and inputs, starting from the second through (2-i-3k multiplexer 3. The signal corresponding to the O balance goes to the information input, starting from the second to (2-t-3k), multiplexer 2 and inputs, starting from the third to (3 + 3k) multiplexer 3. The signal corresponding to the remainder 2 is fed to the information inputs, starting from the third to (3 + 3k) , multiplexers 2 and inputs, starting from first to (), multiplexer 3. Depending on the information received at the address The inputs of multiplexers 2 and 3, at the outputs of the device, generate residual signals modulo three of the entire monitored code. Thus, the introduction of the multiplex and the OR element does not lead to a significant reduction in the time spent forming the control modulo cd. The sizes of the generated code does not lead to an increase in the time of formation of a control code. Formula of the Invention A device for generating a control code modulo three containing a convolution node modulo three, first and in The inputs of which are, respectively, the first and second inputs of the device, characterized in that, in order to increase the speed of the device, the first and second multiplexers and the OR-NOT element are introduced into it, the inputs of the device, starting from the third to the last, are connected to the address inputs the first and second multiplexers, the outputs of which are connected respectively to the first and second inputs of the element OR NOT and are respectively the first and second outputs of the device, the output of the element OR NOT is the third output of devices , the first output of the convolution node modulo three is connected to the inputs, starting from the first through (), the first multiplexer and to the inputs, starting from the second through (), the second multiplexer, the second output of the folding modulo three is connected to the inputs, starting from the second to ( 2 + 3k), the first multiplexer and with inputs, starting from the third through (3 + 3k), second multiplexer, the third output of a modulo three convolution node is connected to the inputs, starting from the third through (3 + 5k), first multiplexer and with inputs , starting with the first through (1 + 3k), the second multiplexer, where k - takes), the value of integer chi ate on n - the number of bits of the control code rows. Sources of information taken into account in the examination 1. The author's certificate of the USSR 163806, cl. G 06 F 11/00, 04.01.63.

2. Sellers F. Methods of detecting errors in the operation of the digital computer. World, 1972, p. 91 (prototype).