SU938198A1 - Device for measuring resistance - Google Patents

Description

(54) DEVICE FOR MEASURING RESISTANCE

The invention relates to a measurement technique, in particular to digital devices for measuring resistance to direct current. A device is known comprising a constant voltage source, a voltage divider, a discharge and reference resistors, a discharge and charge switch, a switch, a differential amplifier, a current integrator, a null organ, a trigger, and a control unit. This device eliminates the effect on the resale of measuring voltage instability of the source of direct voltage tl. However, a significant disadvantage of the known device is the influence on the measurement result of the additive component of the error of the analog-digital converter due to the input drifts of the amplifier and the integrator, which significantly reduces the measurement accuracy especially low resistance to resistance. The closest technical solution to this invention is a digital ohmmeter containing series-connected current-setting, measurable and exemplary resistors, common terminals of which are connected to a common busbar, a second terminal of an exemplary and one terminal of a current-carrying resistor are connected respectively to the voltage source, o & the terminals of the current and measurement resistors and the second terminal of the reference resistor are connected to the corresponding inputs of the switch, to the output of which are connected in series grator, null organ, selector, a clock generator is connected to the second input of the selector, a control unit, the output of which is connected to an input of the switch, the first input - with the output of the organ nup, the second input - with the second input of the clock generator, the second input zero -organ is sub-connected to a common bus, digital reading unit 2}.

A disadvantage of the known technical solution is the narrow measuring range, especially of low-resistance resistors, which is determined by the commensurability of the resistance values of the reference and measured resistors.

The purpose of the invention is to show measurement accuracy while extending the measurement range,

The supplied circuit is achieved in that a device for measuring the resistance, containing a series-connected current source and an exemplary resistor, the second terminal of which is connected to the housing, and the first pin is connected to the first input of the switch, the second input of which is connected to the first input terminal for connecting the measured resistor , the first output is connected to the integrator input, the output of which is connected via a null organ to the selector input. To the second INPUT of which the output of the clock generator is connected, the control unit whose output is The second is connected to the control input of the switch, the digital reading unit, the second input of the null organ, connected to the housing, the second exemplary resistor, reversible counter, amplifier is inserted, the first output of the sample resistor is connected to the housing and the third input of the switch, the second Output is connected to the second input terminal for connecting the measured resistor and the 4eTBepTbnvi input of the switch, the second and third outputs of which are connected to input 1 "1 amplifier, the output of which is connected to the second input of the integrator, outputs of the selector Accordingly dineny a subtraction and summing inputs of the reversible counter you hod which are respectively connected to data inputs of a digital measuring indicator block n with the signal input of the control unit, the second and the third output is connected respectively to upravp kntsimi selector inputs and a digital measuring indicator unit,

FIG. 1 is a block diagram of a device for measuring resistance; in fig. 2 - voltage diagrams.

The device for measuring the resistance contains a series-connected measuring resistor 1, a current source 2, a first exemplary resistor 3 and a second exemplary resistor 4, a switch 5 connected by its four inputs, respectively: first to the common terminals of the measuring resistor 1 and the current source 2, second - with common Pins of measuring measuring resistor 1 and the second model resistor 4, third with a case and fourth with common pins of current source 2 and the first model resistor 3, first two outputs of switch 5 connected to the input of the amplifier 6, and the third output is connected to one of the EKODOV integrator 7, to the other input of which the output of the amplifier 6 is connected, the output of the integrator 7 is connected to the input of the zero-organ 8, the output of which is connected to one of the inputs of the selector 9, the corresponding outputs which are connected with the reading and summing of the inputs of the reversible counter 10, and the outputs of the latter are connected respectively to the signal input of the control unit 11 and the information inputs of the digital reading unit 13. The output of the generator is connected to another input of the selector 9. ra 12 wherein the clock control unit 11 outputs are connected with the control inputs of the switch 5, the selector 9, and the digital measuring indicator unit 13.

Device. works as follows.

When the device is turned on, the signals from the control unit 11 shift the switch 5 to the position corresponding to the connection of the second sample register 4 to the input of the amplifier 6, and the input of the selector 9 is disconnected from the generator output 12 clock pulses. . In this case, the input of the integrator 7 from the output of the amplifier 6 receives a voltage equal to

,, СЗК „± idr), (- 1)

where kch is the gain of the amplifier 6;

D is the current of the current source 2; RJJ is the resistance of the second reference resistor 4; Odr - the value of the input drift amplifier 6,

Moreover, the resistance value RO is chosen so that the voltage drop across it for a given value of current 3 is always greater than the possible value of the drift voltage, i.e. EV 5 IDR | ILK (DRo) 0.

Claims (2)

The voltage U-j is integrated by the integrator 7 during the interval T, the duration of which is chosen equal to the period of the interference voltage (power supply network of the device) and is specified by the control unit 11. At the end of the interval T, a voltage arises at the output of the inrerpjaropa 7,} Oidt K 4K pRo U p) T, (1) rfleKj, -2. - the converting factor of the integrator 7. After the interval T has expired, the signals of the control unit 11 translate the nepesai reader 5 into the position corresponding to the connection of the first peaic Top 3 to the integrator 7 input, and the output of the selector 9 is connected to the subtractive input of the reversible counter 1O for passing pulses 12 clock pulses. At this point, voltage U is applied to the input of integrator 7. removed from the first reference resistor 3 opposite to polarity to the voltage Uj, (3) where 3 is the current source current; I is the resistance of the first exemplary resistor 3. Moreover, the value of the resistance R is chosen much higher than the resistance RQ, i.e. and and. The voltage U2 is integrated by the integrator 7 during the time interval tj up to the instant of the integrator current to the initial state, i.e. until the equality t Uu is fulfilled - к „Ь а --Ки: З11-Ь (4 °. Thus, the time interval is easy to determine by equating (2) and (4) where K, t V.) The end of the interval lf is fixed zero-body 8, the output of which completes the selector 9 and the passage of pulses from the generator 12 clock pulses to the subtracting input of the reversible counter 10 pulses. In the reversible counter 10, a number code will be fixed (Fig. 2). ,, - (where is the pulse frequency from the generator 12 clock pulses. Then the signals of the control unit 11 switch the switch 5 V. position corresponding to the connection to the input of the amplifier 6 serially connected measuring resistor 1 and the second exemplary resistor 4. In this case, from the output of the amplifier 6 the input of the integrator 7 receives the voltage,) irr. (; where RX is the resistance value of the efMoro emer {Resistor 1; RO is the resistance value of the second phase resistor 4. Voltage U is integrated by wwterrator 7 during the interval T, the duration of which is equal to the period and specified by the control unit. 11. At the end of the interval T, The voltage of the integrator 7 arises: 3-KvilM HK, t CRx + Ro) (c) the converting factor of the integrator 7. After the interval T has expired, the signals of the control unit 11 switch 5 to the position corresponding to the connection to the input of the integrator 7 ovogo resistor 3, and the output of the selector 9 is connected to a summing input of down counter Yu for the passage of pulses of the generator 12 clock pulses. At this moment voltage 04 is applied to the input of the integrator 7 taken from the first model resistor 3 opposite to polarity to the voltage .3R, 49) The voltage 1) 4 is integrated by the integrator 7 during the time interval fea. until the trigger 7 returns to its original state, i.e. until equality is satisfied, jDRat - Kv, :) Rt2, og at the moment when the summing input of the reversible counter 10 receives the number of pulses. - KJ, equal to the number of pulses received at the subtracting input, the reversible counter 10 goes to the zero state. In the transition step of the reversible counter through zero, which is fixed by the control unit 11, the latter gives permission for the result to be read by the digital reading unit 13. The end of the interval -b is fixed by the zero by the authority 8, which closes the selector 9 with its signal and the pulses arrive at the summing input reversive UCH5 counter Yu stops. 7 .9 Equating (8) and (10) is not difficult (to determine the time interval J-) UApJT 2 .- :) a (from the moment of transition through the zero of the reversible counter 10 until the end of the interval -tg). At the time of the end of the interval of time 4. "g, the summing input of the reversible counter 1O will receive the number of pulses f Qt a and the code of the number (Fig. 2) VNa-N ,, TeN, .-- R --KRx, - coefficient no conversion of analog-to-digital conversion. The measurement result is indicated by a digital readout unit 13. After which the control unit 11 controls its signals, the device returns to the initial state and the measurement cycle is repeated. As can be seen from (12), the measurement result does not depend on the values of RO 3 U, etc. It is sufficient to ensure only their stability for the time of one measurement cycle, which is almost always performed. Thus, by introducing a second reference resistor 4 and. reversible counter 10, as well as the algorithm of operation in the invention, compared with the known device, showed significant measurement accuracy and extended the lower limit of the measurement range, since the influence of the input drift of the amplifier was eliminated, which is especially important at low resistance values. The lower limit of measurement is practically limited by the sampling error. Claims An impedance measuring device comprising, in series, a single source and a sample resistor, the second output of which is connected to the housing and the first output to the first input of the switch, the second input of which is connected to the first input terminal for connecting the measured resistor, the first output to the integrator input, the output of which is connected through a null-organ to the input of the selector, to the second input of which the output of the clock generator is connected, the control unit, the output of which is connected to the digital input block, the second input of the nullorgan is connected to the housing, characterized in that, in order to measure the measurement accuracy while extending the measuring range, a second exemplary resistor, reversible counter, amplifier is inserted, the first output of the exemplary resistor is connected to the housing and with the third input of the switch, the second output is connected to the second input terminal for connecting the measured resistor and to the fourth input of the switch, the second and third outputs of which are connected to the inputs the amplifier whose output is connected to the second input of the integrator, the outputs of the selector are connected respectively to the subtractive and summing inputs of the reversible counter, the outputs of which are connected respectively to the information inputs of the digital reading unit and the signal input of the control unit, the second and third outputs of which are connected respectively to the matching unit. kgkimi inputs of the selector and the digital reading block. Sources of information taken into account during the examination 1. USSR author's certificate No. 601632, c. QOI R 27 / GS, 1976. 2. US Pat. No. 3875503 ,. NCI 324-62, 1975. 1