SU1273825A1 - Digital voltmeter - Google Patents

Abstract

The invention can be used to construct digital voltmeters with automatic correction of the additive error component. The purpose of the invention is to increase the speed. The device contains a counter 15, elements 10, 18, triggers 19, 17, a reversible counter 21, an amplifier 3, a source 2 of bias voltage, a switch 4, a source 11 of reference voltage, a key 7, an integrator 5, a null organ 8, a block 9 controls, a key management unit 6, a phase detector 12, a clock pulse generator 13, a frequency divider 14, a decoder 28 with an indicator board, a memory block 27, a transfer circuit 25. Introduction of 1 polarity switch, selector 20 ,. items. And 23, 24, the element OR 24, the selector 20, the transfer circuit 16, the formers 22, 30.31 pulses, the trigger 29 allows organizing the output of the measurement results in each operation tick, depending on (/) the values of the input signal in the adjacent cycles . 2 Il.

Description

The invention relates to electrical measurement technology and can be used to construct digital voltmeters with automatic correction of the additive error component. The purpose of this is to increase speed by organizing at each step of operation the output of measurement results, depending on the values of the input signal in the adjacent steps. FIG. 1 shows a digital voltmeter circuit; in fig. 2 - timing diagrams of the main nodes. The digital voltmeter contains a polarity switch 1, a bias voltage source 2, an amplifier 3, a switch 4, an integrator 5, a control unit 6, a first key 7, zero | 0rgan. 8, control unit 9, first element 10, reference voltage source 11, phase detector 12, clock generator 13, frequency divider 1A, counter 15, second transfer circuit 16, second trigger 17 second element 18, first trigger 19 , selector 20, reversible counter 21, first pulse shaper 22, third element AND 23, element OR 24, first transfer circuit 25, fourth element AND 26, memory block 27, decoder 28 with indicator display, third trigger 29, second and third shapers 30 and 31 pulses. Two input busbars of a digital voltmeter are connected to the input of the switch 1 of polarity, the first output of which is connected to the first input of the amplifier 3, the second output is connected to the first terminal of the source 2 of the voltage of the mixture, the second terminal of which is connected to the second input of the amplifier 3, the output of which connected to the first input of the switch 4, the second input of which is connected to the output of the source 11 of the reference voltage. The output of the switch 4 is connected to the first clamp of the key 7 and to the input of the integrator 5, the output of which is connected to the input of the null organ 8, which is connected to the second clamp of the first key 7 with the output of the first trigger 19, the input of the control unit 9 and the first the input of the first element AND 10. The output of the control unit 9 is connected to the input of the key management unit 6, the outputs of which are connected to the control inputs of the polarity switch 1, the switch 4, the first key 7. The bus 50 is connected to the first input of the phase detector 12, the output of which connected the input of the clock generator 13, which is connected to the output of the control unit 9, the second input of the first element 10 and the input of the frequency divider 14, the output of which is connected to the second input of the phase detector 12 and the input of the control unit 9, the output of which is connected to the third input of the first element And 10 and with the input of the fourth element And 26, the second input of which is connected to the single output of the first trigger 19 and the first input of the selector 20, the second input of which is connected to the output of the first element And 10 and the input of the counter 15. The output is quarter About element 26 is connected to the input of the first pulse shaper 22, the output of which is connected to the input of the first transfer circuit 25 and to the input of the second shaper 30, the output of which is connected to the input of the second transfer circuit 16, to the counting input of the trigger 29, and output Which is connected with the (n + 1) th input of the decoder 28 with the indicator board and with the installation input to the zero state of the counter 15 and the zero setting of the trigger 17; the n-information outputs of the counter 15 are connected to the n inputs of the second circuit 16 transfer, information the ion outputs of which are connected to the p inputs of the parallel recording of the reversible counter 21, the summing and subtracting inputs of which are connected to the outputs of the selector 20; (n + 1) -th output of the reversible counter 21 is connected to the installation input to the single state of the trigger 17, whose single output is connected to the input of the And 18 element and to the third input of the selector 20, the fourth input of which is connected to the zero output of the trigger 17 and to the input And 23, the second input of which is connected to the zero output of the trigger 29, the single output of which is connected to the second input of the AND 18 element, the output of which is connected to the first input of the OR 24 element, the second input of which is connected to the output of the AND 23 element, and the output of the OR 24 element plugged in One first transfer circuit 25, the other inputs of which are connected to the information outputs of the reversible counter 21, information outputs of the transfer circuit 25 are connected to the inputs of the memory block 27, the information outputs of which are connected to the information inputs of the decoder 28 with the display board. The digital voltmeter works as follows. 10. In the initial state, the signal from the control unit 9 by means of the key management unit 6 switches the polarity switch 1 to the position where the measured voltage -U is supplied to the measuring circuit 15. Triggers 17, 19, 29, counters 15, .. 21, memory block 27 are set to zero state. At time t (FIG. 26), the block

m f 7t- -t- - t -Uc Uh (t) + Uap) dt +,

l oM-j Lj where t is the time constant of the integrator 5; Ug is the trigger threshold; null-op; fg is the frequency of the pulse generator of 13 clock pulses; and &, source voltage 11; and - the bias voltage of source 2; K is the gain of amplifier 3; U (t) - is the interference voltage in the input measuring circuit: T pT is the integration time in the first cycle; T is the period of interference voltage. The pulses of the sequence N are recorded in counter 15 (Fig. 2d). At time tj, the positive pulse front from the output of the null organ 8 (Fig. 2c) trigger 19 is switched to one state (Fig. 2e), opening And 26 at the corresponding input, as well as the selector 20. In the second measurement cycle at t a pulse of duration (tj-t) (tj-t) is formed. This imN f (t -t) - Uc

which arrive at the input of the counter 21 enters the zero state.

15 and through the selector 20 - to subtract- 55 The signal at its output translates into

reversible counter input 21. single trigger state 17

At time t to the input of the counter 21 with- (Fig.2l). A single signal one goes N pulses of the number Nj. Counter trigger output 17 through open 1273

(1) 54 9 by means of block 6 for the time tj-t (fig. 2a) connects the output voltage and amplifier 3 and ,, -n and + and (t) j + and where is the voltage of the drift of amplifier 3, to the integrator input 5, and at time tj, through switch 4, an exemplary voltage U of source 11 of the reference voltage, opposite in polarity to and, is connected to the input of integrator 5. In the process of push-pull integration, the voltage is 1 g, -bU ,, U, (t) + dt} + IM and, dt Ue. tl is converted to the number of pulses N, the pulse passes through the element AND 26 (Fig. 2e). At the moment (Fig. 2g), at the output of the imaging unit 22, a pulse of duration 7g is formed, rewriting from the reversible counter 21 into the memory block 27 a code of a number equal to zero. At the moment t, the pulse from the output of the imaging unit 30 (FIG. 2z) rewrites from counter 15 to the reversible counter 21 the code of the number Njj and flips the trigger 29, the closing element And 23, and opening the 7th element in the single state. the output of the driver 31 (Fig. 2k) resets the counter 15 and the trigger 17 to the zero state. The signal from blocks 9 and 6 switches the switch 1 to the position where the voltage + U, is applied to the measuring circuit. Therefore, the voltage U, K, (t) + UciJ + on the VCode amplifier 3 is two stroke. . by integrating T. fj {K u ,, (t) -U + U5p} dt + t G w ,,, j dt C tg is converted into the number of pulses Nj t) Uapjdt - UxT.K element AND 18 and element OR 24 enters to the input of the transfer circuit 25. At the same time, this signal from the output of the trigger 17 selector 20 permits the passage of subsequent pulses (Nj-N) of the number Nj to the summing input of the reversing counter 21. By the time t. the code of the number will be fixed in it. - K-2-T ,, N, -N, -and „proportional to the value of the measured voltage U and not depending on the values of the parameters h, U., U (t), U., elements , the input of an analog to the digital-analog conversion circuit. The voltage Up (t) noMexij can have an asymmetrical impulse waveform. Due to its constant for the time of two measurement cycles, the influence of U (t) on the measurement result is eliminated. Due to the introduction of phase-locked loop frequency, the pulse frequency in the generator 13 is proportional to the network frequency. Therefore, the product T, fg A const with a change in the period T of the interference voltage Uj (t), and the expression (3) takes the form N, -N, 2КА,. - by choosing K and and the Polarity value - is multiplied by a multiple of 10 that the polarity Uo is opposite to the polarity of the voltage and.,. If the voltage U were negative, then NJ N. Therefore, by the time t in the reversible counter 21, the number code (N / f-Njj) would be fixed. The presence of a zero signal at a single output of trigger 17 and a zero signal at a zero output of flip-flop 29 would result in a zero signal at the output of the element OR 24. A pulse at the output of shaper 22 rewrites the number code (Nj-N,) from the output of counter 21 and polarity + from the output of the SHSh 24 element - to the memory block 27 and to the decoded 28. The pulse at the output of the driver 30 converts the trigger 29 to the zero signal and rewrites the code of the number Nj from the counter 15 to the reversible counter 21 The pulse at the output of the driver 31 resets trigger 17 to counter 15 to zero state . The polarity switch 1 is turned on at a position where a voltage U is applied to the measuring circuit. Since J NJ, the number of pulses NJ N arrives at the input of the counter 15 and through the selector 20 to the subtracting input of the calculator 21. By the time the two-act integration ends, the number of () pulses is fixed in the reversible meter 21. Trigger 17 is in the idle state due to N Nj. The single signal from the zero output of the trigger 29 and the single signal from the zero output of the trigger 17 lead to the appearance of a single signal at the outputs of the AND 23 element and the OR 24 element. Therefore, at the beginning of the fourth quarter, the measurement in the block. memory 27 is recorded as one number (N, t-N ,,) (Nj-Nj). If the negative polarity is about NJ NJ, the trigger 17 is transferred to a single state. The summing input 1 $ of the eversive counter 21 from the output of the selector 20 is received, (Nj-Nj) pulses. Element And 18 is closed with a signal from a single trigger output 29, and And 23 element is a zero signal from a zero output of trigger 17, Therefore, at the output of element OR 24, a zero signal is obtained that indicates a negative polarity of the measured voltage. An inventive formula Digital voltmeter containing a sensor, two AND elements, an OR element, a clock generator, two triggers, a reversible counter, an amplifier whose second input is connected to the first output of a bias voltage source, and the output is connected to the first input of a second switch the input of which is connected to the output of the voltage source, and the output to the first output of the first key and the integrator input, the output of which is connected to the input of the zero-body, the output of which is connected to the input of the first trigger, to the input of the control unit and the second output of the first key, the first output of the control unit is connected to the input of the key management unit, and the second output is connected to the third input of the first element And, the first and second outputs of the control unit are connected to the control inputs of the switch and the first key, the 50 Hz bus is connected with the first input of the phase detector, the output of which is connected to the input of the clock pulse generator, the output of which is connected to the inputs of the control unit and frequency components, the output of which is connected to the second input of the control unit and the second phase input A new detector, the p inputs of the decoder with the indicator board are connected to the corresponding p-outputs of the memory unit, the p inputs of which are connected to the corresponding p-outputs of the first transfer circuit, (n + 1) -th output of the reversible counter, the output of which is connected to the first input of the second element I, the output of which is connected to the first input of the second element I, the output of the first element I connected to the input of the counter, characterized in that (in order to increase the speed of operation, a third trigger is inserted into it) the transfer, the selector, the third and fourth elements And, three pulse shapers, a polarity switch, the first input of which is connected to the first input bus, the second input to the second input bus, the control input - to the third output of the key management unit, and the first output - the first input of the amplifier, the second output - with the second output of the voltage mixing source, the output of the zero-organ is connected to the first input 4 of the first element And, the single output of the first trigger is connected to the first input of the selector and the first input of the fourth element And, the second the stroke of which is connected to the third input of the first element I, and the output connected to the input of the first pulse shaper, the output of which is connected to the input of the first transfer circuit and to the input of the second pulse shaper, the output of which is connected to the input of the second transfer circuit, with a counting input of the third trigger and input the third pulse generator, the output of which is soy; is repaired with the (n + 1) th input of the decoder unit with the indicator board, the inputs for setting the second trigger to the zero state and the counter whose input is connected to the second input se The lecturer, the second input of the first element I is connected to the output of the clock pulse generator, and the n information outputs of the counter are connected to the p inputs of the second transfer scheme, the n outputs of which are connected to the p inputs of recording the number of the reversible counter, the inputs of the summation and subtraction of the reversible counter are connected to the corresponding the selector outputs, and p information outputs are connected to the p-inputs of the first transfer scheme, Dp + 2) -th input of which is connected to the output of the OR element, the inputs of which are connected to the outputs of the second and third element / I, the second input of the second element I is connected to the unit output of the third trigger, and the inputs of the third element I to the corresponding zero outputs of the second and third trigger, and the selector control inputs are connected to the unit and zero outputs of the second trigger.

id

fcf

Claims (1)

Claim A digital voltmeter containing a sensor, two AND elements, an OR element, a clock, two triggers, a reversible counter, an amplifier, the second input of which is connected to the first output of the bias voltage source, and the output is connected to the first input of the switch, the second input of which is connected to the source output reference voltage, and the output with the first output of the first key and the input of the integrator, the output of which is connected to the input of the zero-organ, the output of which is connected to the input of the first trigger, with the input of the control unit and with the second output the first key, the first output of the control unit is connected to the input of the key control unit, and the second output is connected to the third input of the first AND element, the first and second outputs of the control unit are connected to the control inputs of the switch and the first key, a 50 Hz bus is connected to the first input of the phase detector, whose output 7 1273825 8 is connected to the input of the clock generator of the first element And, and the output is connected to the output pulses, the output of which is connected to the inputs of the control unit and the frequency divider, the output of which is connected to the second input of the control unit j and the second input of the phase detector, η inputs of the decoder with indicator the display is connected to the corresponding η-outputs of the memory unit, η of the inputs of which are connected to the corresponding 10 η-outputs of the first transfer circuit, (n + 1) -th output of the reverse counter is connected to the input of the second trigger, the output of which is connected to the first the input of the second element And, the output 15 of which is connected to the first input of the second element And, the output of the first element And is connected to the counter input, characterized in that / in order to increase the speed of operation, a third trigger, a second transfer circuit, and a selector are introduced into it , the third and fourth elements And, three pulse shapers, a polarity switch, the first input of which is connected to the first input bus on the 25th, the second input to the second input bus, the control input to the third output of the key control unit, and the first output to the first input strengthen- jq la, the second output is with the second output of the mixing voltage source, the zero-organ output is connected to the first input of the first And element, the single output of the first trigger is connected to the first input of the selector and to the first input of the fourth And element, the second input of which is connected to the third input with the input of the first pulse shaper, the output of which is connected to the input of the first transfer circuit and the input of the second pulse shaper, the output of which is connected to the input of the second transfer circuit, with the counting input of the third trigger and the input of the third form pulse changer, the output of which is connected to the (n + 1) -th input of the decoder unit with an indicator board, the inputs of the zero state of the second trigger and counter, the input of which is connected to the second input of the selector, the second input of the first element And is connected to the output of the clock , and η information outputs of the counter are connected to η-inputs of the second transfer circuit, η outputs of which are connected to η-inputs of the number of the reversible counter, the inputs of summing and subtracting the reverse counter are connected to the corresponding outputs selector dams, and η information outputs are connected to the η-inputs of the first transfer circuit, the (n + 2) -th input of which is connected to the output of the OR element, the inputs of which are connected to the outputs of the second and third AND elements, the second input of the second AND element single output of the third trigger, and the inputs of the third element And with the corresponding zero outputs of the second and third triggers, and the control inputs of the selector are connected to the single and zero outputs of the second trigger.