SU1247802A1 - Installation for calibration checking of analog-to-digital converters - Google Patents

Abstract

The invention relates to measurement technology, instrument making and metrology and can be used for automatic calibration of ADC, digital voltmeters and other devices containing a quantization operation to determine their systematic component error. The purpose of the invention is to increase the accuracy of verification, which is achieved by introducing into the device of a controlled source 16 a functional analog signal, an analog adder 17 and a calculator 11 of the arithmetic mean. In this case, the control unit 12 is made of a pulse generator 13 and pulse frequency dividers 14 and 15. In addition, the device contains: block 1 of memory with storage elements 2 and 3, converter 4 code - voltage, adder 5 codes, source 6 of exemplary analog signal, adjustable ADC 7, block 8 of registration, arithmetic unit 9, calculator 10 of difference codes, control unit 12, pulse generator 13, dividers 14 and 15 of the number of pulses. 1 il. (L | C 4 00 about U

Description

The invention relates to measurement technology, instrumentation and metrology, and can be used for automatic calibration of analog-digital converters, digital voltmeters, digital ohmmeters, and other instruments containing a quantization operation to determine their systematic error component.

The purpose of the invention is to improve the accuracy of verification.

The drawing shows a block diagram of an installation for testing analog-to-digital converters.

The circuit contains a memory block 1 with the first and second memory elements 2 and 3, a code-voltage converter 4, a code adder 5, an exemplary analog signal source b, a turnable analog-to-digital converter (ADC) 7, a recording block 8, arithmetic block 9, calculator 10 of the difference of codes, calculator 11 of the arithmetic mean 11, block 12 of control, generator of 13 pulses, first and second dividers 14 and 15 of the number of pulses, controlled source 16 of a functional analog signal and analog adder 17.

The installation works as follows.

From element 2, the checkpoint code is fed to adder 5 and source 6. Block 12 issues an address command Mi to element 3 to issue the first 1ЧФ code |, this code also goes to adder 5 and source 16. A sample analogue signal of the control point Uo from the source output 6 is summed up in adder 17 with a functional analog signal if | from the output of the source 16 and is fed to the first input of the converter 7. There is no high accuracy requirement on the source 16. Output code Nil ADC 7 and code NoH-MF | arrive at the inputs of the calculator 10, the output of which forms the difference

Au and N, 1 - (No + NФ |).

Block 12 provides for a given code YF | the operation of the ADC 7 in a given number m times. All generated m differences D | 1, ..., D | t are accumulated in the calculator 11. Then block 12 provides, by supplying a new address code M2, issuing from element 3 a new value of YF2 of the function code, and the input of the ADC 7 is supplied with a new exemplary analog signal U2, corresponding to the code NO - (- MF2, ADC 7 performs again gp conversions with the results N2i, ..., N2m, and the differences L21, ... L2t generated from the calculator 10 accumulate in the calculator 11. Block 12 provides the output K Nfl, ..., Nfk codes from element 3. For each IF code; m conversions are made of ADC 7 and m per accumulations of differences L, in the calculator 11. Thus, the total K m conversion is performed in ADC 7, and in

AND

The calculator accumulates the sum of i. S D, g,

which, after dividing Kt, i.e., after averaging over all L, gives an estimate of the systematic component D of the error of the A / D converter 7 at the control point given by the NO code

D-

km s

.in, 1

l,

N, (No + Nф |

This value is rewritten by the signal from the output of divider 15 to block 8 after K transformations have expired.

In this case, it is required that the K codes of the functional signal Nfl, ..., Nfc coming from element 3 are distributed uniformly over the interval of one quantum q of the ADC being calibrated, i.e. the values of the functional signal would form a finite linearly ordered set with discreteness

 . For example, if the quantum q is verifiable

The ADC is 100 µV and K 4, then the values of the functional signal can be: 0; 25; 50; 75 µV or -37.5; -12.5; +12.5; +37.5 µV. The setup ensures correct operation even if K of the functional signal codes are evenly distributed over the interval of several quanta of the ADC being calibrated.

The considered installation is universal - it is suitable for calibration of a DC voltage and current converter, alternating voltage or current, resistance, frequency, and other values. The setup also retains the possibility of further refinement for determining estimates of the standard deviation of the random component of the ADC error, its drift, correlation moments, etc.

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Claims (1)

Invention Formula An installation for checking analog-to-digital converters containing a calculator of code difference, the summing input of which is connected to the output of the inverted analog-to-digital converter, code-converter, consisting of a controlled source of an exemplary analog signal and a code adder, the first input of which is connected to the input of a controlled source of an exemplary analog signal and the output of the first storage element of the memory unit, the second input of the code adder connected to the output of the second storage element of the memory unit; the output of the code adder is connected to the subtractive input of the calculator of the difference of codes; the registration unit and the control unit, which differs from oh, in order to improve the accuracy of the verification, a controllable the functional analog signal source, the analog adder and the arithmetic average calculator, and the control unit are made of serially connected pulse generator and the first and second pulse number divisors, the output of the second memory element of the memory unit connected to the controlled analog input of the functional analog signal, output connected to the first input of the analog adder, the second input and the output of which are connected respectively to the output of the source of the exemplary aHajjoroBo signal and with the first entrance | The analogue-digital converter locator, the second input connected to the output of the pulse generator and the first input of the average arithmetic calculator, the second input of which is connected to the output of the code difference calculator, the first output of the second pulse number divider, and the inputs of the recording unit - dinene with the output of the arithmetic average calculator and with the second output of the second pulse number divider.