SU1742644A1 - Device for measuring dc voltage pulsing coefficient - Google Patents

Abstract

Use: measurement of pulsations in the systems for assessing the quality of electrical energy. The essence of the invention: the device contains: analog-to-digital converter (1), three buffer registers 2-4, two keys 5, 6, two buses of the zero level and a single level 7, 8, three comparators 9-11, two counters 12, 13, reversible counter 14, the bus of the signal under study 15, three drivers 16-18, two logical elements I 19, 20, two triggers 21,22, a pulse divider 23, a bus Sbrs 2.4. 1 il.

Description

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The invention relates to electrical measurements and can be used in systems for assessing the quality of electrical energy of mobile power sources for measuring a constant voltage ripple factor.

Methods are known for determining a pulsation coefficient using an electron beam oscilloscope, a memory oscilloscope, or an electronic voltmeter. When using oscilloscopes, it is possible to get errors due to subjective factors, moreover, it takes some time to take readings from oscillograms, which themselves have a rather high error. The use of electron tube voltmeters is coupled using a closed instrument input and isolating capacitors that isolate a variable voltage component. However due to

the frequency dependence of the capacitance value for different harmonic components of the impulsive voltage is introduced error of the measurement result.

Known digital amplitude value voltmeter with memory, containing an analog memory device consisting of two operational amplifiers, a capacitor and an electronic key, a differentiating device, a control device, an analog-to-digital converter and an indicator. The disadvantage of this device is relatively low accuracy at low pulsation frequencies due to samozar and memory capacitor, and at high frequencies because of the loss of time to charge the capacitor.

The closest in technical essence to the invention is a device for automatic control of indicators

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power quality, comprising a logometer and an indication unit, an A / D converter serially connected, first and second quadrants, first and second adders, maximum and minimum code selection blocks, nominal value adjuster, control unit, unit adjuster, square root extraction unit and a totalizer. The disadvantage of this device is the loss of accuracy as a result of sequential processing of information in quadrants, a square-root extraction unit, a logometer, and unequal measurement accuracy at different pulsation frequencies of the voltages under study.

The purpose of the invention is to improve the accuracy,

The purpose of the invention is achieved by the fact that in a device for measuring a constant voltage ripple coefficient, comprising an analog-digital converter, a first, second digital comparators, a stable frequency pulse generator, a first counter, a first logic element AND, the output of which is connected through a pulse divider with a counting the input of the first counter, the output of the stable frequency pulse generator is connected to the first input of the first logic element I, the input of the analog-digital converter is connected to the bus being studied voltage, the second inputs of the first and second digital comparators are interconnected, entered the first, second, third buffer registers, the third digital comparator, the second and third counters, the first, second, third shapers of short pulses, the second logical element And, the first and second the triggers, the first and second electronic keys, the inputs of the first key are connected to the zero level bus, and the outputs are connected to the inputs of the second and third buffer registers, the outputs of the second key, whose inputs are connected to the unit level bus, the analog-digital converter is connected to the inputs of the first buffer register, the outputs of which are connected to the inputs of the third buffer register and the second inputs of the second digital comparator, the output of which is connected to the recording input of the second buffer register through the third shaper of the short buffer, whose outputs are connected to the first inputs the second digital comparator and information inputs of the reversible counter, the reset input of which is connected to the reset bus, the recording input of the second buffer register, the control inputs of the first and second keys, input

Ca of the first trigger, the input of the record of the third buffer register, the output of the first short pulse generator, whose input is connected to the output of the first digital comparator, the first inputs of which are connected to the output of the third buffer register, the output of the first trigger And connected to the second input of the first logic element And, the output of which is connected with the input entry of the first buffer register, the reset input of the first counter is connected to the reset inputs of the second counter, the second trigger and the reset bus, the installation input of the second trigger with Connected to the counting inputs of the reversible counter, the second counter, the installation input of the first trigger, the output of the second logic element And is connected to the counting input of the second counter, the outputs of the first counter are connected to the first inputs of the second logic element And, the output of the stable frequency pulse generator is connected to the second input of the second logical element And, the output of the third digital comparator is connected to the third input of the second logic element And, the output of the second trigger is connected to the input of the second driver short pulses, the output of which is connected to the gate input of the reversible counter, the outputs of which are connected to the second inputs of the third digital comparator, the output of the first logic element I is connected to the write input of the first buffer register, the outputs of the second counter are the output of the device.

The drawing shows a diagram of the device.

The device contains analog-to-digital converter 1, first 2, second 3 and third 4 buffer registers, first 5, second 6 electronic keys, whose inputs are respectively connected by buses with zero 7 and one 8 level, first 9, second 10 and third 11 numerical comparators, the first 12, the second 13 and the reversing 14 counters, the signal bus 15, the first 16, the second 17, the third 18 short pulse drivers, the first 19 and second 20 logic elements And, the first 21 and second 22 triggers, the pulse divider 23, the bus 24 Reset , generator 25 stable pulses at .

The device works as follows.

The input signal from the bus 15 arrives at the input of the ADC 1. An instantaneous voltage value code is generated at its output. A signal is sent to the bus 2 The device is reset to its initial state. When this is done, counters 12-14,

the trigger 22 goes to the zero state, and the signal at its output disappears. The keys 5, 6 are opened briefly. Split 1 is spacing at register 3 bits, and register 0 at O bits of register 4. At the same time, trigger 21 enters the zero state and a signal appears at its inverse output, which prepares logic element 19 the second entrance. From the output of the pulse generator 25, an element 19 enters a pulse at the register entry input, into which the code of the instantaneous voltage value is output from the output of the ADC 1. This code is fed to the second inputs of the comparators 9 and 10. At the comparator 9, the zero code is compared with the register output 4 with the instantaneous voltage code and a signal appears at its first output, which is fed to the input of the former 16. An instantaneous voltage value code is entered into the register 4 by a pulse from the output of the former 16. At the same time, the instantaneous voltage code is compared with the highest possible code at the comparator 10. At its output, a signal arrives at the input of the former 18. In this case, the instantaneous voltage code is inputted from the output of the former 18 into register 3. Let the input signal voltage increase (time interval ti-ta), then at the next pulse from the output of the generator 25 to the register 2 a code is entered that is larger than the previous one. Therefore, a signal appears at the output of the comparator 9, and to register 4 a new code instantaneous voltage value. In register 3, the previous voltage code is saved, because the code at the first input is less than the code at the second input of the comparator 10. Until time t2, with each successive pulse from the generator output 25, coming through element 19, to the input of register 2, register 4 the voltage code corresponding to the highest voltage value is rewritten during the time ti-t2 is changed. Register 3 stores the code corresponding to the smallest instantaneous value for the same time period. Let the input voltage decrease (time interval n-ta). From time t2, the code on the first input of the comparator 9 is greater than the code on its second input. There is no output signal, and the register 4 is not overwritten. When the voltage code at the second input of the comparator 10 becomes less than the voltage code at the first input coming from the output of register 3, a signal appears at the output of the comparator 10. In the register 3, the code of the smallest voltage is entered. instantaneous voltage values, if each of them is less than the previous one. At time tz codes on

the outputs of comparator 10 are aligned, and rewriting in register 3 is terminated. With the next bursts and dips of the instantaneous voltage, the code of the highest voltage value is corrected.

0 and the correction of the code of the lowest voltage in the register 3, if the instantaneous value of the voltage is lower than the one registered earlier. From the beginning of the measurement, the pulses of the input of the generator 25 through

5, the element And 19 and the divider 23 are fed to a counting input counter 12, counting the measurement time. At the end of the measurement time, all bits of the output of counter 12 are observed 1. At the first input

0 element And 20 prepared by a high level from the output of the comparator 11, which has a larger code at the first input. Element And 20 opens and transmits pulses from the output of generator 25, arriving at the second input

5 elements And 20. At the same time, a signal arrives at the single input of the trigger 21, and the signal at its inverse output disappears. Element And 19 is closed, blocking the arrival of signals for recording instant codes.

0 voltage values in register 2 and preventing further receipt of pulses at the input of the counter 12. Together with the appearance of the first pulse at the output of the element 20, which is fed to the single input of the trigger 22, a signal appears at the output of the trigger 22. The imager 17 outputs a short pulse to the input of the record of the initial number of the counter 14, where the code of the smallest instant value is entered

0 voltage from the output of the register 3. At the same time from the output of the generator 25 through the element And 20 pulses arrive at the counting input of the counter 13 and summing the input of the reversible counter 14. The pulses go through 5 until the code at the output of the reversing counter 14 arrives at the second input comparator 11, does not coincide with the code of the greatest instantaneous value coming from the output of register 4 to the first input of comparator 11. At the same time, the signal at the output of comparator 11 disappears. Element AND 20 is closed at the second input, and the passage of pulses from the output of generator 25 is stopped.

5 The number of pulses received at the summing input of the reversible counter 14 and the counter 13 is determined by the expression N Max. - Mn. (1)

where is Mnaib. - the number corresponding to the code of the highest instantaneous voltage generated at the end of the measurement at the output of the register 4;

Mnaim - the number corresponding to the code of the smallest instantaneous voltage generated at the end of the measurement at the output of the register 3.

Considering the expression for determining the constant voltage ripple ratio in percent

,, Rnaib. Rnaim . 1PP 0 / Kpuls. 1 °

where is unaib. - the greatest instantaneous value of a pulsating voltage;

11th Mnaib. AU,

where L U is the quantization step of the ADC 1 over voltage;

inaim - the smallest instantaneous value of the pulsating voltage;

Unaim Mnaim. A u

where UH is the nominal value of the pulsating voltage,

The code at the output of the device is proportional to the ripple factor of the voltage under study.

Kpul.-Ki -N,%

where Ki is the proportionality coefficient; AU

Ki

Uh

100.

Thus, the proposed device makes it possible to estimate the constant voltage ripple factor. The measurement accuracy depends on the number of ADC bits and the generator frequency.

So, for example, with a generator frequency of 200 kHz and an eight-slot ADC, the measurement error of the pulsation coefficient for most of the manufactured DC generators does not exceed 0.004.

Claims (1)

Invention Formula A device for measuring the ripple factor of a constant voltage, containing an analog-digital converter, a first, second digital comparators, a stable frequency pulse generator, a first counter, a first logic element AND whose output is connected through a pulse divider, with a counting input of the first counter, an output a stable frequency pulse generator is connected to the first input of the first logic element I, the input of the analog-to-digital converter is connected to the bus of the voltage under study, the second inputs of the first and Secondly, digital comparators are interconnected, characterized in that, in order to improve accuracy, the first, second third buffer registers, the third digital comparator, the second and third counters, the first, second, third, short pulse drivers, and the second logic element I are entered into it , the first and second triggers, the first and second electronic keys, the inputs of the first key are connected to 0 by the zero-level bus, and the outputs are connected to the inputs of the second and third buffer registers, the outputs of the second key, the inputs of which are connected to the bus of the unit level, the output of the analog-digital converter, are connected to the inputs of the first buffer register, the outputs of which are connected to the inputs of the third buffer register and the second inputs of the second digital comparator, the output of which is through 0 the third short pulse driver is connected to the recording input of the second buffer register, the outputs of which are connected to the first inputs of the second digital comparator and information inputs of the recalculated counter, the reset input of which is connected to the reset bus, the recording input of the second buffer register, the control inputs of the first and second keys , reset input of the first trigger, input 0 records of the third buffer register, the output of the first short pulse generator, whose input is connected to the output of the first digital comparator, the first inputs of which are connected to the output of the third 5 of its buffer register, the output of the first trigger is connected to the second input of the first logic element And, the output of which is connected to the recording input the first buffer register, the reset input of the first counter co0 is united with the reset inputs of the second counter, the second trigger and the reset bus, the installation input of the second trigger is connected to the counting inputs s down counter, a second counter input of the first mounting 5 triggers, the output of the second logic element I is connected to the counting input of the second counter, the outputs of the first counter are connected to the first inputs of the second logic element I, the generator output of stable frequency pulses is connected to the second input of the second logic element I, the output of the third digital comparator is connected to the third input of the second logical alement And, the output of the second The 5 trigger is connected to the input of the second short pulse pulse, the output of the kopoporo is connected to the gate input of the reversing counter, the drives of which are connected to the second inputs of the third digital kilogram-paratprz, the output of the first logic gate AND is connected to the write input of the first buffer register, the outputs of the second counter are the output of the device