SU949802A1 - Device for measuring d-a converter non-linearity - Google Patents

Description

(54) DEVICE FOR MEASURING NONLINEARITY OF DIGITAL ANALOG CONVERTERS

one

The device relates to the measurement technique and can be used when checking digital-analog converters (D / A converters).

Devices for measuring the non-linearity of a D / A converter are known, comprising a pulse generator, a binary counter, an exemplary DAC or sawtooth generator (GPS), a subtracting amplifier and an oscilloscope 1.

A disadvantage of the known devices is the impossibility of minimizing the values of the error of linearity for a calibrated DAC.

A device for measuring non-linearity of digital-to-analog converters is also known, comprising a pulse counter, a saw-tooth voltage generator, a variable digital-analog converter, an analog-to-digital converter, a control unit, and a differential amplifier whose first input is connected to the output of the digital-analog converter that is being tested, the second input of a differential amplifier connected to the output of the sawtooth generator, the output of the differential amplifier is connected to

the output of the analog-digital converter, the output of the pulse counter is connected to the input of the digital-to-analog converter under test, the input of the sawtooth generator is connected to the first output of the control unit 2.

The disadvantages of this device include limited accuracy due to the additional error introduced into the measurement results by analogue ones.

, 0 blocks the device itself measuring the non-linearity of the DAC.

The purpose of the invention is to improve the accuracy of measuring the non-linearity of the DAC.

The goal is achieved by the fact that in a device for measuring nonlinearity

15 digital-to-analog converters containing a pulse counter, a saw-tooth voltage generator, a verifiable digital-to-analog converter, an analog-to-digital converter, a control unit

20 and a differential amplifier, the first input of which is connected to the output of a tested D / A converter, the second input of a differential amplifier is connected to the output of a sawtooth voltage generator, the output of a differential amplifier is connected to the output of an analog-digital converter, the output of a pulse counter is connected to the input of a tested digital-analog converter, the input of the sawtooth generator is connected to the first output of the control unit; an adjustable frequency generator is inserted; and an arithmetic unit whose input is connected to the output of an analog-digital converter, the output of the arithmetic unit is connected to the input of the control unit, the second output of which is connected to the input of the adjustable frequency generator, the output of which is connected to the input of the pulse counter and the delay unit whose output is connected to the second input to analog-to-digital converter.

FIG. 1 shows a block diagram of the device; in fig. 2 is a graph of linearity error versus clocking frequency.

The device contains a pulse counter t, a delay unit 2, a differential amplifier 3, an ADC 4, a variable frequency generator (VFD), GPS 6, an arithmetic unit 7, and a control unit 8. The diagram also shows the verifiable DAC 9.

The device works as follows.

The signals of oscillator 5 with the initial frequency fill the counter 1, the output code of which is fed to the calibrated DAC. The output signal Yx (t) of the DAC, proportional to Y (N), where N is the output code, is fed to the differential amplifier 3. The signal Y (t) from the GPS is fed to the second input of the amplifier. After each change of the code at the input of the DAC 9 and after the time the ty signal is set to - (i) to the level of static error, the A / D converter 4 measures the difference Yx (t) -YTi (t). The operation of the ADC is synchronized by pulses from the output of the VFG 5, received by them through the delay block 2. The measurement results are sent to the arithmetic unit 7, where only the extreme (largest and smallest) values are recorded over the full range of variation of the input codes TsAGS - the difference of values, (t) -Yn (t) lmax-S (rt) -Yn. (T) defined em is the largest in the range of the DAC error value D. The value of Dd depends on the relative position of Y () and Yf5 (N), and the minimization of Dl is achieved by changing the slope of the DAC characteristic (Fig. 2). In the diagram in FIG. 1 such minimization is performed by changing the slope

YX (N) DAC characteristics by changing the clocking frequency f (Fig. 2). The frequency f is varied so that it causes a decrease in the maximum over the range of the error Al. Change 4, caused by changing f, is monotonous and is controlled by the arithmetic unit. If the next frequency increment causes an increase in A, then the process

The measurement is stopped, and the penultimate value is incorrectly minimized linearity DL.

Claims (2)

1. “Questions of radio electronics. Ser. TPS, issue. 1, 1975, p. 74, fig. one. 2. USSR author's certificate No. 731584, cl. H 03 K 13/34, 30.04.80 (prototype). / / five / / / J 7 FIG. / N five