SU924705A1 - Device for taking logarithms of binary numbers - Google Patents

Description

The invention relates to computing and can be used as a digital generator of logarithmic function values. A device is known comprising number and result registers, a dividing unit, a comparison circuit, an accumulator shift register and a control unit 1. The disadvantage of this device is low speed. The closest in technical essence to the present invention is a device for logarifliruvaniya binary numbers, which contains the registration of the higher bits of the argument connected to the address inputs of two memory blocks and the register of the lower bits of the argument, the output of which is through the driver, the first switch and the .sum the device is connected to the output register 12. A disadvantage of the known device is the large amount of permanent memory required for storing the coefficient tables, which significantly reduces the scope of application of such devices. tv and allows to use them only in malorazr dnyh digital computer (not more than 12 - 16 bits). For an argument of length 24 binary bits, the volume of the tables is 119.2. bit., which prevents the use of this device as a node of a universal computer. The purpose of the invention is to reduce hardware costs. The goal is achieved in that the device containing the registers of the high and low bits, two memory blocks, the first shifter, the first switch, the adder and the output register, the input of which is connected to the output of the adder, the first input of which is connected to the output of the first switch, the input of which through the first shifter is connected to the output of the register of the least significant bits, the output of the register of the most significant bits is connected to the inputs of the memory blocks, contains the second and third shifters, the second, third and fourth switches: tori, dividing unit, synchronization lock and two buffer registers, the inputs of which are connected to the output of the adder, the outputs of the first and second buffer registers are connected respectively to the first inputs of the second and third switches, the outputs of which are connected to the first and second inputs of the dividing unit, the output of which is connected to the first input of the fourth switch whose output is connected to the second input of the adder, the second inputs of the second, third and fourth switches are connected respectively to the outputs of the second shifter of the first memory block and the small register The second bits of which are connected to the first inputs of the second liter of the third shifters, the second inputs of which are connected to the output of the register of the higher bits, the outputs of the second shift of the bodies and the second memory block are connected respectively to the second and third inputs of the first switch with the control inputs of the upper and lower order registers, buffer registers and switches. The calculation of the natural logarithm of the normalized argument X (1/2 v X 1) is performed in the proposed device based on the following relations L пХ cir U (x), where. u (, x) enX (j4 - Here Xd is the supporting part of the argument represented by the k bits of the argument, and dx is the increment of the argument represented by nk-binary bits, where n is the total number of bits required for representing the X argument. En XgU-l, which depend only on the reference part of the argument, are precomputed and entered in the tables implemented on the fixed memory blocks. The value of the parameter k to get all n binary bits before the result is taken from the expression k G (n - 1) / ST. Calculations carried out at, n It turns out that only 32 constants of 24 bits in length will need to be stored. Thus, for the considered device, as compared with the prototype device, a gain in the volume of memory blocks is more than 300 times. The drawing shows the block diagram of the proposed device. and 2, register 3 high bits, switch 4, block 5, fi, switch 6, adder 7, switch 8, output output register 9, registers 10 and 11 buffer, switch 12, register 13 low bits (argument), shifters 14 - 16, block 17 synchronization of The 15 and 1e shifters implement the 4Xo + iXr + LH operations, respectively, which consist in adding between the higher and lower order bits of the argument of the corresponding number of zeros (two and one). A device for logarithmic binary numbers works as follows. In the first clock cycle, the signal from the synchronization block 17 sends the address XQ from the output of the high-order register of argument 3 to the inputs of the memory blocks 1 and 2, the outputs of these memory blocks appear, respectively, 2 X and HRP, and at the outputs of the shifters 15 and 16, respectively, the values of 4X (j + + ЛХ and 2X0 + ДХ. The values of 2Х from the output of the first memory block 1 through the switch 4 by the signal from block 17 are fed to the input of the divisible division block 5, the value of 2x Q + l X from the output of the shifter 16 through the switch 12 on the signal from block 17, is fed to the input of the divider unit 5 d The output of which produces an intermediate result Pjf -2Xg / / (2X о + dX). Simultaneously, the value of DH from the output of the register of the lower bits of argument 13 through the switch b comes from the signal from block 17 to the second input of the adder 7, to the first the input of which receives the value 24X, formed at the output of the shifter 14, transmitted through the switch 8, according to a signal from block 17. A result equal to FZH is stored in the buffer register 10. In the second clock, the control result from the synchronization block 17 adds the intermediate result P, arriving at the adder 7 through the switch 6, and 4Xo + dX, coming from the output of the shifter 15 through the switch 8 to the input of the adder 7. The intermediate result - P / 2 4X0 + lX + P / 1 is stored in the second buffer register. In the third cycle, the value of the SSX from the output of the buffer register 10 through the switch 4. is fed to the input of the dividend block 5, the intermediate result P from the output of the buffer register 11 through the switch 12 is fed to the input of the divider of the division block 5. Intermediate result P 5 ZDH / P (2 from the output of dividing unit 5 through switch b is transmitted to the input of adder 7. To the other input of the latter, the value from the output of the second memory block 2 is transmitted to adder 7 through switch 8. Result P InPHO + Pj from the output of the adder 7 is fed to the input of the register result 9. .. Thus, the proposed device provides a positive

the effect is a reduction in the amount of memory blocks.

Formula of Invention

- A device for logarithmic binary numbers containing higher and lower order registers, two memory blocks, a first shifter, a first switch, an adder and an output register, the input of which is connected to the output of the adder, the first input of which is connected to the output of the first switch, the first input of which through the first shifter is connected to the output of the register of the lower bits, the output of the register of the higher bits is connected to the inputs of the memory blocks, characterized in that, in order to reduce hardware costs, it contains the second and third shifts The second, third and fourth switches, a block of synchronization dividing unit and two buffer registers, whose inputs are connected to the output of the adder, the outputs of the first and second buffer registers are connected, respectively, to the first inputs of the second and third switches, whose outputs are connected to the first and second inputs of the block division, the output of which is connected to the first input of the fourth switch, the output of which is connected to the second input of the adder, the second inputs of the second, third and fourth switches are connected respectively to the output The signals of the second shifter, the first memory block and the lower-order register, whose output is connected to the first inputs of the second and third shifters, the second inputs of which are connected to the output of the high-order register, the outputs of the second shifter and the second memory block 1g are connected respectively to the second and third the inputs of the first switch, the outputs of the synchronization block are connected respectively to the control inputs of the high and low bits, buffer registers and switches.

Sources of information taken into account in the examination

1. Authors certificate of the USSR 590733, cl. G About F 7/38, 1978.

2. Authors certificate of the USSR 593212, cl. G 06 F 7/38, 1978 (prototype). . .

Claims (1)

Claim - A device for the logarithm of binary numbers, containing high and low order registers, two memory blocks, the first shifter, the first switch, the adder and the output register, the input of which is connected to the output of the adder, the first input of which is connected to the output of the first switch, the first input of which is through the first the shifter is connected to the output of the register of the least significant bits, the output of the register of the highest bits is connected to the inputs of the memory blocks, characterized in that, in order to reduce hardware costs, it contains a second and third shift whether 20, second, third and fourth switches, a division unit, a synchronization unit and two buffer registers, the inputs of which are connected to the output of the adder, the outputs of the first and second buffer registers are connected, respectively, with the first inputs of the second and third switches, whose outputs are connected to the first and the second inputs of the division unit, the output of which is connected to the first input of the fourth switch, the output of which is connected to the second input of the adder, the second inputs of the second, third and fourth switches are connected respectively to the output the second shifter, the first memory block and the low-order register, the output of which is connected to the first inputs of the second and third shifters, the second inputs of which are connected to the output of the high-order register, the outputs of the second shifter and the second memory block are connected respectively to the second and third inputs of the first switch, the outputs of the synchronization unit are connected respectively to the control inputs of the registers of the upper and lower digits, buffer registers and switches.